cache.cc revision 13017
12810Srdreslin@umich.edu/* 212500Snikos.nikoleris@arm.com * Copyright (c) 2010-2018 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 4712349Snikos.nikoleris@arm.com * Nikos Nikoleris 482810Srdreslin@umich.edu */ 492810Srdreslin@umich.edu 502810Srdreslin@umich.edu/** 512810Srdreslin@umich.edu * @file 5211051Sandreas.hansson@arm.com * Cache definitions. 532810Srdreslin@umich.edu */ 542810Srdreslin@umich.edu 5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 562810Srdreslin@umich.edu 5712724Snikos.nikoleris@arm.com#include <cassert> 5812724Snikos.nikoleris@arm.com 5912724Snikos.nikoleris@arm.com#include "base/compiler.hh" 6012334Sgabeblack@google.com#include "base/logging.hh" 6112724Snikos.nikoleris@arm.com#include "base/trace.hh" 6211051Sandreas.hansson@arm.com#include "base/types.hh" 6311051Sandreas.hansson@arm.com#include "debug/Cache.hh" 6411051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6511288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6612724Snikos.nikoleris@arm.com#include "enums/Clusivity.hh" 6711051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6811051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6912724Snikos.nikoleris@arm.com#include "mem/cache/tags/base.hh" 7012724Snikos.nikoleris@arm.com#include "mem/cache/write_queue_entry.hh" 7112724Snikos.nikoleris@arm.com#include "mem/request.hh" 7212724Snikos.nikoleris@arm.com#include "params/Cache.hh" 7311051Sandreas.hansson@arm.com 7411053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 7511053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 7612724Snikos.nikoleris@arm.com doFastWrites(true) 7711051Sandreas.hansson@arm.com{ 7811051Sandreas.hansson@arm.com} 7911051Sandreas.hansson@arm.com 8011051Sandreas.hansson@arm.comvoid 8111601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, 8211601Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 8311051Sandreas.hansson@arm.com{ 8412724Snikos.nikoleris@arm.com BaseCache::satisfyRequest(pkt, blk); 8511051Sandreas.hansson@arm.com 8612724Snikos.nikoleris@arm.com if (pkt->isRead()) { 8711600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 8811600Sandreas.hansson@arm.com if (pkt->fromCache()) { 8911051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 9011051Sandreas.hansson@arm.com // special handling for coherent block requests from 9111051Sandreas.hansson@arm.com // upper-level caches 9211284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 9311051Sandreas.hansson@arm.com // sanity check 9411051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 9511051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 9611602Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 9711051Sandreas.hansson@arm.com 9811051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 9911284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 10011051Sandreas.hansson@arm.com if (blk->isDirty()) { 10111284Sandreas.hansson@arm.com pkt->setCacheResponding(); 10211602Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 10311051Sandreas.hansson@arm.com } 10411051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 10511284Sandreas.hansson@arm.com !pkt->hasSharers() && 10611051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 10711284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 10811284Sandreas.hansson@arm.com // request if: 10911284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 11011051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 11111051Sandreas.hansson@arm.com // signaling another read request 11211051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 11311284Sandreas.hansson@arm.com // would have set hasSharers flag when 11411284Sandreas.hansson@arm.com // snooping the packet) 11511284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 11611284Sandreas.hansson@arm.com // copy of the line 11711051Sandreas.hansson@arm.com if (blk->isDirty()) { 11811051Sandreas.hansson@arm.com // special considerations if we're owner: 11911051Sandreas.hansson@arm.com if (!deferred_response) { 12011284Sandreas.hansson@arm.com // respond with the line in Modified state 12111284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 12211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 12311197Sandreas.hansson@arm.com 12411601Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 12511601Sandreas.hansson@arm.com // keep the block in the Exclusive state, 12611601Sandreas.hansson@arm.com // and pass it upwards as Modified 12711601Sandreas.hansson@arm.com // (writable and dirty), hence we have 12811601Sandreas.hansson@arm.com // multiple caches, all on the same path 12911601Sandreas.hansson@arm.com // towards memory, all considering the 13011601Sandreas.hansson@arm.com // same block writable, but only one 13111601Sandreas.hansson@arm.com // considering it Modified 13211197Sandreas.hansson@arm.com 13311601Sandreas.hansson@arm.com // we get away with multiple caches (on 13411601Sandreas.hansson@arm.com // the same path to memory) considering 13511601Sandreas.hansson@arm.com // the block writeable as we always enter 13611601Sandreas.hansson@arm.com // the cache hierarchy through a cache, 13711601Sandreas.hansson@arm.com // and first snoop upwards in all other 13811601Sandreas.hansson@arm.com // branches 13911601Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 14011051Sandreas.hansson@arm.com } else { 14111051Sandreas.hansson@arm.com // if we're responding after our own miss, 14211051Sandreas.hansson@arm.com // there's a window where the recipient didn't 14311051Sandreas.hansson@arm.com // know it was getting ownership and may not 14411051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 14511284Sandreas.hansson@arm.com // have to respond with a shared line 14611284Sandreas.hansson@arm.com pkt->setHasSharers(); 14711051Sandreas.hansson@arm.com } 14811051Sandreas.hansson@arm.com } 14911051Sandreas.hansson@arm.com } else { 15011051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 15111284Sandreas.hansson@arm.com pkt->setHasSharers(); 15211051Sandreas.hansson@arm.com } 15311051Sandreas.hansson@arm.com } 15411051Sandreas.hansson@arm.com } 15511051Sandreas.hansson@arm.com} 15611051Sandreas.hansson@arm.com 15711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 15811051Sandreas.hansson@arm.com// 15911051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 16011051Sandreas.hansson@arm.com// 16111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 16211051Sandreas.hansson@arm.com 16311051Sandreas.hansson@arm.combool 16411051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 16511051Sandreas.hansson@arm.com PacketList &writebacks) 16611051Sandreas.hansson@arm.com{ 16711051Sandreas.hansson@arm.com 16811051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 16912724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 17012724Snikos.nikoleris@arm.com 17112724Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 17212724Snikos.nikoleris@arm.com "Should never see a write in a read-only cache %s\n", 17312724Snikos.nikoleris@arm.com name()); 17412724Snikos.nikoleris@arm.com 17512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 17611051Sandreas.hansson@arm.com 17711051Sandreas.hansson@arm.com // flush and invalidate any existing block 17811051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 17911051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 18012723Snikos.nikoleris@arm.com evictBlock(old_blk, writebacks); 18111051Sandreas.hansson@arm.com } 18211051Sandreas.hansson@arm.com 18311484Snikos.nikoleris@arm.com blk = nullptr; 18411051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 18511051Sandreas.hansson@arm.com lat = lookupLatency; 18611051Sandreas.hansson@arm.com return false; 18711051Sandreas.hansson@arm.com } 18811051Sandreas.hansson@arm.com 18912724Snikos.nikoleris@arm.com return BaseCache::access(pkt, blk, lat, writebacks); 19011601Sandreas.hansson@arm.com} 19111601Sandreas.hansson@arm.com 19211601Sandreas.hansson@arm.comvoid 19311051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 19411051Sandreas.hansson@arm.com{ 19511051Sandreas.hansson@arm.com while (!writebacks.empty()) { 19611051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 19711051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 19812345Snikos.nikoleris@arm.com // write buffer. 19912345Snikos.nikoleris@arm.com 20012345Snikos.nikoleris@arm.com // Call isCachedAbove for Writebacks, CleanEvicts and 20112345Snikos.nikoleris@arm.com // WriteCleans to discover if the block is cached above. 20211051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 20311051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 20411051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 20511051Sandreas.hansson@arm.com // packet destructor will delete the request object because 20611051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 20711051Sandreas.hansson@arm.com // response. 20811051Sandreas.hansson@arm.com delete wbPkt; 20911199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 21011199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 21111199Sandreas.hansson@arm.com // still cached above 21211199Sandreas.hansson@arm.com assert(writebackClean); 21311199Sandreas.hansson@arm.com delete wbPkt; 21411051Sandreas.hansson@arm.com } else { 21512345Snikos.nikoleris@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty || 21612345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean); 21711051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 21811051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 21911051Sandreas.hansson@arm.com // address in the snoop filter below. 22011051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 22111051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 22211051Sandreas.hansson@arm.com } 22311051Sandreas.hansson@arm.com } else { 22411051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 22511051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 22611051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 22711051Sandreas.hansson@arm.com // below. 22811051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 22911051Sandreas.hansson@arm.com } 23011051Sandreas.hansson@arm.com writebacks.pop_front(); 23111051Sandreas.hansson@arm.com } 23211051Sandreas.hansson@arm.com} 23311051Sandreas.hansson@arm.com 23411130Sali.jafri@arm.comvoid 23511130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 23611130Sali.jafri@arm.com{ 23711130Sali.jafri@arm.com while (!writebacks.empty()) { 23811130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 23911130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 24011130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 24111130Sali.jafri@arm.com // and discard CleanEvicts. 24211130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 24312345Snikos.nikoleris@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty || 24412345Snikos.nikoleris@arm.com wbPkt->cmd == MemCmd::WriteClean) { 24511130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 24611130Sali.jafri@arm.com // so that the Writeback does not reset the bit 24711130Sali.jafri@arm.com // corresponding to this address in the snoop filter 24811130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 24911130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 25011130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 25112724Snikos.nikoleris@arm.com memSidePort.sendAtomic(wbPkt); 25211130Sali.jafri@arm.com } 25311130Sali.jafri@arm.com } else { 25411130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 25511130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 25611130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 25711130Sali.jafri@arm.com // below. 25812724Snikos.nikoleris@arm.com memSidePort.sendAtomic(wbPkt); 25911130Sali.jafri@arm.com } 26011130Sali.jafri@arm.com writebacks.pop_front(); 26111130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 26211130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 26311130Sali.jafri@arm.com // does not require a response. 26411130Sali.jafri@arm.com delete wbPkt; 26511130Sali.jafri@arm.com } 26611130Sali.jafri@arm.com} 26711130Sali.jafri@arm.com 26811051Sandreas.hansson@arm.com 26911051Sandreas.hansson@arm.comvoid 27011051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 27111051Sandreas.hansson@arm.com{ 27211744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s\n", __func__, pkt->print()); 27311051Sandreas.hansson@arm.com 27411276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 27511276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 27611276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 27711276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 27811276Sandreas.hansson@arm.com outstandingSnoop.end(); 27911276Sandreas.hansson@arm.com 28011276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 28111276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 28211276Sandreas.hansson@arm.com // forward it 28311051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 28411276Sandreas.hansson@arm.com 28511276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 28611276Sandreas.hansson@arm.com 28711276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 28811276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 28911051Sandreas.hansson@arm.com recvTimingResp(pkt); 29011051Sandreas.hansson@arm.com return; 29111051Sandreas.hansson@arm.com } 29211051Sandreas.hansson@arm.com 29311051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 29411051Sandreas.hansson@arm.com // upper level cache. 29511051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 29611051Sandreas.hansson@arm.com // we charge also headerDelay. 29711051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 29811051Sandreas.hansson@arm.com // Reset the timing of the packet. 29911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 30012724Snikos.nikoleris@arm.com memSidePort.schedTimingSnoopResp(pkt, snoop_resp_time); 30111051Sandreas.hansson@arm.com} 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.comvoid 30411051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 30511051Sandreas.hansson@arm.com{ 30611051Sandreas.hansson@arm.com // Cache line clearing instructions 30711051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 30811051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 30911051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 31011051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 31111051Sandreas.hansson@arm.com } 31211051Sandreas.hansson@arm.com} 31311051Sandreas.hansson@arm.com 31412630Snikos.nikoleris@arm.comvoid 31512720Snikos.nikoleris@arm.comCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 31612720Snikos.nikoleris@arm.com{ 31712720Snikos.nikoleris@arm.com // should never be satisfying an uncacheable access as we 31812720Snikos.nikoleris@arm.com // flush and invalidate any existing block as part of the 31912720Snikos.nikoleris@arm.com // lookup 32012720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 32112720Snikos.nikoleris@arm.com 32212724Snikos.nikoleris@arm.com BaseCache::handleTimingReqHit(pkt, blk, request_time); 32312720Snikos.nikoleris@arm.com} 32412720Snikos.nikoleris@arm.com 32512720Snikos.nikoleris@arm.comvoid 32612720Snikos.nikoleris@arm.comCache::handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk, Tick forward_time, 32712720Snikos.nikoleris@arm.com Tick request_time) 32812720Snikos.nikoleris@arm.com{ 32912724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 33012724Snikos.nikoleris@arm.com // ignore any existing MSHR if we are dealing with an 33112724Snikos.nikoleris@arm.com // uncacheable request 33212724Snikos.nikoleris@arm.com 33312724Snikos.nikoleris@arm.com // should have flushed and have no valid block 33412724Snikos.nikoleris@arm.com assert(!blk || !blk->isValid()); 33512724Snikos.nikoleris@arm.com 33612724Snikos.nikoleris@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 33712724Snikos.nikoleris@arm.com 33812724Snikos.nikoleris@arm.com if (pkt->isWrite()) { 33912724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 34012724Snikos.nikoleris@arm.com } else { 34112724Snikos.nikoleris@arm.com assert(pkt->isRead()); 34212724Snikos.nikoleris@arm.com 34312724Snikos.nikoleris@arm.com // uncacheable accesses always allocate a new MSHR 34412724Snikos.nikoleris@arm.com 34512724Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 34612724Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 34712724Snikos.nikoleris@arm.com // lookupLatency component. 34812724Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 34912724Snikos.nikoleris@arm.com } 35012724Snikos.nikoleris@arm.com 35112724Snikos.nikoleris@arm.com return; 35212724Snikos.nikoleris@arm.com } 35312724Snikos.nikoleris@arm.com 35412720Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 35512720Snikos.nikoleris@arm.com 35612724Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, pkt->isSecure()); 35712720Snikos.nikoleris@arm.com 35812720Snikos.nikoleris@arm.com // Software prefetch handling: 35912720Snikos.nikoleris@arm.com // To keep the core from waiting on data it won't look at 36012720Snikos.nikoleris@arm.com // anyway, send back a response with dummy data. Miss handling 36112720Snikos.nikoleris@arm.com // will continue asynchronously. Unfortunately, the core will 36212720Snikos.nikoleris@arm.com // insist upon freeing original Packet/Request, so we have to 36312720Snikos.nikoleris@arm.com // create a new pair with a different lifecycle. Note that this 36412720Snikos.nikoleris@arm.com // processing happens before any MSHR munging on the behalf of 36512720Snikos.nikoleris@arm.com // this request because this new Request will be the one stored 36612720Snikos.nikoleris@arm.com // into the MSHRs, not the original. 36712720Snikos.nikoleris@arm.com if (pkt->cmd.isSWPrefetch()) { 36812720Snikos.nikoleris@arm.com assert(pkt->needsResponse()); 36912720Snikos.nikoleris@arm.com assert(pkt->req->hasPaddr()); 37012720Snikos.nikoleris@arm.com assert(!pkt->req->isUncacheable()); 37112720Snikos.nikoleris@arm.com 37212720Snikos.nikoleris@arm.com // There's no reason to add a prefetch as an additional target 37312720Snikos.nikoleris@arm.com // to an existing MSHR. If an outstanding request is already 37412720Snikos.nikoleris@arm.com // in progress, there is nothing for the prefetch to do. 37512720Snikos.nikoleris@arm.com // If this is the case, we don't even create a request at all. 37612720Snikos.nikoleris@arm.com PacketPtr pf = nullptr; 37712720Snikos.nikoleris@arm.com 37812720Snikos.nikoleris@arm.com if (!mshr) { 37912720Snikos.nikoleris@arm.com // copy the request and create a new SoftPFReq packet 38012749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(pkt->req->getPaddr(), 38112749Sgiacomo.travaglini@arm.com pkt->req->getSize(), 38212749Sgiacomo.travaglini@arm.com pkt->req->getFlags(), 38312749Sgiacomo.travaglini@arm.com pkt->req->masterId()); 38412720Snikos.nikoleris@arm.com pf = new Packet(req, pkt->cmd); 38512720Snikos.nikoleris@arm.com pf->allocate(); 38612720Snikos.nikoleris@arm.com assert(pf->getAddr() == pkt->getAddr()); 38712720Snikos.nikoleris@arm.com assert(pf->getSize() == pkt->getSize()); 38812720Snikos.nikoleris@arm.com } 38912720Snikos.nikoleris@arm.com 39012720Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 39112720Snikos.nikoleris@arm.com 39212720Snikos.nikoleris@arm.com // request_time is used here, taking into account lat and the delay 39312720Snikos.nikoleris@arm.com // charged if the packet comes from the xbar. 39412724Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, request_time, true); 39512720Snikos.nikoleris@arm.com 39612720Snikos.nikoleris@arm.com // If an outstanding request is in progress (we found an 39712720Snikos.nikoleris@arm.com // MSHR) this is set to null 39812720Snikos.nikoleris@arm.com pkt = pf; 39912720Snikos.nikoleris@arm.com } 40012720Snikos.nikoleris@arm.com 40112724Snikos.nikoleris@arm.com BaseCache::handleTimingReqMiss(pkt, mshr, blk, forward_time, request_time); 40212720Snikos.nikoleris@arm.com} 40312720Snikos.nikoleris@arm.com 40412720Snikos.nikoleris@arm.comvoid 40511051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 40611051Sandreas.hansson@arm.com{ 40711830Sbaz21@cam.ac.uk DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print()); 40811051Sandreas.hansson@arm.com 40911051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 41011051Sandreas.hansson@arm.com 41111284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 41211051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 41311284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 41411284Sandreas.hansson@arm.com // in Modified or Owned state 41511744Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 41611744Snikos.nikoleris@arm.com pkt->print()); 41711051Sandreas.hansson@arm.com 41811284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 41911284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 42011284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 42111284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 42211284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 42311334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 42411284Sandreas.hansson@arm.com 42511334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 42611334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 42711334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 42811334Sandreas.hansson@arm.com // cache hierarchy to another 42911284Sandreas.hansson@arm.com 43011334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 43111334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 43211334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 43311334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 43411334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 43511334Sandreas.hansson@arm.com // path to memory 43611051Sandreas.hansson@arm.com 43711334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 43811334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 43911334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 44011334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 44111051Sandreas.hansson@arm.com 44211334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 44311334Sandreas.hansson@arm.com // not yet paid for 44411334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 44511051Sandreas.hansson@arm.com 44611334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 44711334Sandreas.hansson@arm.com // other caches in the system know that the another cache 44811334Sandreas.hansson@arm.com // is responding, because we have found the authorative 44911334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 45011334Sandreas.hansson@arm.com // data 45111334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 45211334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 45311051Sandreas.hansson@arm.com 45411334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 45511334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 45611334Sandreas.hansson@arm.com // every cache in the system 45712724Snikos.nikoleris@arm.com bool M5_VAR_USED success = memSidePort.sendTimingReq(snoop_pkt); 45811334Sandreas.hansson@arm.com // express snoops always succeed 45911334Sandreas.hansson@arm.com assert(success); 46011334Sandreas.hansson@arm.com 46111334Sandreas.hansson@arm.com // main memory will delete the snoop packet 46211051Sandreas.hansson@arm.com 46311284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 46411284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 46511190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 46611051Sandreas.hansson@arm.com 46711334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 46811334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 46911334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 47011334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 47111334Sandreas.hansson@arm.com // invalidated 47212630Snikos.nikoleris@arm.com return; 47311051Sandreas.hansson@arm.com } 47411051Sandreas.hansson@arm.com 47512724Snikos.nikoleris@arm.com BaseCache::recvTimingReq(pkt); 47611051Sandreas.hansson@arm.com} 47711051Sandreas.hansson@arm.com 47811051Sandreas.hansson@arm.comPacketPtr 47911452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 48011452Sandreas.hansson@arm.com bool needsWritable) const 48111051Sandreas.hansson@arm.com{ 48211452Sandreas.hansson@arm.com // should never see evictions here 48311452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 48411452Sandreas.hansson@arm.com 48511051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 48611051Sandreas.hansson@arm.com 48711452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 48811745Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade()) || 48912349Snikos.nikoleris@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) { 49011452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 49111452Sandreas.hansson@arm.com // that missed completely just go through as is 49211452Sandreas.hansson@arm.com return nullptr; 49311051Sandreas.hansson@arm.com } 49411051Sandreas.hansson@arm.com 49511051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 49611051Sandreas.hansson@arm.com 49711051Sandreas.hansson@arm.com MemCmd cmd; 49811051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 49911051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 50011051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 50111051Sandreas.hansson@arm.com // which will clobber the owned copy. 50211051Sandreas.hansson@arm.com const bool useUpgrades = true; 50311747Snikos.nikoleris@arm.com if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 50411747Snikos.nikoleris@arm.com assert(!blkValid || !blk->isWritable()); 50511747Snikos.nikoleris@arm.com // forward as invalidate to all other caches, this gives us 50611747Snikos.nikoleris@arm.com // the line in Exclusive state, and invalidates all other 50711747Snikos.nikoleris@arm.com // copies 50811747Snikos.nikoleris@arm.com cmd = MemCmd::InvalidateReq; 50911747Snikos.nikoleris@arm.com } else if (blkValid && useUpgrades) { 51011284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 51111284Sandreas.hansson@arm.com // it to be writable 51211284Sandreas.hansson@arm.com assert(needsWritable); 51311051Sandreas.hansson@arm.com assert(!blk->isWritable()); 51411051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 51511051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 51611051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 51711051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 51811051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 51911051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 52011051Sandreas.hansson@arm.com // all caches not being on the same local bus. 52111051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 52211051Sandreas.hansson@arm.com } else { 52311051Sandreas.hansson@arm.com // block is invalid 52412425Snikos.nikoleris@arm.com 52512425Snikos.nikoleris@arm.com // If the request does not need a writable there are two cases 52612425Snikos.nikoleris@arm.com // where we need to ensure the response will not fetch the 52712425Snikos.nikoleris@arm.com // block in dirty state: 52812425Snikos.nikoleris@arm.com // * this cache is read only and it does not perform 52912425Snikos.nikoleris@arm.com // writebacks, 53012425Snikos.nikoleris@arm.com // * this cache is mostly exclusive and will not fill (since 53112425Snikos.nikoleris@arm.com // it does not fill it will have to writeback the dirty data 53212425Snikos.nikoleris@arm.com // immediately which generates uneccesary writebacks). 53312425Snikos.nikoleris@arm.com bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl; 53411284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 53512425Snikos.nikoleris@arm.com (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 53611051Sandreas.hansson@arm.com } 53711051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 53811051Sandreas.hansson@arm.com 53911284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 54011284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 54111284Sandreas.hansson@arm.com // downstream 54211602Sandreas.hansson@arm.com if (cpu_pkt->hasSharers() && !needsWritable) { 54311051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 54411051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 54511051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 54611284Sandreas.hansson@arm.com // assuming the block has sharers 54711284Sandreas.hansson@arm.com pkt->setHasSharers(); 54811744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n", 54911744Snikos.nikoleris@arm.com __func__, cpu_pkt->print(), pkt->print()); 55011051Sandreas.hansson@arm.com } 55111051Sandreas.hansson@arm.com 55211051Sandreas.hansson@arm.com // the packet should be block aligned 55311892Snikos.nikoleris@arm.com assert(pkt->getAddr() == pkt->getBlockAddr(blkSize)); 55411051Sandreas.hansson@arm.com 55511051Sandreas.hansson@arm.com pkt->allocate(); 55611744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(), 55711744Snikos.nikoleris@arm.com cpu_pkt->print()); 55811051Sandreas.hansson@arm.com return pkt; 55911051Sandreas.hansson@arm.com} 56011051Sandreas.hansson@arm.com 56111051Sandreas.hansson@arm.com 56212721Snikos.nikoleris@arm.comCycles 56313017Snikos.nikoleris@arm.comCache::handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 56412721Snikos.nikoleris@arm.com PacketList &writebacks) 56512721Snikos.nikoleris@arm.com{ 56612721Snikos.nikoleris@arm.com // deal with the packets that go through the write path of 56712721Snikos.nikoleris@arm.com // the cache, i.e. any evictions and writes 56812721Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean || 56912721Snikos.nikoleris@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 57012724Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort.sendAtomic(pkt)); 57112721Snikos.nikoleris@arm.com 57212721Snikos.nikoleris@arm.com // at this point, if the request was an uncacheable write 57312721Snikos.nikoleris@arm.com // request, it has been satisfied by a memory below and the 57412721Snikos.nikoleris@arm.com // packet carries the response back 57512721Snikos.nikoleris@arm.com assert(!(pkt->req->isUncacheable() && pkt->isWrite()) || 57612721Snikos.nikoleris@arm.com pkt->isResponse()); 57712721Snikos.nikoleris@arm.com 57812721Snikos.nikoleris@arm.com return latency; 57912721Snikos.nikoleris@arm.com } 58012721Snikos.nikoleris@arm.com 58112721Snikos.nikoleris@arm.com // only misses left 58212721Snikos.nikoleris@arm.com 58312721Snikos.nikoleris@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 58412721Snikos.nikoleris@arm.com 58512721Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 58612721Snikos.nikoleris@arm.com 58712721Snikos.nikoleris@arm.com if (is_forward) { 58812721Snikos.nikoleris@arm.com // just forwarding the same request to the next level 58912721Snikos.nikoleris@arm.com // no local cache operation involved 59012721Snikos.nikoleris@arm.com bus_pkt = pkt; 59112721Snikos.nikoleris@arm.com } 59212721Snikos.nikoleris@arm.com 59312721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__, 59412721Snikos.nikoleris@arm.com bus_pkt->print()); 59512721Snikos.nikoleris@arm.com 59612721Snikos.nikoleris@arm.com#if TRACING_ON 59712721Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 59812721Snikos.nikoleris@arm.com#endif 59912721Snikos.nikoleris@arm.com 60012724Snikos.nikoleris@arm.com Cycles latency = ticksToCycles(memSidePort.sendAtomic(bus_pkt)); 60112721Snikos.nikoleris@arm.com 60212721Snikos.nikoleris@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 60312721Snikos.nikoleris@arm.com 60412721Snikos.nikoleris@arm.com // We are now dealing with the response handling 60512721Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__, 60612721Snikos.nikoleris@arm.com bus_pkt->print(), old_state); 60712721Snikos.nikoleris@arm.com 60812721Snikos.nikoleris@arm.com // If packet was a forward, the response (if any) is already 60912721Snikos.nikoleris@arm.com // in place in the bus_pkt == pkt structure, so we don't need 61012721Snikos.nikoleris@arm.com // to do anything. Otherwise, use the separate bus_pkt to 61112721Snikos.nikoleris@arm.com // generate response to pkt and then delete it. 61212721Snikos.nikoleris@arm.com if (!is_forward) { 61312721Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 61412721Snikos.nikoleris@arm.com assert(bus_pkt->isResponse()); 61512721Snikos.nikoleris@arm.com if (bus_pkt->isError()) { 61612721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 61712721Snikos.nikoleris@arm.com pkt->copyError(bus_pkt); 61812721Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 61912721Snikos.nikoleris@arm.com // note the use of pkt, not bus_pkt here. 62012721Snikos.nikoleris@arm.com 62112721Snikos.nikoleris@arm.com // write-line request to the cache that promoted 62212721Snikos.nikoleris@arm.com // the write to a whole line 62312721Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, 62412721Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 62512721Snikos.nikoleris@arm.com assert(blk != NULL); 62612721Snikos.nikoleris@arm.com is_invalidate = false; 62712721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 62812721Snikos.nikoleris@arm.com } else if (bus_pkt->isRead() || 62912721Snikos.nikoleris@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 63012721Snikos.nikoleris@arm.com // we're updating cache state to allow us to 63112721Snikos.nikoleris@arm.com // satisfy the upstream request from the cache 63212721Snikos.nikoleris@arm.com blk = handleFill(bus_pkt, blk, writebacks, 63312721Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 63412721Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 63512721Snikos.nikoleris@arm.com maintainClusivity(pkt->fromCache(), blk); 63612721Snikos.nikoleris@arm.com } else { 63712721Snikos.nikoleris@arm.com // we're satisfying the upstream request without 63812721Snikos.nikoleris@arm.com // modifying cache state, e.g., a write-through 63912721Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 64012721Snikos.nikoleris@arm.com } 64112721Snikos.nikoleris@arm.com } 64212721Snikos.nikoleris@arm.com delete bus_pkt; 64312721Snikos.nikoleris@arm.com } 64412721Snikos.nikoleris@arm.com 64512721Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 64612721Snikos.nikoleris@arm.com invalidateBlock(blk); 64712721Snikos.nikoleris@arm.com } 64812721Snikos.nikoleris@arm.com 64912721Snikos.nikoleris@arm.com return latency; 65012721Snikos.nikoleris@arm.com} 65112721Snikos.nikoleris@arm.com 65211051Sandreas.hansson@arm.comTick 65311051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 65411051Sandreas.hansson@arm.com{ 65511051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 65611051Sandreas.hansson@arm.com 65712724Snikos.nikoleris@arm.com return BaseCache::recvAtomic(pkt); 65811051Sandreas.hansson@arm.com} 65911051Sandreas.hansson@arm.com 66011051Sandreas.hansson@arm.com 66111051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 66211051Sandreas.hansson@arm.com// 66311051Sandreas.hansson@arm.com// Response handling: responses from the memory side 66411051Sandreas.hansson@arm.com// 66511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 66611051Sandreas.hansson@arm.com 66711051Sandreas.hansson@arm.com 66811051Sandreas.hansson@arm.comvoid 66912719Snikos.nikoleris@arm.comCache::serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, CacheBlk *blk, 67012719Snikos.nikoleris@arm.com PacketList &writebacks) 67111051Sandreas.hansson@arm.com{ 67211051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 67312719Snikos.nikoleris@arm.com // First offset for critical word first calculations 67412719Snikos.nikoleris@arm.com const int initial_offset = initial_tgt->pkt->getOffset(blkSize); 67512719Snikos.nikoleris@arm.com 67612719Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 67711051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 67811051Sandreas.hansson@arm.com // requests to be discarded 67911136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 68011051Sandreas.hansson@arm.com 68111742Snikos.nikoleris@arm.com MSHR::TargetList targets = mshr->extractServiceableTargets(pkt); 68211742Snikos.nikoleris@arm.com for (auto &target: targets) { 68311742Snikos.nikoleris@arm.com Packet *tgt_pkt = target.pkt; 68411742Snikos.nikoleris@arm.com switch (target.source) { 68511051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 68611051Sandreas.hansson@arm.com Tick completion_time; 68711051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 68811051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 68911051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 69011051Sandreas.hansson@arm.com 69111051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 69211051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 69311483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 69411483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 69511483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 69611483Snikos.nikoleris@arm.com // deallocate it. 69711051Sandreas.hansson@arm.com delete tgt_pkt; 69811051Sandreas.hansson@arm.com break; // skip response 69911051Sandreas.hansson@arm.com } 70011051Sandreas.hansson@arm.com 70111051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 70211051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 70311051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 70411051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 70511051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 70611051Sandreas.hansson@arm.com // from above. 70711051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 70811051Sandreas.hansson@arm.com assert(!is_error); 70911284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 71011284Sandreas.hansson@arm.com // any deferred targets if possible 71111284Sandreas.hansson@arm.com mshr->promoteWritable(); 71211051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 71311741Snikos.nikoleris@arm.com blk = handleFill(tgt_pkt, blk, writebacks, 71411742Snikos.nikoleris@arm.com targets.allocOnFill); 71512719Snikos.nikoleris@arm.com assert(blk); 71611051Sandreas.hansson@arm.com 71712794Snikos.nikoleris@arm.com // discard the invalidation response 71811136Sandreas.hansson@arm.com is_invalidate = false; 71911051Sandreas.hansson@arm.com } 72011051Sandreas.hansson@arm.com 72112794Snikos.nikoleris@arm.com if (blk && blk->isValid() && !mshr->isForward) { 72211601Sandreas.hansson@arm.com satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade()); 72311051Sandreas.hansson@arm.com 72411051Sandreas.hansson@arm.com // How many bytes past the first request is this one 72511051Sandreas.hansson@arm.com int transfer_offset = 72611051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 72711051Sandreas.hansson@arm.com if (transfer_offset < 0) { 72811051Sandreas.hansson@arm.com transfer_offset += blkSize; 72911051Sandreas.hansson@arm.com } 73011051Sandreas.hansson@arm.com 73111051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 73211051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 73311051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 73411051Sandreas.hansson@arm.com // the core. 73511051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 73611051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 73711051Sandreas.hansson@arm.com 73811051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 73911051Sandreas.hansson@arm.com 74011051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 74111051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 74211742Snikos.nikoleris@arm.com completion_time - target.recvTime; 74311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 74411051Sandreas.hansson@arm.com // failed StoreCond upgrade 74511051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 74611051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 74711051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 74811051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 74911051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 75011051Sandreas.hansson@arm.com // the core. 75111051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 75211051Sandreas.hansson@arm.com pkt->payloadDelay; 75311051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 75411051Sandreas.hansson@arm.com } else { 75511750Snikos.nikoleris@arm.com // We are about to send a response to a cache above 75611750Snikos.nikoleris@arm.com // that asked for an invalidation; we need to 75711750Snikos.nikoleris@arm.com // invalidate our copy immediately as the most 75811750Snikos.nikoleris@arm.com // up-to-date copy of the block will now be in the 75911750Snikos.nikoleris@arm.com // cache above. It will also prevent this cache from 76011750Snikos.nikoleris@arm.com // responding (if the block was previously dirty) to 76111750Snikos.nikoleris@arm.com // snoops as they should snoop the caches above where 76211750Snikos.nikoleris@arm.com // they will get the response from. 76311750Snikos.nikoleris@arm.com if (is_invalidate && blk && blk->isValid()) { 76411750Snikos.nikoleris@arm.com invalidateBlock(blk); 76511750Snikos.nikoleris@arm.com } 76611051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 76711051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 76811051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 76911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 77011051Sandreas.hansson@arm.com pkt->payloadDelay; 77111051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 77211051Sandreas.hansson@arm.com // sanity check 77311051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 77411051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 77511051Sandreas.hansson@arm.com 77611051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 77711051Sandreas.hansson@arm.com } 77811051Sandreas.hansson@arm.com } 77911051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 78011051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 78111051Sandreas.hansson@arm.com if (is_error) 78211051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 78311051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 78411136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 78511051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 78611051Sandreas.hansson@arm.com // propagate that. Response should not have 78711051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 78811051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 78911744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: updated cmd to %s\n", __func__, 79011744Snikos.nikoleris@arm.com tgt_pkt->print()); 79111051Sandreas.hansson@arm.com } 79211051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 79311051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 79412724Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(tgt_pkt, completion_time, true); 79511051Sandreas.hansson@arm.com break; 79611051Sandreas.hansson@arm.com 79711051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 79811051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 79911051Sandreas.hansson@arm.com if (blk) 80011051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 80111051Sandreas.hansson@arm.com delete tgt_pkt; 80211051Sandreas.hansson@arm.com break; 80311051Sandreas.hansson@arm.com 80411051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 80511051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 80611051Sandreas.hansson@arm.com assert(!is_error); 80711051Sandreas.hansson@arm.com // response to snoop request 80811051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 80911749Snikos.nikoleris@arm.com // If the response is invalidating, a snooping target can 81011749Snikos.nikoleris@arm.com // be satisfied if it is also invalidating. If the reponse is, not 81112349Snikos.nikoleris@arm.com // only invalidating, but more specifically an InvalidateResp and 81212349Snikos.nikoleris@arm.com // the MSHR was created due to an InvalidateReq then a cache above 81312349Snikos.nikoleris@arm.com // is waiting to satisfy a WriteLineReq. In this case even an 81411749Snikos.nikoleris@arm.com // non-invalidating snoop is added as a target here since this is 81511749Snikos.nikoleris@arm.com // the ordering point. When the InvalidateResp reaches this cache, 81611749Snikos.nikoleris@arm.com // the snooping target will snoop further the cache above with the 81711749Snikos.nikoleris@arm.com // WriteLineReq. 81812349Snikos.nikoleris@arm.com assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp || 81912349Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance() || 82012349Snikos.nikoleris@arm.com mshr->hasPostInvalidate()); 82111051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 82211051Sandreas.hansson@arm.com break; 82311051Sandreas.hansson@arm.com 82411051Sandreas.hansson@arm.com default: 82511742Snikos.nikoleris@arm.com panic("Illegal target->source enum %d\n", target.source); 82611051Sandreas.hansson@arm.com } 82711051Sandreas.hansson@arm.com } 82811051Sandreas.hansson@arm.com 82912715Snikos.nikoleris@arm.com maintainClusivity(targets.hasFromCache, blk); 83011601Sandreas.hansson@arm.com 83111051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 83211051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 83311051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 83411051Sandreas.hansson@arm.com // invalidation should be discarded 83511136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 83611197Sandreas.hansson@arm.com invalidateBlock(blk); 83711051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 83811051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 83911051Sandreas.hansson@arm.com } 84011051Sandreas.hansson@arm.com } 84112719Snikos.nikoleris@arm.com} 84212719Snikos.nikoleris@arm.com 84311051Sandreas.hansson@arm.comPacketPtr 84412723Snikos.nikoleris@arm.comCache::evictBlock(CacheBlk *blk) 84512723Snikos.nikoleris@arm.com{ 84612723Snikos.nikoleris@arm.com PacketPtr pkt = (blk->isDirty() || writebackClean) ? 84712723Snikos.nikoleris@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 84812723Snikos.nikoleris@arm.com 84912723Snikos.nikoleris@arm.com invalidateBlock(blk); 85012723Snikos.nikoleris@arm.com 85112723Snikos.nikoleris@arm.com return pkt; 85212723Snikos.nikoleris@arm.com} 85312723Snikos.nikoleris@arm.com 85412723Snikos.nikoleris@arm.comvoid 85512723Snikos.nikoleris@arm.comCache::evictBlock(CacheBlk *blk, PacketList &writebacks) 85612723Snikos.nikoleris@arm.com{ 85712723Snikos.nikoleris@arm.com PacketPtr pkt = evictBlock(blk); 85812723Snikos.nikoleris@arm.com if (pkt) { 85912723Snikos.nikoleris@arm.com writebacks.push_back(pkt); 86012723Snikos.nikoleris@arm.com } 86112723Snikos.nikoleris@arm.com} 86212723Snikos.nikoleris@arm.com 86312723Snikos.nikoleris@arm.comPacketPtr 86411051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 86511051Sandreas.hansson@arm.com{ 86611199Sandreas.hansson@arm.com assert(!writebackClean); 86711051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 86812749Sgiacomo.travaglini@arm.com 86911051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 87012749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 87112749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 87212748Sgiacomo.travaglini@arm.com 87311051Sandreas.hansson@arm.com if (blk->isSecure()) 87411051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 87511051Sandreas.hansson@arm.com 87611051Sandreas.hansson@arm.com req->taskId(blk->task_id); 87711051Sandreas.hansson@arm.com 87811051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 87911051Sandreas.hansson@arm.com pkt->allocate(); 88011744Snikos.nikoleris@arm.com DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print()); 88111051Sandreas.hansson@arm.com 88211051Sandreas.hansson@arm.com return pkt; 88311051Sandreas.hansson@arm.com} 88411051Sandreas.hansson@arm.com 88511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 88611051Sandreas.hansson@arm.com// 88711051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 88811051Sandreas.hansson@arm.com// 88911051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 89011051Sandreas.hansson@arm.com 89111051Sandreas.hansson@arm.comvoid 89211051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 89311051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 89411051Sandreas.hansson@arm.com{ 89511051Sandreas.hansson@arm.com // sanity check 89611051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 89711051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 89811051Sandreas.hansson@arm.com 89911744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print()); 90011051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 90111051Sandreas.hansson@arm.com // already made a copy... 90211051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 90311051Sandreas.hansson@arm.com if (!already_copied) 90411051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 90511051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 90611051Sandreas.hansson@arm.com // responses) 90711051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 90811051Sandreas.hansson@arm.com 90911051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 91011284Sandreas.hansson@arm.com pkt->hasSharers()); 91111051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 91211051Sandreas.hansson@arm.com if (pkt->isRead()) { 91311051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 91411051Sandreas.hansson@arm.com } 91511051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 91611051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 91711051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 91811284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 91911284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 92011284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 92111284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 92211284Sandreas.hansson@arm.com // but must immediately invalidate it. 92311051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 92411051Sandreas.hansson@arm.com } 92511051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 92611051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 92711051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 92811051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 92911051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 93011051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 93111744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__, 93211744Snikos.nikoleris@arm.com pkt->print(), forward_time); 93312724Snikos.nikoleris@arm.com memSidePort.schedTimingSnoopResp(pkt, forward_time, true); 93411051Sandreas.hansson@arm.com} 93511051Sandreas.hansson@arm.com 93611127Sandreas.hansson@arm.comuint32_t 93711051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 93811051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 93911051Sandreas.hansson@arm.com{ 94011744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 94111051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 94211051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 94311051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 94411051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 94511051Sandreas.hansson@arm.com assert(pkt->isRequest()); 94611051Sandreas.hansson@arm.com 94711051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 94811051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 94911051Sandreas.hansson@arm.com // original packet up front 95011051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 95111284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 95211051Sandreas.hansson@arm.com 95311285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 95411285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 95511285Sandreas.hansson@arm.com // with this case 95611285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 95711744Snikos.nikoleris@arm.com "%s got an invalidating uncacheable snoop request %s", 95811744Snikos.nikoleris@arm.com name(), pkt->print()); 95911285Sandreas.hansson@arm.com 96011127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 96111127Sandreas.hansson@arm.com 96211051Sandreas.hansson@arm.com if (forwardSnoops) { 96311051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 96411051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 96511051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 96611284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 96711051Sandreas.hansson@arm.com if (is_timing) { 96811051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 96911051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 97011051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 97111051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 97211051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 97311051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 97411051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 97511051Sandreas.hansson@arm.com // time 97611051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 97712724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoopPkt); 97811127Sandreas.hansson@arm.com 97911127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 98011127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 98111127Sandreas.hansson@arm.com // cache 98211127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 98311127Sandreas.hansson@arm.com 98411284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 98511051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 98611051Sandreas.hansson@arm.com assert(!alreadyResponded); 98711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 98811051Sandreas.hansson@arm.com } 98911284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 99011284Sandreas.hansson@arm.com // MSHR, pass the flag on 99111284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 99211284Sandreas.hansson@arm.com pkt->setHasSharers(); 99311051Sandreas.hansson@arm.com } 99411051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 99511051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 99611051Sandreas.hansson@arm.com // presence to the requester. 99711051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 99811051Sandreas.hansson@arm.com pkt->setBlockCached(); 99911051Sandreas.hansson@arm.com } 100012349Snikos.nikoleris@arm.com // If the request was satisfied by snooping the cache 100112349Snikos.nikoleris@arm.com // above, mark the original packet as satisfied too. 100212349Snikos.nikoleris@arm.com if (snoopPkt.satisfied()) { 100312349Snikos.nikoleris@arm.com pkt->setSatisfied(); 100412349Snikos.nikoleris@arm.com } 100511051Sandreas.hansson@arm.com } else { 100612724Snikos.nikoleris@arm.com cpuSidePort.sendAtomicSnoop(pkt); 100711284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 100811051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 100911051Sandreas.hansson@arm.com // forward response to original requester 101011051Sandreas.hansson@arm.com assert(pkt->isResponse()); 101111051Sandreas.hansson@arm.com } 101211051Sandreas.hansson@arm.com } 101311051Sandreas.hansson@arm.com } 101411051Sandreas.hansson@arm.com 101512349Snikos.nikoleris@arm.com bool respond = false; 101612349Snikos.nikoleris@arm.com bool blk_valid = blk && blk->isValid(); 101712349Snikos.nikoleris@arm.com if (pkt->isClean()) { 101812349Snikos.nikoleris@arm.com if (blk_valid && blk->isDirty()) { 101912349Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n", 102012349Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 102112351Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 102212349Snikos.nikoleris@arm.com PacketList writebacks; 102312349Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 102412349Snikos.nikoleris@arm.com 102512349Snikos.nikoleris@arm.com if (is_timing) { 102612349Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward 102712349Snikos.nikoleris@arm.com // latency and the delay provided by the crossbar 102812349Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + 102912349Snikos.nikoleris@arm.com pkt->headerDelay; 103012349Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 103112349Snikos.nikoleris@arm.com } else { 103212349Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 103312349Snikos.nikoleris@arm.com } 103412349Snikos.nikoleris@arm.com pkt->setSatisfied(); 103512349Snikos.nikoleris@arm.com } 103612349Snikos.nikoleris@arm.com } else if (!blk_valid) { 103711744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__, 103811744Snikos.nikoleris@arm.com pkt->print()); 103911493Sandreas.hansson@arm.com if (is_deferred) { 104011493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 104111493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 104211493Sandreas.hansson@arm.com // to delete it 104311493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 104411493Sandreas.hansson@arm.com 104511493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 104611493Sandreas.hansson@arm.com // cache should be responding 104711493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 104811493Sandreas.hansson@arm.com 104911493Sandreas.hansson@arm.com delete pkt; 105011493Sandreas.hansson@arm.com } 105111127Sandreas.hansson@arm.com return snoop_delay; 105211051Sandreas.hansson@arm.com } else { 105311744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__, 105411744Snikos.nikoleris@arm.com pkt->print(), blk->print()); 105512349Snikos.nikoleris@arm.com 105612349Snikos.nikoleris@arm.com // We may end up modifying both the block state and the packet (if 105712349Snikos.nikoleris@arm.com // we respond in atomic mode), so just figure out what to do now 105812349Snikos.nikoleris@arm.com // and then do it later. We respond to all snoops that need 105912349Snikos.nikoleris@arm.com // responses provided we have the block in dirty state. The 106012349Snikos.nikoleris@arm.com // invalidation itself is taken care of below. We don't respond to 106112349Snikos.nikoleris@arm.com // cache maintenance operations as this is done by the destination 106212349Snikos.nikoleris@arm.com // xbar. 106312349Snikos.nikoleris@arm.com respond = blk->isDirty() && pkt->needsResponse(); 106412349Snikos.nikoleris@arm.com 106512349Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have " 106612349Snikos.nikoleris@arm.com "a dirty block in a read-only cache %s\n", name()); 106711051Sandreas.hansson@arm.com } 106811051Sandreas.hansson@arm.com 106911051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 107011051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 107111051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 107211051Sandreas.hansson@arm.com // downstream caches observe. 107311051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 107411483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 107511744Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->print()); 107611051Sandreas.hansson@arm.com pkt->setBlockCached(); 107711127Sandreas.hansson@arm.com return snoop_delay; 107811051Sandreas.hansson@arm.com } 107911051Sandreas.hansson@arm.com 108011285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 108111285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 108211284Sandreas.hansson@arm.com assert(!needs_writable); 108311284Sandreas.hansson@arm.com pkt->setHasSharers(); 108411285Sandreas.hansson@arm.com 108511285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 108611285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 108711285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 108811285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 108911285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 109011285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 109111285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 109212349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 109311051Sandreas.hansson@arm.com } 109411051Sandreas.hansson@arm.com 109511051Sandreas.hansson@arm.com if (respond) { 109611051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 109711051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 109811284Sandreas.hansson@arm.com // request 109911284Sandreas.hansson@arm.com pkt->setCacheResponding(); 110012349Snikos.nikoleris@arm.com if (!pkt->isClean() && blk->isWritable()) { 110111284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 110211284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 110311284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 110411284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 110511284Sandreas.hansson@arm.com 110611081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 110711284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 110811284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 110911284Sandreas.hansson@arm.com } else { 111011284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 111111284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 111211284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 111311284Sandreas.hansson@arm.com // we already called setHasSharers above 111411051Sandreas.hansson@arm.com } 111511284Sandreas.hansson@arm.com 111611285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 111711285Sandreas.hansson@arm.com // we should be invalidating the line 111811285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 111911744Snikos.nikoleris@arm.com "%s is passing a Modified line through %s, " 112011744Snikos.nikoleris@arm.com "but keeping the block", name(), pkt->print()); 112111285Sandreas.hansson@arm.com 112211051Sandreas.hansson@arm.com if (is_timing) { 112311051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 112411051Sandreas.hansson@arm.com } else { 112511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 112611286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 112711286Sandreas.hansson@arm.com // payload 112811286Sandreas.hansson@arm.com if (pkt->hasData()) 112911286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 113011051Sandreas.hansson@arm.com } 113111051Sandreas.hansson@arm.com } 113211051Sandreas.hansson@arm.com 113311602Sandreas.hansson@arm.com if (!respond && is_deferred) { 113411051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 113511051Sandreas.hansson@arm.com delete pkt; 113611051Sandreas.hansson@arm.com } 113711051Sandreas.hansson@arm.com 113811051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 113911051Sandreas.hansson@arm.com // like that 114012349Snikos.nikoleris@arm.com if (blk_valid && invalidate) { 114111197Sandreas.hansson@arm.com invalidateBlock(blk); 114212349Snikos.nikoleris@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 114311051Sandreas.hansson@arm.com } 114411051Sandreas.hansson@arm.com 114511127Sandreas.hansson@arm.com return snoop_delay; 114611051Sandreas.hansson@arm.com} 114711051Sandreas.hansson@arm.com 114811051Sandreas.hansson@arm.com 114911051Sandreas.hansson@arm.comvoid 115011051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 115111051Sandreas.hansson@arm.com{ 115211744Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print()); 115311051Sandreas.hansson@arm.com 115411130Sali.jafri@arm.com // no need to snoop requests that are not in range 115511051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 115611051Sandreas.hansson@arm.com return; 115711051Sandreas.hansson@arm.com } 115811051Sandreas.hansson@arm.com 115911051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 116011051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 116111051Sandreas.hansson@arm.com 116211892Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 116311051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 116411051Sandreas.hansson@arm.com 116511127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 116611127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 116711127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 116811127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 116911127Sandreas.hansson@arm.com // happens below. 117011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 117111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 117211127Sandreas.hansson@arm.com 117311051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 117411051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 117511051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 117611744Snikos.nikoleris@arm.com DPRINTF(Cache, "Setting block cached for %s from lower cache on " 117711744Snikos.nikoleris@arm.com "mshr hit\n", pkt->print()); 117811051Sandreas.hansson@arm.com pkt->setBlockCached(); 117911051Sandreas.hansson@arm.com return; 118011051Sandreas.hansson@arm.com } 118111051Sandreas.hansson@arm.com 118212349Snikos.nikoleris@arm.com // Bypass any existing cache maintenance requests if the request 118312349Snikos.nikoleris@arm.com // has been satisfied already (i.e., the dirty block has been 118412349Snikos.nikoleris@arm.com // found). 118512349Snikos.nikoleris@arm.com if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) { 118612349Snikos.nikoleris@arm.com return; 118712349Snikos.nikoleris@arm.com } 118812349Snikos.nikoleris@arm.com 118911051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 119011051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 119111051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 119211051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 119311051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 119411051Sandreas.hansson@arm.com mshr->print()); 119511051Sandreas.hansson@arm.com 119611051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 119711051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 119811051Sandreas.hansson@arm.com return; 119911051Sandreas.hansson@arm.com } 120011051Sandreas.hansson@arm.com 120111051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 120211375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 120311375Sandreas.hansson@arm.com if (wb_entry) { 120411051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 120511051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 120611051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 120711051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 120811051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 120911051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 121011051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 121111051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 121211051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 121312345Snikos.nikoleris@arm.com assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean); 121411051Sandreas.hansson@arm.com 121511199Sandreas.hansson@arm.com if (pkt->isEviction()) { 121611051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 121711051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 121811051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 121911051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 122011051Sandreas.hansson@arm.com pkt->setBlockCached(); 122111744Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue " 122211744Snikos.nikoleris@arm.com "hit\n", __func__, pkt->print()); 122311051Sandreas.hansson@arm.com return; 122411051Sandreas.hansson@arm.com } 122511051Sandreas.hansson@arm.com 122611332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 122711332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 122811332Sandreas.hansson@arm.com // the difference being that instead of querying the block 122911332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 123011332Sandreas.hansson@arm.com // command and fields of the writeback packet 123111332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 123211751Snikos.nikoleris@arm.com pkt->needsResponse(); 123311332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 123411332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 123511332Sandreas.hansson@arm.com 123611332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 123711332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 123811332Sandreas.hansson@arm.com pkt->setHasSharers(); 123911332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 124011332Sandreas.hansson@arm.com } 124111332Sandreas.hansson@arm.com 124211332Sandreas.hansson@arm.com if (respond) { 124311284Sandreas.hansson@arm.com pkt->setCacheResponding(); 124411332Sandreas.hansson@arm.com 124511332Sandreas.hansson@arm.com if (have_writable) { 124611332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 124711051Sandreas.hansson@arm.com } 124811332Sandreas.hansson@arm.com 124911051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 125011051Sandreas.hansson@arm.com false, false); 125111051Sandreas.hansson@arm.com } 125211051Sandreas.hansson@arm.com 125312349Snikos.nikoleris@arm.com if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) { 125411051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 125511051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 125611375Sandreas.hansson@arm.com markInService(wb_entry); 125711051Sandreas.hansson@arm.com delete wb_pkt; 125811051Sandreas.hansson@arm.com } 125911051Sandreas.hansson@arm.com } 126011051Sandreas.hansson@arm.com 126111051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 126211051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 126311051Sandreas.hansson@arm.com // We could be more selective and return here if the 126411051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 126511051Sandreas.hansson@arm.com // exclusive. 126611127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 126711127Sandreas.hansson@arm.com 126811127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 126911127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 127011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 127111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 127211051Sandreas.hansson@arm.com} 127311051Sandreas.hansson@arm.com 127411051Sandreas.hansson@arm.comTick 127511051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 127611051Sandreas.hansson@arm.com{ 127711130Sali.jafri@arm.com // no need to snoop requests that are not in range. 127811130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 127911051Sandreas.hansson@arm.com return 0; 128011051Sandreas.hansson@arm.com } 128111051Sandreas.hansson@arm.com 128211051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 128311127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 128411127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 128511051Sandreas.hansson@arm.com} 128611051Sandreas.hansson@arm.com 128711051Sandreas.hansson@arm.combool 128812724Snikos.nikoleris@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) 128911051Sandreas.hansson@arm.com{ 129011051Sandreas.hansson@arm.com if (!forwardSnoops) 129111051Sandreas.hansson@arm.com return false; 129211051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 129311051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 129411051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 129511051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 129611051Sandreas.hansson@arm.com // of the block. 129711130Sali.jafri@arm.com if (is_timing) { 129811130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 129911130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 130011130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 130111130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 130211130Sali.jafri@arm.com // generate a snoop response. 130312345Snikos.nikoleris@arm.com assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean); 130411484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 130512724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 130611130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 130711284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 130811130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 130911130Sali.jafri@arm.com } else { 131012724Snikos.nikoleris@arm.com cpuSidePort.sendAtomicSnoop(pkt); 131111130Sali.jafri@arm.com return pkt->isBlockCached(); 131211130Sali.jafri@arm.com } 131311051Sandreas.hansson@arm.com} 131411051Sandreas.hansson@arm.com 131511375Sandreas.hansson@arm.combool 131611375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 131711375Sandreas.hansson@arm.com{ 131811375Sandreas.hansson@arm.com assert(mshr); 131911375Sandreas.hansson@arm.com 132011051Sandreas.hansson@arm.com // use request from 1st target 132111051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 132211375Sandreas.hansson@arm.com 132312724Snikos.nikoleris@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 132412724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 132511051Sandreas.hansson@arm.com 132611375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 132711375Sandreas.hansson@arm.com // blocks 132812724Snikos.nikoleris@arm.com assert(!tags->findBlock(mshr->blkAddr, mshr->isSecure)); 132911375Sandreas.hansson@arm.com 133011051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 133111051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 133211051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 133311051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 133411051Sandreas.hansson@arm.com // dirty one. 133511051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 133611051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 133711275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 133811275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 133911275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 134011275Sandreas.hansson@arm.com // state 134111051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 134212724Snikos.nikoleris@arm.com cpuSidePort.sendTimingSnoopReq(&snoop_pkt); 134311051Sandreas.hansson@arm.com 134411051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 134511051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 134611051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 134711051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 134811051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 134911051Sandreas.hansson@arm.com 135011284Sandreas.hansson@arm.com // It is important to check cacheResponding before 135111284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 135211284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 135311284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 135411284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 135511284Sandreas.hansson@arm.com // prematurely deallocated. 135611284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 135711276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 135811276Sandreas.hansson@arm.com assert(r.second); 135911284Sandreas.hansson@arm.com 136011284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 136111284Sandreas.hansson@arm.com // will be allocated as Modified 136211284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 136311284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 136411284Sandreas.hansson@arm.com 136511051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 136611051Sandreas.hansson@arm.com " %#x (%s) hit\n", 136711051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 136811375Sandreas.hansson@arm.com return false; 136911051Sandreas.hansson@arm.com } 137011051Sandreas.hansson@arm.com 137111375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 137211051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 137311051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 137411051Sandreas.hansson@arm.com mshr->blkAddr); 137511375Sandreas.hansson@arm.com 137611051Sandreas.hansson@arm.com // Deallocate the mshr target 137711375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 137811277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 137911277Sandreas.hansson@arm.com // mshr when all had previously been utilized 138011375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 138111051Sandreas.hansson@arm.com } 138212167Spau.cabre@metempsy.com 138312167Spau.cabre@metempsy.com // given that no response is expected, delete Request and Packet 138412167Spau.cabre@metempsy.com delete tgt_pkt; 138512167Spau.cabre@metempsy.com 138611375Sandreas.hansson@arm.com return false; 138711051Sandreas.hansson@arm.com } 138811051Sandreas.hansson@arm.com } 138911051Sandreas.hansson@arm.com 139012724Snikos.nikoleris@arm.com return BaseCache::sendMSHRQueuePacket(mshr); 139111051Sandreas.hansson@arm.com} 139211051Sandreas.hansson@arm.com 139311053Sandreas.hansson@arm.comCache* 139411053Sandreas.hansson@arm.comCacheParams::create() 139511053Sandreas.hansson@arm.com{ 139611053Sandreas.hansson@arm.com assert(tags); 139712600Sodanrc@yahoo.com.br assert(replacement_policy); 139811053Sandreas.hansson@arm.com 139911053Sandreas.hansson@arm.com return new Cache(this); 140011053Sandreas.hansson@arm.com} 1401