cache.cc revision 12715
12810Srdreslin@umich.edu/*
212500Snikos.nikoleris@arm.com * Copyright (c) 2010-2018 ARM Limited
311051Sandreas.hansson@arm.com * All rights reserved.
411051Sandreas.hansson@arm.com *
511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall
611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual
711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating
811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software
911051Sandreas.hansson@arm.com * licensed hereunder.  You may use the software subject to the license
1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated
1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software,
1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form.
1311051Sandreas.hansson@arm.com *
1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan
1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc.
162810Srdreslin@umich.edu * All rights reserved.
172810Srdreslin@umich.edu *
182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without
192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are
202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright
212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer;
222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright
232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the
242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution;
252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its
262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from
272810Srdreslin@umich.edu * this software without specific prior written permission.
282810Srdreslin@umich.edu *
292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
402810Srdreslin@umich.edu *
412810Srdreslin@umich.edu * Authors: Erik Hallnor
4211051Sandreas.hansson@arm.com *          Dave Greene
4311051Sandreas.hansson@arm.com *          Nathan Binkert
442810Srdreslin@umich.edu *          Steve Reinhardt
4511051Sandreas.hansson@arm.com *          Ron Dreslinski
4611051Sandreas.hansson@arm.com *          Andreas Sandberg
4712349Snikos.nikoleris@arm.com *          Nikos Nikoleris
482810Srdreslin@umich.edu */
492810Srdreslin@umich.edu
502810Srdreslin@umich.edu/**
512810Srdreslin@umich.edu * @file
5211051Sandreas.hansson@arm.com * Cache definitions.
532810Srdreslin@umich.edu */
542810Srdreslin@umich.edu
5511051Sandreas.hansson@arm.com#include "mem/cache/cache.hh"
562810Srdreslin@umich.edu
5712334Sgabeblack@google.com#include "base/logging.hh"
5811051Sandreas.hansson@arm.com#include "base/types.hh"
5911051Sandreas.hansson@arm.com#include "debug/Cache.hh"
6011051Sandreas.hansson@arm.com#include "debug/CachePort.hh"
6111051Sandreas.hansson@arm.com#include "debug/CacheTags.hh"
6211288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh"
6311051Sandreas.hansson@arm.com#include "mem/cache/blk.hh"
6411051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh"
6511051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh"
6611051Sandreas.hansson@arm.com#include "sim/sim_exit.hh"
6711051Sandreas.hansson@arm.com
6811053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p)
6911053Sandreas.hansson@arm.com    : BaseCache(p, p->system->cacheLineSize()),
7011051Sandreas.hansson@arm.com      tags(p->tags),
7111051Sandreas.hansson@arm.com      prefetcher(p->prefetcher),
7211051Sandreas.hansson@arm.com      doFastWrites(true),
7311197Sandreas.hansson@arm.com      prefetchOnAccess(p->prefetch_on_access),
7411197Sandreas.hansson@arm.com      clusivity(p->clusivity),
7511199Sandreas.hansson@arm.com      writebackClean(p->writeback_clean),
7611197Sandreas.hansson@arm.com      tempBlockWriteback(nullptr),
7712084Sspwilson2@wisc.edu      writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); },
7812084Sspwilson2@wisc.edu                                    name(), false,
7911197Sandreas.hansson@arm.com                                    EventBase::Delayed_Writeback_Pri)
8011051Sandreas.hansson@arm.com{
8111051Sandreas.hansson@arm.com    tempBlock = new CacheBlk();
8211051Sandreas.hansson@arm.com    tempBlock->data = new uint8_t[blkSize];
8311051Sandreas.hansson@arm.com
8411051Sandreas.hansson@arm.com    cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this,
8511051Sandreas.hansson@arm.com                                  "CpuSidePort");
8611051Sandreas.hansson@arm.com    memSidePort = new MemSidePort(p->name + ".mem_side", this,
8711051Sandreas.hansson@arm.com                                  "MemSidePort");
8811051Sandreas.hansson@arm.com
8911051Sandreas.hansson@arm.com    tags->setCache(this);
9011051Sandreas.hansson@arm.com    if (prefetcher)
9111051Sandreas.hansson@arm.com        prefetcher->setCache(this);
9211051Sandreas.hansson@arm.com}
9311051Sandreas.hansson@arm.com
9411051Sandreas.hansson@arm.comCache::~Cache()
9511051Sandreas.hansson@arm.com{
9611051Sandreas.hansson@arm.com    delete [] tempBlock->data;
9711051Sandreas.hansson@arm.com    delete tempBlock;
9811051Sandreas.hansson@arm.com
9911051Sandreas.hansson@arm.com    delete cpuSidePort;
10011051Sandreas.hansson@arm.com    delete memSidePort;
10111051Sandreas.hansson@arm.com}
10211051Sandreas.hansson@arm.com
10311051Sandreas.hansson@arm.comvoid
10411051Sandreas.hansson@arm.comCache::regStats()
10511051Sandreas.hansson@arm.com{
10611051Sandreas.hansson@arm.com    BaseCache::regStats();
10711051Sandreas.hansson@arm.com}
10811051Sandreas.hansson@arm.com
10911051Sandreas.hansson@arm.comvoid
11011051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt)
11111051Sandreas.hansson@arm.com{
11211051Sandreas.hansson@arm.com    assert(pkt->isRequest());
11311051Sandreas.hansson@arm.com
11411051Sandreas.hansson@arm.com    uint64_t overwrite_val;
11511051Sandreas.hansson@arm.com    bool overwrite_mem;
11611051Sandreas.hansson@arm.com    uint64_t condition_val64;
11711051Sandreas.hansson@arm.com    uint32_t condition_val32;
11811051Sandreas.hansson@arm.com
11911051Sandreas.hansson@arm.com    int offset = tags->extractBlkOffset(pkt->getAddr());
12011051Sandreas.hansson@arm.com    uint8_t *blk_data = blk->data + offset;
12111051Sandreas.hansson@arm.com
12211051Sandreas.hansson@arm.com    assert(sizeof(uint64_t) >= pkt->getSize());
12311051Sandreas.hansson@arm.com
12411051Sandreas.hansson@arm.com    overwrite_mem = true;
12511051Sandreas.hansson@arm.com    // keep a copy of our possible write value, and copy what is at the
12611051Sandreas.hansson@arm.com    // memory address into the packet
12711051Sandreas.hansson@arm.com    pkt->writeData((uint8_t *)&overwrite_val);
12811051Sandreas.hansson@arm.com    pkt->setData(blk_data);
12911051Sandreas.hansson@arm.com
13011051Sandreas.hansson@arm.com    if (pkt->req->isCondSwap()) {
13111051Sandreas.hansson@arm.com        if (pkt->getSize() == sizeof(uint64_t)) {
13211051Sandreas.hansson@arm.com            condition_val64 = pkt->req->getExtraData();
13311051Sandreas.hansson@arm.com            overwrite_mem = !std::memcmp(&condition_val64, blk_data,
13411051Sandreas.hansson@arm.com                                         sizeof(uint64_t));
13511051Sandreas.hansson@arm.com        } else if (pkt->getSize() == sizeof(uint32_t)) {
13611051Sandreas.hansson@arm.com            condition_val32 = (uint32_t)pkt->req->getExtraData();
13711051Sandreas.hansson@arm.com            overwrite_mem = !std::memcmp(&condition_val32, blk_data,
13811051Sandreas.hansson@arm.com                                         sizeof(uint32_t));
13911051Sandreas.hansson@arm.com        } else
14011051Sandreas.hansson@arm.com            panic("Invalid size for conditional read/write\n");
14111051Sandreas.hansson@arm.com    }
14211051Sandreas.hansson@arm.com
14311051Sandreas.hansson@arm.com    if (overwrite_mem) {
14411051Sandreas.hansson@arm.com        std::memcpy(blk_data, &overwrite_val, pkt->getSize());
14511051Sandreas.hansson@arm.com        blk->status |= BlkDirty;
14611051Sandreas.hansson@arm.com    }
14711051Sandreas.hansson@arm.com}
14811051Sandreas.hansson@arm.com
14911051Sandreas.hansson@arm.com
15011051Sandreas.hansson@arm.comvoid
15111601Sandreas.hansson@arm.comCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk,
15211601Sandreas.hansson@arm.com                      bool deferred_response, bool pending_downgrade)
15311051Sandreas.hansson@arm.com{
15411051Sandreas.hansson@arm.com    assert(pkt->isRequest());
15511051Sandreas.hansson@arm.com
15611051Sandreas.hansson@arm.com    assert(blk && blk->isValid());
15711051Sandreas.hansson@arm.com    // Occasionally this is not true... if we are a lower-level cache
15811051Sandreas.hansson@arm.com    // satisfying a string of Read and ReadEx requests from
15911051Sandreas.hansson@arm.com    // upper-level caches, a Read will mark the block as shared but we
16011051Sandreas.hansson@arm.com    // can satisfy a following ReadEx anyway since we can rely on the
16111051Sandreas.hansson@arm.com    // Read requester(s) to have buffered the ReadEx snoop and to
16211051Sandreas.hansson@arm.com    // invalidate their blocks after receiving them.
16311284Sandreas.hansson@arm.com    // assert(!pkt->needsWritable() || blk->isWritable());
16411051Sandreas.hansson@arm.com    assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize);
16511051Sandreas.hansson@arm.com
16611051Sandreas.hansson@arm.com    // Check RMW operations first since both isRead() and
16711051Sandreas.hansson@arm.com    // isWrite() will be true for them
16811051Sandreas.hansson@arm.com    if (pkt->cmd == MemCmd::SwapReq) {
16911051Sandreas.hansson@arm.com        cmpAndSwap(blk, pkt);
17011051Sandreas.hansson@arm.com    } else if (pkt->isWrite()) {
17111284Sandreas.hansson@arm.com        // we have the block in a writable state and can go ahead,
17211284Sandreas.hansson@arm.com        // note that the line may be also be considered writable in
17311284Sandreas.hansson@arm.com        // downstream caches along the path to memory, but always
17411284Sandreas.hansson@arm.com        // Exclusive, and never Modified
17511051Sandreas.hansson@arm.com        assert(blk->isWritable());
17611284Sandreas.hansson@arm.com        // Write or WriteLine at the first cache with block in writable state
17711051Sandreas.hansson@arm.com        if (blk->checkWrite(pkt)) {
17811051Sandreas.hansson@arm.com            pkt->writeDataToBlock(blk->data, blkSize);
17911051Sandreas.hansson@arm.com        }
18011284Sandreas.hansson@arm.com        // Always mark the line as dirty (and thus transition to the
18111284Sandreas.hansson@arm.com        // Modified state) even if we are a failed StoreCond so we
18211284Sandreas.hansson@arm.com        // supply data to any snoops that have appended themselves to
18311284Sandreas.hansson@arm.com        // this cache before knowing the store will fail.
18411051Sandreas.hansson@arm.com        blk->status |= BlkDirty;
18511744Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print());
18611051Sandreas.hansson@arm.com    } else if (pkt->isRead()) {
18711051Sandreas.hansson@arm.com        if (pkt->isLLSC()) {
18811051Sandreas.hansson@arm.com            blk->trackLoadLocked(pkt);
18911051Sandreas.hansson@arm.com        }
19011286Sandreas.hansson@arm.com
19111286Sandreas.hansson@arm.com        // all read responses have a data payload
19211286Sandreas.hansson@arm.com        assert(pkt->hasRespData());
19311051Sandreas.hansson@arm.com        pkt->setDataFromBlock(blk->data, blkSize);
19411286Sandreas.hansson@arm.com
19511600Sandreas.hansson@arm.com        // determine if this read is from a (coherent) cache or not
19611600Sandreas.hansson@arm.com        if (pkt->fromCache()) {
19711051Sandreas.hansson@arm.com            assert(pkt->getSize() == blkSize);
19811051Sandreas.hansson@arm.com            // special handling for coherent block requests from
19911051Sandreas.hansson@arm.com            // upper-level caches
20011284Sandreas.hansson@arm.com            if (pkt->needsWritable()) {
20111051Sandreas.hansson@arm.com                // sanity check
20211051Sandreas.hansson@arm.com                assert(pkt->cmd == MemCmd::ReadExReq ||
20311051Sandreas.hansson@arm.com                       pkt->cmd == MemCmd::SCUpgradeFailReq);
20411602Sandreas.hansson@arm.com                assert(!pkt->hasSharers());
20511051Sandreas.hansson@arm.com
20611051Sandreas.hansson@arm.com                // if we have a dirty copy, make sure the recipient
20711284Sandreas.hansson@arm.com                // keeps it marked dirty (in the modified state)
20811051Sandreas.hansson@arm.com                if (blk->isDirty()) {
20911284Sandreas.hansson@arm.com                    pkt->setCacheResponding();
21011602Sandreas.hansson@arm.com                    blk->status &= ~BlkDirty;
21111051Sandreas.hansson@arm.com                }
21211051Sandreas.hansson@arm.com            } else if (blk->isWritable() && !pending_downgrade &&
21311284Sandreas.hansson@arm.com                       !pkt->hasSharers() &&
21411051Sandreas.hansson@arm.com                       pkt->cmd != MemCmd::ReadCleanReq) {
21511284Sandreas.hansson@arm.com                // we can give the requester a writable copy on a read
21611284Sandreas.hansson@arm.com                // request if:
21711284Sandreas.hansson@arm.com                // - we have a writable copy at this level (& below)
21811051Sandreas.hansson@arm.com                // - we don't have a pending snoop from below
21911051Sandreas.hansson@arm.com                //   signaling another read request
22011051Sandreas.hansson@arm.com                // - no other cache above has a copy (otherwise it
22111284Sandreas.hansson@arm.com                //   would have set hasSharers flag when
22211284Sandreas.hansson@arm.com                //   snooping the packet)
22311284Sandreas.hansson@arm.com                // - the read has explicitly asked for a clean
22411284Sandreas.hansson@arm.com                //   copy of the line
22511051Sandreas.hansson@arm.com                if (blk->isDirty()) {
22611051Sandreas.hansson@arm.com                    // special considerations if we're owner:
22711051Sandreas.hansson@arm.com                    if (!deferred_response) {
22811284Sandreas.hansson@arm.com                        // respond with the line in Modified state
22911284Sandreas.hansson@arm.com                        // (cacheResponding set, hasSharers not set)
23011284Sandreas.hansson@arm.com                        pkt->setCacheResponding();
23111197Sandreas.hansson@arm.com
23211601Sandreas.hansson@arm.com                        // if this cache is mostly inclusive, we
23311601Sandreas.hansson@arm.com                        // keep the block in the Exclusive state,
23411601Sandreas.hansson@arm.com                        // and pass it upwards as Modified
23511601Sandreas.hansson@arm.com                        // (writable and dirty), hence we have
23611601Sandreas.hansson@arm.com                        // multiple caches, all on the same path
23711601Sandreas.hansson@arm.com                        // towards memory, all considering the
23811601Sandreas.hansson@arm.com                        // same block writable, but only one
23911601Sandreas.hansson@arm.com                        // considering it Modified
24011197Sandreas.hansson@arm.com
24111601Sandreas.hansson@arm.com                        // we get away with multiple caches (on
24211601Sandreas.hansson@arm.com                        // the same path to memory) considering
24311601Sandreas.hansson@arm.com                        // the block writeable as we always enter
24411601Sandreas.hansson@arm.com                        // the cache hierarchy through a cache,
24511601Sandreas.hansson@arm.com                        // and first snoop upwards in all other
24611601Sandreas.hansson@arm.com                        // branches
24711601Sandreas.hansson@arm.com                        blk->status &= ~BlkDirty;
24811051Sandreas.hansson@arm.com                    } else {
24911051Sandreas.hansson@arm.com                        // if we're responding after our own miss,
25011051Sandreas.hansson@arm.com                        // there's a window where the recipient didn't
25111051Sandreas.hansson@arm.com                        // know it was getting ownership and may not
25211051Sandreas.hansson@arm.com                        // have responded to snoops correctly, so we
25311284Sandreas.hansson@arm.com                        // have to respond with a shared line
25411284Sandreas.hansson@arm.com                        pkt->setHasSharers();
25511051Sandreas.hansson@arm.com                    }
25611051Sandreas.hansson@arm.com                }
25711051Sandreas.hansson@arm.com            } else {
25811051Sandreas.hansson@arm.com                // otherwise only respond with a shared copy
25911284Sandreas.hansson@arm.com                pkt->setHasSharers();
26011051Sandreas.hansson@arm.com            }
26111051Sandreas.hansson@arm.com        }
26211602Sandreas.hansson@arm.com    } else if (pkt->isUpgrade()) {
26311602Sandreas.hansson@arm.com        // sanity check
26411602Sandreas.hansson@arm.com        assert(!pkt->hasSharers());
26511602Sandreas.hansson@arm.com
26611602Sandreas.hansson@arm.com        if (blk->isDirty()) {
26711602Sandreas.hansson@arm.com            // we were in the Owned state, and a cache above us that
26811602Sandreas.hansson@arm.com            // has the line in Shared state needs to be made aware
26911602Sandreas.hansson@arm.com            // that the data it already has is in fact dirty
27011602Sandreas.hansson@arm.com            pkt->setCacheResponding();
27111602Sandreas.hansson@arm.com            blk->status &= ~BlkDirty;
27211602Sandreas.hansson@arm.com        }
27311051Sandreas.hansson@arm.com    } else {
27411602Sandreas.hansson@arm.com        assert(pkt->isInvalidate());
27511197Sandreas.hansson@arm.com        invalidateBlock(blk);
27611744Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__,
27711744Snikos.nikoleris@arm.com                pkt->print());
27811051Sandreas.hansson@arm.com    }
27911051Sandreas.hansson@arm.com}
28011051Sandreas.hansson@arm.com
28111051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
28211051Sandreas.hansson@arm.com//
28311051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side
28411051Sandreas.hansson@arm.com//
28511051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
28611051Sandreas.hansson@arm.com
28711051Sandreas.hansson@arm.combool
28811051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
28911051Sandreas.hansson@arm.com              PacketList &writebacks)
29011051Sandreas.hansson@arm.com{
29111051Sandreas.hansson@arm.com    // sanity check
29211051Sandreas.hansson@arm.com    assert(pkt->isRequest());
29311051Sandreas.hansson@arm.com
29411051Sandreas.hansson@arm.com    chatty_assert(!(isReadOnly && pkt->isWrite()),
29511051Sandreas.hansson@arm.com                  "Should never see a write in a read-only cache %s\n",
29611051Sandreas.hansson@arm.com                  name());
29711051Sandreas.hansson@arm.com
29811744Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s for %s\n", __func__, pkt->print());
29911051Sandreas.hansson@arm.com
30011051Sandreas.hansson@arm.com    if (pkt->req->isUncacheable()) {
30111744Snikos.nikoleris@arm.com        DPRINTF(Cache, "uncacheable: %s\n", pkt->print());
30211051Sandreas.hansson@arm.com
30311051Sandreas.hansson@arm.com        // flush and invalidate any existing block
30411051Sandreas.hansson@arm.com        CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure()));
30511051Sandreas.hansson@arm.com        if (old_blk && old_blk->isValid()) {
30611199Sandreas.hansson@arm.com            if (old_blk->isDirty() || writebackClean)
30711051Sandreas.hansson@arm.com                writebacks.push_back(writebackBlk(old_blk));
30811051Sandreas.hansson@arm.com            else
30911051Sandreas.hansson@arm.com                writebacks.push_back(cleanEvictBlk(old_blk));
31011867Snikos.nikoleris@arm.com            invalidateBlock(old_blk);
31111051Sandreas.hansson@arm.com        }
31211051Sandreas.hansson@arm.com
31311484Snikos.nikoleris@arm.com        blk = nullptr;
31411051Sandreas.hansson@arm.com        // lookupLatency is the latency in case the request is uncacheable.
31511051Sandreas.hansson@arm.com        lat = lookupLatency;
31611051Sandreas.hansson@arm.com        return false;
31711051Sandreas.hansson@arm.com    }
31811051Sandreas.hansson@arm.com
31911051Sandreas.hansson@arm.com    // Here lat is the value passed as parameter to accessBlock() function
32011051Sandreas.hansson@arm.com    // that can modify its value.
32111870Snikos.nikoleris@arm.com    blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat);
32211051Sandreas.hansson@arm.com
32311744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s %s\n", pkt->print(),
32411051Sandreas.hansson@arm.com            blk ? "hit " + blk->print() : "miss");
32511051Sandreas.hansson@arm.com
32612349Snikos.nikoleris@arm.com    if (pkt->req->isCacheMaintenance()) {
32712349Snikos.nikoleris@arm.com        // A cache maintenance operation is always forwarded to the
32812349Snikos.nikoleris@arm.com        // memory below even if the block is found in dirty state.
32912349Snikos.nikoleris@arm.com
33012349Snikos.nikoleris@arm.com        // We defer any changes to the state of the block until we
33112349Snikos.nikoleris@arm.com        // create and mark as in service the mshr for the downstream
33212349Snikos.nikoleris@arm.com        // packet.
33312349Snikos.nikoleris@arm.com        return false;
33412349Snikos.nikoleris@arm.com    }
33511051Sandreas.hansson@arm.com
33611199Sandreas.hansson@arm.com    if (pkt->isEviction()) {
33711051Sandreas.hansson@arm.com        // We check for presence of block in above caches before issuing
33811051Sandreas.hansson@arm.com        // Writeback or CleanEvict to write buffer. Therefore the only
33911051Sandreas.hansson@arm.com        // possible cases can be of a CleanEvict packet coming from above
34011051Sandreas.hansson@arm.com        // encountering a Writeback generated in this cache peer cache and
34111051Sandreas.hansson@arm.com        // waiting in the write buffer. Cases of upper level peer caches
34211051Sandreas.hansson@arm.com        // generating CleanEvict and Writeback or simply CleanEvict and
34311051Sandreas.hansson@arm.com        // CleanEvict almost simultaneously will be caught by snoops sent out
34411051Sandreas.hansson@arm.com        // by crossbar.
34511375Sandreas.hansson@arm.com        WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(),
34611375Sandreas.hansson@arm.com                                                          pkt->isSecure());
34711375Sandreas.hansson@arm.com        if (wb_entry) {
34811199Sandreas.hansson@arm.com            assert(wb_entry->getNumTargets() == 1);
34911199Sandreas.hansson@arm.com            PacketPtr wbPkt = wb_entry->getTarget()->pkt;
35011199Sandreas.hansson@arm.com            assert(wbPkt->isWriteback());
35111199Sandreas.hansson@arm.com
35211199Sandreas.hansson@arm.com            if (pkt->isCleanEviction()) {
35311199Sandreas.hansson@arm.com                // The CleanEvict and WritebackClean snoops into other
35411199Sandreas.hansson@arm.com                // peer caches of the same level while traversing the
35511199Sandreas.hansson@arm.com                // crossbar. If a copy of the block is found, the
35611199Sandreas.hansson@arm.com                // packet is deleted in the crossbar. Hence, none of
35711199Sandreas.hansson@arm.com                // the other upper level caches connected to this
35811199Sandreas.hansson@arm.com                // cache have the block, so we can clear the
35911199Sandreas.hansson@arm.com                // BLOCK_CACHED flag in the Writeback if set and
36011199Sandreas.hansson@arm.com                // discard the CleanEvict by returning true.
36111199Sandreas.hansson@arm.com                wbPkt->clearBlockCached();
36211199Sandreas.hansson@arm.com                return true;
36311199Sandreas.hansson@arm.com            } else {
36411199Sandreas.hansson@arm.com                assert(pkt->cmd == MemCmd::WritebackDirty);
36511199Sandreas.hansson@arm.com                // Dirty writeback from above trumps our clean
36611199Sandreas.hansson@arm.com                // writeback... discard here
36711199Sandreas.hansson@arm.com                // Note: markInService will remove entry from writeback buffer.
36811375Sandreas.hansson@arm.com                markInService(wb_entry);
36911199Sandreas.hansson@arm.com                delete wbPkt;
37011199Sandreas.hansson@arm.com            }
37111051Sandreas.hansson@arm.com        }
37211051Sandreas.hansson@arm.com    }
37311051Sandreas.hansson@arm.com
37411051Sandreas.hansson@arm.com    // Writeback handling is special case.  We can write the block into
37511051Sandreas.hansson@arm.com    // the cache without having a writeable copy (or any copy at all).
37611199Sandreas.hansson@arm.com    if (pkt->isWriteback()) {
37711051Sandreas.hansson@arm.com        assert(blkSize == pkt->getSize());
37811199Sandreas.hansson@arm.com
37911199Sandreas.hansson@arm.com        // we could get a clean writeback while we are having
38011199Sandreas.hansson@arm.com        // outstanding accesses to a block, do the simple thing for
38111199Sandreas.hansson@arm.com        // now and drop the clean writeback so that we do not upset
38211199Sandreas.hansson@arm.com        // any ordering/decisions about ownership already taken
38311199Sandreas.hansson@arm.com        if (pkt->cmd == MemCmd::WritebackClean &&
38411199Sandreas.hansson@arm.com            mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) {
38511199Sandreas.hansson@arm.com            DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, "
38611199Sandreas.hansson@arm.com                    "dropping\n", pkt->getAddr());
38711199Sandreas.hansson@arm.com            return true;
38811199Sandreas.hansson@arm.com        }
38911199Sandreas.hansson@arm.com
39011484Snikos.nikoleris@arm.com        if (blk == nullptr) {
39111051Sandreas.hansson@arm.com            // need to do a replacement
39211051Sandreas.hansson@arm.com            blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks);
39311484Snikos.nikoleris@arm.com            if (blk == nullptr) {
39411051Sandreas.hansson@arm.com                // no replaceable block available: give up, fwd to next level.
39511051Sandreas.hansson@arm.com                incMissCount(pkt);
39611051Sandreas.hansson@arm.com                return false;
39711051Sandreas.hansson@arm.com            }
39811051Sandreas.hansson@arm.com            tags->insertBlock(pkt, blk);
39911051Sandreas.hansson@arm.com
40012691Sodanrc@yahoo.com.br            blk->status |= (BlkValid | BlkReadable);
40111051Sandreas.hansson@arm.com        }
40211199Sandreas.hansson@arm.com        // only mark the block dirty if we got a writeback command,
40311199Sandreas.hansson@arm.com        // and leave it as is for a clean writeback
40411199Sandreas.hansson@arm.com        if (pkt->cmd == MemCmd::WritebackDirty) {
40512500Snikos.nikoleris@arm.com            assert(!blk->isDirty());
40611199Sandreas.hansson@arm.com            blk->status |= BlkDirty;
40711199Sandreas.hansson@arm.com        }
40811284Sandreas.hansson@arm.com        // if the packet does not have sharers, it is passing
40911284Sandreas.hansson@arm.com        // writable, and we got the writeback in Modified or Exclusive
41011284Sandreas.hansson@arm.com        // state, if not we are in the Owned or Shared state
41111284Sandreas.hansson@arm.com        if (!pkt->hasSharers()) {
41211051Sandreas.hansson@arm.com            blk->status |= BlkWritable;
41311051Sandreas.hansson@arm.com        }
41411051Sandreas.hansson@arm.com        // nothing else to do; writeback doesn't expect response
41511051Sandreas.hansson@arm.com        assert(!pkt->needsResponse());
41612633Sodanrc@yahoo.com.br        pkt->writeDataToBlock(blk->data, blkSize);
41711051Sandreas.hansson@arm.com        DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
41811051Sandreas.hansson@arm.com        incHitCount(pkt);
41912556Snikos.nikoleris@arm.com        // populate the time when the block will be ready to access.
42012556Snikos.nikoleris@arm.com        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
42112556Snikos.nikoleris@arm.com            pkt->payloadDelay;
42211051Sandreas.hansson@arm.com        return true;
42311051Sandreas.hansson@arm.com    } else if (pkt->cmd == MemCmd::CleanEvict) {
42411484Snikos.nikoleris@arm.com        if (blk != nullptr) {
42511051Sandreas.hansson@arm.com            // Found the block in the tags, need to stop CleanEvict from
42611051Sandreas.hansson@arm.com            // propagating further down the hierarchy. Returning true will
42711051Sandreas.hansson@arm.com            // treat the CleanEvict like a satisfied write request and delete
42811051Sandreas.hansson@arm.com            // it.
42911051Sandreas.hansson@arm.com            return true;
43011051Sandreas.hansson@arm.com        }
43111051Sandreas.hansson@arm.com        // We didn't find the block here, propagate the CleanEvict further
43211051Sandreas.hansson@arm.com        // down the memory hierarchy. Returning false will treat the CleanEvict
43311051Sandreas.hansson@arm.com        // like a Writeback which could not find a replaceable block so has to
43411051Sandreas.hansson@arm.com        // go to next level.
43511051Sandreas.hansson@arm.com        return false;
43612345Snikos.nikoleris@arm.com    } else if (pkt->cmd == MemCmd::WriteClean) {
43712345Snikos.nikoleris@arm.com        // WriteClean handling is a special case. We can allocate a
43812345Snikos.nikoleris@arm.com        // block directly if it doesn't exist and we can update the
43912345Snikos.nikoleris@arm.com        // block immediately. The WriteClean transfers the ownership
44012345Snikos.nikoleris@arm.com        // of the block as well.
44112345Snikos.nikoleris@arm.com        assert(blkSize == pkt->getSize());
44212345Snikos.nikoleris@arm.com
44312345Snikos.nikoleris@arm.com        if (!blk) {
44412346Snikos.nikoleris@arm.com            if (pkt->writeThrough()) {
44512346Snikos.nikoleris@arm.com                // if this is a write through packet, we don't try to
44612346Snikos.nikoleris@arm.com                // allocate if the block is not present
44712345Snikos.nikoleris@arm.com                return false;
44812346Snikos.nikoleris@arm.com            } else {
44912346Snikos.nikoleris@arm.com                // a writeback that misses needs to allocate a new block
45012346Snikos.nikoleris@arm.com                blk = allocateBlock(pkt->getAddr(), pkt->isSecure(),
45112346Snikos.nikoleris@arm.com                                    writebacks);
45212346Snikos.nikoleris@arm.com                if (!blk) {
45312346Snikos.nikoleris@arm.com                    // no replaceable block available: give up, fwd to
45412346Snikos.nikoleris@arm.com                    // next level.
45512346Snikos.nikoleris@arm.com                    incMissCount(pkt);
45612346Snikos.nikoleris@arm.com                    return false;
45712346Snikos.nikoleris@arm.com                }
45812346Snikos.nikoleris@arm.com                tags->insertBlock(pkt, blk);
45912346Snikos.nikoleris@arm.com
46012691Sodanrc@yahoo.com.br                blk->status |= (BlkValid | BlkReadable);
46112345Snikos.nikoleris@arm.com            }
46212345Snikos.nikoleris@arm.com        }
46312345Snikos.nikoleris@arm.com
46412345Snikos.nikoleris@arm.com        // at this point either this is a writeback or a write-through
46512345Snikos.nikoleris@arm.com        // write clean operation and the block is already in this
46612345Snikos.nikoleris@arm.com        // cache, we need to update the data and the block flags
46712345Snikos.nikoleris@arm.com        assert(blk);
46812500Snikos.nikoleris@arm.com        assert(!blk->isDirty());
46912346Snikos.nikoleris@arm.com        if (!pkt->writeThrough()) {
47012346Snikos.nikoleris@arm.com            blk->status |= BlkDirty;
47112346Snikos.nikoleris@arm.com        }
47212345Snikos.nikoleris@arm.com        // nothing else to do; writeback doesn't expect response
47312345Snikos.nikoleris@arm.com        assert(!pkt->needsResponse());
47412633Sodanrc@yahoo.com.br        pkt->writeDataToBlock(blk->data, blkSize);
47512345Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print());
47612345Snikos.nikoleris@arm.com
47712345Snikos.nikoleris@arm.com        incHitCount(pkt);
47812345Snikos.nikoleris@arm.com        // populate the time when the block will be ready to access.
47912345Snikos.nikoleris@arm.com        blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay +
48012345Snikos.nikoleris@arm.com            pkt->payloadDelay;
48112346Snikos.nikoleris@arm.com        // if this a write-through packet it will be sent to cache
48212346Snikos.nikoleris@arm.com        // below
48312346Snikos.nikoleris@arm.com        return !pkt->writeThrough();
48411601Sandreas.hansson@arm.com    } else if (blk && (pkt->needsWritable() ? blk->isWritable() :
48511601Sandreas.hansson@arm.com                       blk->isReadable())) {
48611051Sandreas.hansson@arm.com        // OK to satisfy access
48711051Sandreas.hansson@arm.com        incHitCount(pkt);
48811601Sandreas.hansson@arm.com        satisfyRequest(pkt, blk);
48911601Sandreas.hansson@arm.com        maintainClusivity(pkt->fromCache(), blk);
49011601Sandreas.hansson@arm.com
49111051Sandreas.hansson@arm.com        return true;
49211051Sandreas.hansson@arm.com    }
49311051Sandreas.hansson@arm.com
49411484Snikos.nikoleris@arm.com    // Can't satisfy access normally... either no block (blk == nullptr)
49511284Sandreas.hansson@arm.com    // or have block but need writable
49611051Sandreas.hansson@arm.com
49711051Sandreas.hansson@arm.com    incMissCount(pkt);
49811051Sandreas.hansson@arm.com
49911484Snikos.nikoleris@arm.com    if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) {
50011051Sandreas.hansson@arm.com        // complete miss on store conditional... just give up now
50111051Sandreas.hansson@arm.com        pkt->req->setExtraData(0);
50211051Sandreas.hansson@arm.com        return true;
50311051Sandreas.hansson@arm.com    }
50411051Sandreas.hansson@arm.com
50511051Sandreas.hansson@arm.com    return false;
50611051Sandreas.hansson@arm.com}
50711051Sandreas.hansson@arm.com
50811051Sandreas.hansson@arm.comvoid
50911601Sandreas.hansson@arm.comCache::maintainClusivity(bool from_cache, CacheBlk *blk)
51011601Sandreas.hansson@arm.com{
51111601Sandreas.hansson@arm.com    if (from_cache && blk && blk->isValid() && !blk->isDirty() &&
51211601Sandreas.hansson@arm.com        clusivity == Enums::mostly_excl) {
51311601Sandreas.hansson@arm.com        // if we have responded to a cache, and our block is still
51411601Sandreas.hansson@arm.com        // valid, but not dirty, and this cache is mostly exclusive
51511601Sandreas.hansson@arm.com        // with respect to the cache above, drop the block
51611601Sandreas.hansson@arm.com        invalidateBlock(blk);
51711601Sandreas.hansson@arm.com    }
51811601Sandreas.hansson@arm.com}
51911601Sandreas.hansson@arm.com
52011601Sandreas.hansson@arm.comvoid
52111051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time)
52211051Sandreas.hansson@arm.com{
52311051Sandreas.hansson@arm.com    while (!writebacks.empty()) {
52411051Sandreas.hansson@arm.com        PacketPtr wbPkt = writebacks.front();
52511051Sandreas.hansson@arm.com        // We use forwardLatency here because we are copying writebacks to
52612345Snikos.nikoleris@arm.com        // write buffer.
52712345Snikos.nikoleris@arm.com
52812345Snikos.nikoleris@arm.com        // Call isCachedAbove for Writebacks, CleanEvicts and
52912345Snikos.nikoleris@arm.com        // WriteCleans to discover if the block is cached above.
53011051Sandreas.hansson@arm.com        if (isCachedAbove(wbPkt)) {
53111051Sandreas.hansson@arm.com            if (wbPkt->cmd == MemCmd::CleanEvict) {
53211051Sandreas.hansson@arm.com                // Delete CleanEvict because cached copies exist above. The
53311051Sandreas.hansson@arm.com                // packet destructor will delete the request object because
53411051Sandreas.hansson@arm.com                // this is a non-snoop request packet which does not require a
53511051Sandreas.hansson@arm.com                // response.
53611051Sandreas.hansson@arm.com                delete wbPkt;
53711199Sandreas.hansson@arm.com            } else if (wbPkt->cmd == MemCmd::WritebackClean) {
53811199Sandreas.hansson@arm.com                // clean writeback, do not send since the block is
53911199Sandreas.hansson@arm.com                // still cached above
54011199Sandreas.hansson@arm.com                assert(writebackClean);
54111199Sandreas.hansson@arm.com                delete wbPkt;
54211051Sandreas.hansson@arm.com            } else {
54312345Snikos.nikoleris@arm.com                assert(wbPkt->cmd == MemCmd::WritebackDirty ||
54412345Snikos.nikoleris@arm.com                       wbPkt->cmd == MemCmd::WriteClean);
54511051Sandreas.hansson@arm.com                // Set BLOCK_CACHED flag in Writeback and send below, so that
54611051Sandreas.hansson@arm.com                // the Writeback does not reset the bit corresponding to this
54711051Sandreas.hansson@arm.com                // address in the snoop filter below.
54811051Sandreas.hansson@arm.com                wbPkt->setBlockCached();
54911051Sandreas.hansson@arm.com                allocateWriteBuffer(wbPkt, forward_time);
55011051Sandreas.hansson@arm.com            }
55111051Sandreas.hansson@arm.com        } else {
55211051Sandreas.hansson@arm.com            // If the block is not cached above, send packet below. Both
55311051Sandreas.hansson@arm.com            // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
55411051Sandreas.hansson@arm.com            // reset the bit corresponding to this address in the snoop filter
55511051Sandreas.hansson@arm.com            // below.
55611051Sandreas.hansson@arm.com            allocateWriteBuffer(wbPkt, forward_time);
55711051Sandreas.hansson@arm.com        }
55811051Sandreas.hansson@arm.com        writebacks.pop_front();
55911051Sandreas.hansson@arm.com    }
56011051Sandreas.hansson@arm.com}
56111051Sandreas.hansson@arm.com
56211130Sali.jafri@arm.comvoid
56311130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks)
56411130Sali.jafri@arm.com{
56511130Sali.jafri@arm.com    while (!writebacks.empty()) {
56611130Sali.jafri@arm.com        PacketPtr wbPkt = writebacks.front();
56711130Sali.jafri@arm.com        // Call isCachedAbove for both Writebacks and CleanEvicts. If
56811130Sali.jafri@arm.com        // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks
56911130Sali.jafri@arm.com        // and discard CleanEvicts.
57011130Sali.jafri@arm.com        if (isCachedAbove(wbPkt, false)) {
57112345Snikos.nikoleris@arm.com            if (wbPkt->cmd == MemCmd::WritebackDirty ||
57212345Snikos.nikoleris@arm.com                wbPkt->cmd == MemCmd::WriteClean) {
57311130Sali.jafri@arm.com                // Set BLOCK_CACHED flag in Writeback and send below,
57411130Sali.jafri@arm.com                // so that the Writeback does not reset the bit
57511130Sali.jafri@arm.com                // corresponding to this address in the snoop filter
57611130Sali.jafri@arm.com                // below. We can discard CleanEvicts because cached
57711130Sali.jafri@arm.com                // copies exist above. Atomic mode isCachedAbove
57811130Sali.jafri@arm.com                // modifies packet to set BLOCK_CACHED flag
57911130Sali.jafri@arm.com                memSidePort->sendAtomic(wbPkt);
58011130Sali.jafri@arm.com            }
58111130Sali.jafri@arm.com        } else {
58211130Sali.jafri@arm.com            // If the block is not cached above, send packet below. Both
58311130Sali.jafri@arm.com            // CleanEvict and Writeback with BLOCK_CACHED flag cleared will
58411130Sali.jafri@arm.com            // reset the bit corresponding to this address in the snoop filter
58511130Sali.jafri@arm.com            // below.
58611130Sali.jafri@arm.com            memSidePort->sendAtomic(wbPkt);
58711130Sali.jafri@arm.com        }
58811130Sali.jafri@arm.com        writebacks.pop_front();
58911130Sali.jafri@arm.com        // In case of CleanEvicts, the packet destructor will delete the
59011130Sali.jafri@arm.com        // request object because this is a non-snoop request packet which
59111130Sali.jafri@arm.com        // does not require a response.
59211130Sali.jafri@arm.com        delete wbPkt;
59311130Sali.jafri@arm.com    }
59411130Sali.jafri@arm.com}
59511130Sali.jafri@arm.com
59611051Sandreas.hansson@arm.com
59711051Sandreas.hansson@arm.comvoid
59811051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt)
59911051Sandreas.hansson@arm.com{
60011744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s for %s\n", __func__, pkt->print());
60111051Sandreas.hansson@arm.com
60211051Sandreas.hansson@arm.com    assert(pkt->isResponse());
60311051Sandreas.hansson@arm.com    assert(!system->bypassCaches());
60411051Sandreas.hansson@arm.com
60511276Sandreas.hansson@arm.com    // determine if the response is from a snoop request we created
60611276Sandreas.hansson@arm.com    // (in which case it should be in the outstandingSnoop), or if we
60711276Sandreas.hansson@arm.com    // merely forwarded someone else's snoop request
60811276Sandreas.hansson@arm.com    const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) ==
60911276Sandreas.hansson@arm.com        outstandingSnoop.end();
61011276Sandreas.hansson@arm.com
61111276Sandreas.hansson@arm.com    if (!forwardAsSnoop) {
61211276Sandreas.hansson@arm.com        // the packet came from this cache, so sink it here and do not
61311276Sandreas.hansson@arm.com        // forward it
61411051Sandreas.hansson@arm.com        assert(pkt->cmd == MemCmd::HardPFResp);
61511276Sandreas.hansson@arm.com
61611276Sandreas.hansson@arm.com        outstandingSnoop.erase(pkt->req);
61711276Sandreas.hansson@arm.com
61811276Sandreas.hansson@arm.com        DPRINTF(Cache, "Got prefetch response from above for addr "
61911276Sandreas.hansson@arm.com                "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns");
62011051Sandreas.hansson@arm.com        recvTimingResp(pkt);
62111051Sandreas.hansson@arm.com        return;
62211051Sandreas.hansson@arm.com    }
62311051Sandreas.hansson@arm.com
62411051Sandreas.hansson@arm.com    // forwardLatency is set here because there is a response from an
62511051Sandreas.hansson@arm.com    // upper level cache.
62611051Sandreas.hansson@arm.com    // To pay the delay that occurs if the packet comes from the bus,
62711051Sandreas.hansson@arm.com    // we charge also headerDelay.
62811051Sandreas.hansson@arm.com    Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay;
62911051Sandreas.hansson@arm.com    // Reset the timing of the packet.
63011051Sandreas.hansson@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
63111051Sandreas.hansson@arm.com    memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time);
63211051Sandreas.hansson@arm.com}
63311051Sandreas.hansson@arm.com
63411051Sandreas.hansson@arm.comvoid
63511051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt)
63611051Sandreas.hansson@arm.com{
63711051Sandreas.hansson@arm.com    // Cache line clearing instructions
63811051Sandreas.hansson@arm.com    if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) &&
63911051Sandreas.hansson@arm.com        (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) {
64011051Sandreas.hansson@arm.com        pkt->cmd = MemCmd::WriteLineReq;
64111051Sandreas.hansson@arm.com        DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n");
64211051Sandreas.hansson@arm.com    }
64311051Sandreas.hansson@arm.com}
64411051Sandreas.hansson@arm.com
64512630Snikos.nikoleris@arm.comvoid
64611051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt)
64711051Sandreas.hansson@arm.com{
64811830Sbaz21@cam.ac.uk    DPRINTF(CacheTags, "%s tags:\n%s\n", __func__, tags->print());
64911051Sandreas.hansson@arm.com
65011051Sandreas.hansson@arm.com    assert(pkt->isRequest());
65111051Sandreas.hansson@arm.com
65211051Sandreas.hansson@arm.com    // Just forward the packet if caches are disabled.
65311051Sandreas.hansson@arm.com    if (system->bypassCaches()) {
65411051Sandreas.hansson@arm.com        // @todo This should really enqueue the packet rather
65511051Sandreas.hansson@arm.com        bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt);
65611051Sandreas.hansson@arm.com        assert(success);
65712630Snikos.nikoleris@arm.com        return;
65811051Sandreas.hansson@arm.com    }
65911051Sandreas.hansson@arm.com
66011051Sandreas.hansson@arm.com    promoteWholeLineWrites(pkt);
66111051Sandreas.hansson@arm.com
66212349Snikos.nikoleris@arm.com    // Cache maintenance operations have to visit all the caches down
66312349Snikos.nikoleris@arm.com    // to the specified xbar (PoC, PoU, etc.). Even if a cache above
66412349Snikos.nikoleris@arm.com    // is responding we forward the packet to the memory below rather
66512349Snikos.nikoleris@arm.com    // than creating an express snoop.
66611284Sandreas.hansson@arm.com    if (pkt->cacheResponding()) {
66711051Sandreas.hansson@arm.com        // a cache above us (but not where the packet came from) is
66811284Sandreas.hansson@arm.com        // responding to the request, in other words it has the line
66911284Sandreas.hansson@arm.com        // in Modified or Owned state
67011744Snikos.nikoleris@arm.com        DPRINTF(Cache, "Cache above responding to %s: not responding\n",
67111744Snikos.nikoleris@arm.com                pkt->print());
67211051Sandreas.hansson@arm.com
67311284Sandreas.hansson@arm.com        // if the packet needs the block to be writable, and the cache
67411284Sandreas.hansson@arm.com        // that has promised to respond (setting the cache responding
67511284Sandreas.hansson@arm.com        // flag) is not providing writable (it is in Owned rather than
67611284Sandreas.hansson@arm.com        // the Modified state), we know that there may be other Shared
67711284Sandreas.hansson@arm.com        // copies in the system; go out and invalidate them all
67811334Sandreas.hansson@arm.com        assert(pkt->needsWritable() && !pkt->responderHadWritable());
67911284Sandreas.hansson@arm.com
68011334Sandreas.hansson@arm.com        // an upstream cache that had the line in Owned state
68111334Sandreas.hansson@arm.com        // (dirty, but not writable), is responding and thus
68211334Sandreas.hansson@arm.com        // transferring the dirty line from one branch of the
68311334Sandreas.hansson@arm.com        // cache hierarchy to another
68411284Sandreas.hansson@arm.com
68511334Sandreas.hansson@arm.com        // send out an express snoop and invalidate all other
68611334Sandreas.hansson@arm.com        // copies (snooping a packet that needs writable is the
68711334Sandreas.hansson@arm.com        // same as an invalidation), thus turning the Owned line
68811334Sandreas.hansson@arm.com        // into a Modified line, note that we don't invalidate the
68911334Sandreas.hansson@arm.com        // block in the current cache or any other cache on the
69011334Sandreas.hansson@arm.com        // path to memory
69111051Sandreas.hansson@arm.com
69211334Sandreas.hansson@arm.com        // create a downstream express snoop with cleared packet
69311334Sandreas.hansson@arm.com        // flags, there is no need to allocate any data as the
69411334Sandreas.hansson@arm.com        // packet is merely used to co-ordinate state transitions
69511334Sandreas.hansson@arm.com        Packet *snoop_pkt = new Packet(pkt, true, false);
69611051Sandreas.hansson@arm.com
69711334Sandreas.hansson@arm.com        // also reset the bus time that the original packet has
69811334Sandreas.hansson@arm.com        // not yet paid for
69911334Sandreas.hansson@arm.com        snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0;
70011051Sandreas.hansson@arm.com
70111334Sandreas.hansson@arm.com        // make this an instantaneous express snoop, and let the
70211334Sandreas.hansson@arm.com        // other caches in the system know that the another cache
70311334Sandreas.hansson@arm.com        // is responding, because we have found the authorative
70411334Sandreas.hansson@arm.com        // copy (Modified or Owned) that will supply the right
70511334Sandreas.hansson@arm.com        // data
70611334Sandreas.hansson@arm.com        snoop_pkt->setExpressSnoop();
70711334Sandreas.hansson@arm.com        snoop_pkt->setCacheResponding();
70811051Sandreas.hansson@arm.com
70911334Sandreas.hansson@arm.com        // this express snoop travels towards the memory, and at
71011334Sandreas.hansson@arm.com        // every crossbar it is snooped upwards thus reaching
71111334Sandreas.hansson@arm.com        // every cache in the system
71211334Sandreas.hansson@arm.com        bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt);
71311334Sandreas.hansson@arm.com        // express snoops always succeed
71411334Sandreas.hansson@arm.com        assert(success);
71511334Sandreas.hansson@arm.com
71611334Sandreas.hansson@arm.com        // main memory will delete the snoop packet
71711051Sandreas.hansson@arm.com
71811284Sandreas.hansson@arm.com        // queue for deletion, as opposed to immediate deletion, as
71911284Sandreas.hansson@arm.com        // the sending cache is still relying on the packet
72011190Sandreas.hansson@arm.com        pendingDelete.reset(pkt);
72111051Sandreas.hansson@arm.com
72211334Sandreas.hansson@arm.com        // no need to take any further action in this particular cache
72311334Sandreas.hansson@arm.com        // as an upstram cache has already committed to responding,
72411334Sandreas.hansson@arm.com        // and we have already sent out any express snoops in the
72511334Sandreas.hansson@arm.com        // section above to ensure all other copies in the system are
72611334Sandreas.hansson@arm.com        // invalidated
72712630Snikos.nikoleris@arm.com        return;
72811051Sandreas.hansson@arm.com    }
72911051Sandreas.hansson@arm.com
73011051Sandreas.hansson@arm.com    // anything that is merely forwarded pays for the forward latency and
73111051Sandreas.hansson@arm.com    // the delay provided by the crossbar
73211051Sandreas.hansson@arm.com    Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
73311051Sandreas.hansson@arm.com
73411051Sandreas.hansson@arm.com    // We use lookupLatency here because it is used to specify the latency
73511051Sandreas.hansson@arm.com    // to access.
73611051Sandreas.hansson@arm.com    Cycles lat = lookupLatency;
73711484Snikos.nikoleris@arm.com    CacheBlk *blk = nullptr;
73811051Sandreas.hansson@arm.com    bool satisfied = false;
73911051Sandreas.hansson@arm.com    {
74011051Sandreas.hansson@arm.com        PacketList writebacks;
74111051Sandreas.hansson@arm.com        // Note that lat is passed by reference here. The function
74211051Sandreas.hansson@arm.com        // access() calls accessBlock() which can modify lat value.
74311051Sandreas.hansson@arm.com        satisfied = access(pkt, blk, lat, writebacks);
74411051Sandreas.hansson@arm.com
74511051Sandreas.hansson@arm.com        // copy writebacks to write buffer here to ensure they logically
74611051Sandreas.hansson@arm.com        // proceed anything happening below
74711051Sandreas.hansson@arm.com        doWritebacks(writebacks, forward_time);
74811051Sandreas.hansson@arm.com    }
74911051Sandreas.hansson@arm.com
75011051Sandreas.hansson@arm.com    // Here we charge the headerDelay that takes into account the latencies
75111051Sandreas.hansson@arm.com    // of the bus, if the packet comes from it.
75211051Sandreas.hansson@arm.com    // The latency charged it is just lat that is the value of lookupLatency
75311051Sandreas.hansson@arm.com    // modified by access() function, or if not just lookupLatency.
75411051Sandreas.hansson@arm.com    // In case of a hit we are neglecting response latency.
75511051Sandreas.hansson@arm.com    // In case of a miss we are neglecting forward latency.
75611051Sandreas.hansson@arm.com    Tick request_time = clockEdge(lat) + pkt->headerDelay;
75711051Sandreas.hansson@arm.com    // Here we reset the timing of the packet.
75811051Sandreas.hansson@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
75911051Sandreas.hansson@arm.com
76011051Sandreas.hansson@arm.com    // track time of availability of next prefetch, if any
76111051Sandreas.hansson@arm.com    Tick next_pf_time = MaxTick;
76211051Sandreas.hansson@arm.com
76311051Sandreas.hansson@arm.com    bool needsResponse = pkt->needsResponse();
76411051Sandreas.hansson@arm.com
76511051Sandreas.hansson@arm.com    if (satisfied) {
76611051Sandreas.hansson@arm.com        // should never be satisfying an uncacheable access as we
76711051Sandreas.hansson@arm.com        // flush and invalidate any existing block as part of the
76811051Sandreas.hansson@arm.com        // lookup
76911051Sandreas.hansson@arm.com        assert(!pkt->req->isUncacheable());
77011051Sandreas.hansson@arm.com
77111051Sandreas.hansson@arm.com        // hit (for all other request types)
77211051Sandreas.hansson@arm.com
77311483Snikos.nikoleris@arm.com        if (prefetcher && (prefetchOnAccess ||
77411483Snikos.nikoleris@arm.com                           (blk && blk->wasPrefetched()))) {
77511051Sandreas.hansson@arm.com            if (blk)
77611051Sandreas.hansson@arm.com                blk->status &= ~BlkHWPrefetched;
77711051Sandreas.hansson@arm.com
77811051Sandreas.hansson@arm.com            // Don't notify on SWPrefetch
77912349Snikos.nikoleris@arm.com            if (!pkt->cmd.isSWPrefetch()) {
78012349Snikos.nikoleris@arm.com                assert(!pkt->req->isCacheMaintenance());
78111051Sandreas.hansson@arm.com                next_pf_time = prefetcher->notify(pkt);
78212349Snikos.nikoleris@arm.com            }
78311051Sandreas.hansson@arm.com        }
78411051Sandreas.hansson@arm.com
78511051Sandreas.hansson@arm.com        if (needsResponse) {
78611051Sandreas.hansson@arm.com            pkt->makeTimingResponse();
78711051Sandreas.hansson@arm.com            // @todo: Make someone pay for this
78811051Sandreas.hansson@arm.com            pkt->headerDelay = pkt->payloadDelay = 0;
78911051Sandreas.hansson@arm.com
79011051Sandreas.hansson@arm.com            // In this case we are considering request_time that takes
79111051Sandreas.hansson@arm.com            // into account the delay of the xbar, if any, and just
79211051Sandreas.hansson@arm.com            // lat, neglecting responseLatency, modelling hit latency
79311051Sandreas.hansson@arm.com            // just as lookupLatency or or the value of lat overriden
79411051Sandreas.hansson@arm.com            // by access(), that calls accessBlock() function.
79511194Sali.jafri@arm.com            cpuSidePort->schedTimingResp(pkt, request_time, true);
79611051Sandreas.hansson@arm.com        } else {
79711744Snikos.nikoleris@arm.com            DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
79811744Snikos.nikoleris@arm.com                    pkt->print());
79911199Sandreas.hansson@arm.com
80011190Sandreas.hansson@arm.com            // queue the packet for deletion, as the sending cache is
80111190Sandreas.hansson@arm.com            // still relying on it; if the block is found in access(),
80211190Sandreas.hansson@arm.com            // CleanEvict and Writeback messages will be deleted
80311190Sandreas.hansson@arm.com            // here as well
80411190Sandreas.hansson@arm.com            pendingDelete.reset(pkt);
80511051Sandreas.hansson@arm.com        }
80611051Sandreas.hansson@arm.com    } else {
80711051Sandreas.hansson@arm.com        // miss
80811051Sandreas.hansson@arm.com
80911892Snikos.nikoleris@arm.com        Addr blk_addr = pkt->getBlockAddr(blkSize);
81011051Sandreas.hansson@arm.com
81111051Sandreas.hansson@arm.com        // ignore any existing MSHR if we are dealing with an
81211051Sandreas.hansson@arm.com        // uncacheable request
81311051Sandreas.hansson@arm.com        MSHR *mshr = pkt->req->isUncacheable() ? nullptr :
81411051Sandreas.hansson@arm.com            mshrQueue.findMatch(blk_addr, pkt->isSecure());
81511051Sandreas.hansson@arm.com
81611051Sandreas.hansson@arm.com        // Software prefetch handling:
81711051Sandreas.hansson@arm.com        // To keep the core from waiting on data it won't look at
81811051Sandreas.hansson@arm.com        // anyway, send back a response with dummy data. Miss handling
81911051Sandreas.hansson@arm.com        // will continue asynchronously. Unfortunately, the core will
82011051Sandreas.hansson@arm.com        // insist upon freeing original Packet/Request, so we have to
82111051Sandreas.hansson@arm.com        // create a new pair with a different lifecycle. Note that this
82211051Sandreas.hansson@arm.com        // processing happens before any MSHR munging on the behalf of
82311051Sandreas.hansson@arm.com        // this request because this new Request will be the one stored
82411051Sandreas.hansson@arm.com        // into the MSHRs, not the original.
82511051Sandreas.hansson@arm.com        if (pkt->cmd.isSWPrefetch()) {
82611051Sandreas.hansson@arm.com            assert(needsResponse);
82711051Sandreas.hansson@arm.com            assert(pkt->req->hasPaddr());
82811051Sandreas.hansson@arm.com            assert(!pkt->req->isUncacheable());
82911051Sandreas.hansson@arm.com
83011051Sandreas.hansson@arm.com            // There's no reason to add a prefetch as an additional target
83111051Sandreas.hansson@arm.com            // to an existing MSHR. If an outstanding request is already
83211051Sandreas.hansson@arm.com            // in progress, there is nothing for the prefetch to do.
83311051Sandreas.hansson@arm.com            // If this is the case, we don't even create a request at all.
83411051Sandreas.hansson@arm.com            PacketPtr pf = nullptr;
83511051Sandreas.hansson@arm.com
83611051Sandreas.hansson@arm.com            if (!mshr) {
83711051Sandreas.hansson@arm.com                // copy the request and create a new SoftPFReq packet
83811051Sandreas.hansson@arm.com                RequestPtr req = new Request(pkt->req->getPaddr(),
83911051Sandreas.hansson@arm.com                                             pkt->req->getSize(),
84011051Sandreas.hansson@arm.com                                             pkt->req->getFlags(),
84111051Sandreas.hansson@arm.com                                             pkt->req->masterId());
84211051Sandreas.hansson@arm.com                pf = new Packet(req, pkt->cmd);
84311051Sandreas.hansson@arm.com                pf->allocate();
84411051Sandreas.hansson@arm.com                assert(pf->getAddr() == pkt->getAddr());
84511051Sandreas.hansson@arm.com                assert(pf->getSize() == pkt->getSize());
84611051Sandreas.hansson@arm.com            }
84711051Sandreas.hansson@arm.com
84811051Sandreas.hansson@arm.com            pkt->makeTimingResponse();
84911286Sandreas.hansson@arm.com
85011051Sandreas.hansson@arm.com            // request_time is used here, taking into account lat and the delay
85111051Sandreas.hansson@arm.com            // charged if the packet comes from the xbar.
85211194Sali.jafri@arm.com            cpuSidePort->schedTimingResp(pkt, request_time, true);
85311051Sandreas.hansson@arm.com
85411051Sandreas.hansson@arm.com            // If an outstanding request is in progress (we found an
85511051Sandreas.hansson@arm.com            // MSHR) this is set to null
85611051Sandreas.hansson@arm.com            pkt = pf;
85711051Sandreas.hansson@arm.com        }
85811051Sandreas.hansson@arm.com
85911051Sandreas.hansson@arm.com        if (mshr) {
86011051Sandreas.hansson@arm.com            /// MSHR hit
86111051Sandreas.hansson@arm.com            /// @note writebacks will be checked in getNextMSHR()
86211051Sandreas.hansson@arm.com            /// for any conflicting requests to the same block
86311051Sandreas.hansson@arm.com
86411051Sandreas.hansson@arm.com            //@todo remove hw_pf here
86511051Sandreas.hansson@arm.com
86611051Sandreas.hansson@arm.com            // Coalesce unless it was a software prefetch (see above).
86711051Sandreas.hansson@arm.com            if (pkt) {
86811199Sandreas.hansson@arm.com                assert(!pkt->isWriteback());
86911199Sandreas.hansson@arm.com                // CleanEvicts corresponding to blocks which have
87011199Sandreas.hansson@arm.com                // outstanding requests in MSHRs are simply sunk here
87111051Sandreas.hansson@arm.com                if (pkt->cmd == MemCmd::CleanEvict) {
87211190Sandreas.hansson@arm.com                    pendingDelete.reset(pkt);
87312349Snikos.nikoleris@arm.com                } else if (pkt->cmd == MemCmd::WriteClean) {
87412349Snikos.nikoleris@arm.com                    // A WriteClean should never coalesce with any
87512349Snikos.nikoleris@arm.com                    // outstanding cache maintenance requests.
87612349Snikos.nikoleris@arm.com
87712349Snikos.nikoleris@arm.com                    // We use forward_time here because there is an
87812349Snikos.nikoleris@arm.com                    // uncached memory write, forwarded to WriteBuffer.
87912349Snikos.nikoleris@arm.com                    allocateWriteBuffer(pkt, forward_time);
88011051Sandreas.hansson@arm.com                } else {
88111744Snikos.nikoleris@arm.com                    DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__,
88211744Snikos.nikoleris@arm.com                            pkt->print());
88311051Sandreas.hansson@arm.com
88411051Sandreas.hansson@arm.com                    assert(pkt->req->masterId() < system->maxMasters());
88511051Sandreas.hansson@arm.com                    mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
88611051Sandreas.hansson@arm.com                    // We use forward_time here because it is the same
88711051Sandreas.hansson@arm.com                    // considering new targets. We have multiple
88811051Sandreas.hansson@arm.com                    // requests for the same address here. It
88911051Sandreas.hansson@arm.com                    // specifies the latency to allocate an internal
89011051Sandreas.hansson@arm.com                    // buffer and to schedule an event to the queued
89111051Sandreas.hansson@arm.com                    // port and also takes into account the additional
89211051Sandreas.hansson@arm.com                    // delay of the xbar.
89311197Sandreas.hansson@arm.com                    mshr->allocateTarget(pkt, forward_time, order++,
89411197Sandreas.hansson@arm.com                                         allocOnFill(pkt->cmd));
89511051Sandreas.hansson@arm.com                    if (mshr->getNumTargets() == numTarget) {
89611051Sandreas.hansson@arm.com                        noTargetMSHR = mshr;
89711051Sandreas.hansson@arm.com                        setBlocked(Blocked_NoTargets);
89811051Sandreas.hansson@arm.com                        // need to be careful with this... if this mshr isn't
89911051Sandreas.hansson@arm.com                        // ready yet (i.e. time > curTick()), we don't want to
90011051Sandreas.hansson@arm.com                        // move it ahead of mshrs that are ready
90111051Sandreas.hansson@arm.com                        // mshrQueue.moveToFront(mshr);
90211051Sandreas.hansson@arm.com                    }
90311051Sandreas.hansson@arm.com                }
90411051Sandreas.hansson@arm.com                // We should call the prefetcher reguardless if the request is
90511483Snikos.nikoleris@arm.com                // satisfied or not, reguardless if the request is in the MSHR
90611483Snikos.nikoleris@arm.com                // or not.  The request could be a ReadReq hit, but still not
90711051Sandreas.hansson@arm.com                // satisfied (potentially because of a prior write to the same
90811051Sandreas.hansson@arm.com                // cache line.  So, even when not satisfied, tehre is an MSHR
90911483Snikos.nikoleris@arm.com                // already allocated for this, we need to let the prefetcher
91011483Snikos.nikoleris@arm.com                // know about the request
91111051Sandreas.hansson@arm.com                if (prefetcher) {
91211051Sandreas.hansson@arm.com                    // Don't notify on SWPrefetch
91312349Snikos.nikoleris@arm.com                    if (!pkt->cmd.isSWPrefetch() &&
91412349Snikos.nikoleris@arm.com                        !pkt->req->isCacheMaintenance())
91511051Sandreas.hansson@arm.com                        next_pf_time = prefetcher->notify(pkt);
91611051Sandreas.hansson@arm.com                }
91711051Sandreas.hansson@arm.com            }
91811051Sandreas.hansson@arm.com        } else {
91911051Sandreas.hansson@arm.com            // no MSHR
92011051Sandreas.hansson@arm.com            assert(pkt->req->masterId() < system->maxMasters());
92111051Sandreas.hansson@arm.com            if (pkt->req->isUncacheable()) {
92211051Sandreas.hansson@arm.com                mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++;
92311051Sandreas.hansson@arm.com            } else {
92411051Sandreas.hansson@arm.com                mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
92511051Sandreas.hansson@arm.com            }
92611051Sandreas.hansson@arm.com
92712345Snikos.nikoleris@arm.com            if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean ||
92811051Sandreas.hansson@arm.com                (pkt->req->isUncacheable() && pkt->isWrite())) {
92911051Sandreas.hansson@arm.com                // We use forward_time here because there is an
93011051Sandreas.hansson@arm.com                // uncached memory write, forwarded to WriteBuffer.
93111051Sandreas.hansson@arm.com                allocateWriteBuffer(pkt, forward_time);
93211051Sandreas.hansson@arm.com            } else {
93311051Sandreas.hansson@arm.com                if (blk && blk->isValid()) {
93411051Sandreas.hansson@arm.com                    // should have flushed and have no valid block
93511051Sandreas.hansson@arm.com                    assert(!pkt->req->isUncacheable());
93611051Sandreas.hansson@arm.com
93711051Sandreas.hansson@arm.com                    // If we have a write miss to a valid block, we
93811051Sandreas.hansson@arm.com                    // need to mark the block non-readable.  Otherwise
93911051Sandreas.hansson@arm.com                    // if we allow reads while there's an outstanding
94011051Sandreas.hansson@arm.com                    // write miss, the read could return stale data
94111051Sandreas.hansson@arm.com                    // out of the cache block... a more aggressive
94211051Sandreas.hansson@arm.com                    // system could detect the overlap (if any) and
94311051Sandreas.hansson@arm.com                    // forward data out of the MSHRs, but we don't do
94411051Sandreas.hansson@arm.com                    // that yet.  Note that we do need to leave the
94511051Sandreas.hansson@arm.com                    // block valid so that it stays in the cache, in
94611051Sandreas.hansson@arm.com                    // case we get an upgrade response (and hence no
94711051Sandreas.hansson@arm.com                    // new data) when the write miss completes.
94811051Sandreas.hansson@arm.com                    // As long as CPUs do proper store/load forwarding
94911051Sandreas.hansson@arm.com                    // internally, and have a sufficiently weak memory
95011051Sandreas.hansson@arm.com                    // model, this is probably unnecessary, but at some
95111051Sandreas.hansson@arm.com                    // point it must have seemed like we needed it...
95212349Snikos.nikoleris@arm.com                    assert((pkt->needsWritable() && !blk->isWritable()) ||
95312349Snikos.nikoleris@arm.com                           pkt->req->isCacheMaintenance());
95411051Sandreas.hansson@arm.com                    blk->status &= ~BlkReadable;
95511051Sandreas.hansson@arm.com                }
95611051Sandreas.hansson@arm.com                // Here we are using forward_time, modelling the latency of
95711051Sandreas.hansson@arm.com                // a miss (outbound) just as forwardLatency, neglecting the
95811051Sandreas.hansson@arm.com                // lookupLatency component.
95911051Sandreas.hansson@arm.com                allocateMissBuffer(pkt, forward_time);
96011051Sandreas.hansson@arm.com            }
96111051Sandreas.hansson@arm.com
96211051Sandreas.hansson@arm.com            if (prefetcher) {
96311051Sandreas.hansson@arm.com                // Don't notify on SWPrefetch
96412349Snikos.nikoleris@arm.com                if (!pkt->cmd.isSWPrefetch() &&
96512349Snikos.nikoleris@arm.com                    !pkt->req->isCacheMaintenance())
96611051Sandreas.hansson@arm.com                    next_pf_time = prefetcher->notify(pkt);
96711051Sandreas.hansson@arm.com            }
96811051Sandreas.hansson@arm.com        }
96911051Sandreas.hansson@arm.com    }
97011051Sandreas.hansson@arm.com
97111051Sandreas.hansson@arm.com    if (next_pf_time != MaxTick)
97211051Sandreas.hansson@arm.com        schedMemSideSendEvent(next_pf_time);
97311051Sandreas.hansson@arm.com}
97411051Sandreas.hansson@arm.com
97511051Sandreas.hansson@arm.comPacketPtr
97611452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
97711452Sandreas.hansson@arm.com                        bool needsWritable) const
97811051Sandreas.hansson@arm.com{
97911452Sandreas.hansson@arm.com    // should never see evictions here
98011452Sandreas.hansson@arm.com    assert(!cpu_pkt->isEviction());
98111452Sandreas.hansson@arm.com
98211051Sandreas.hansson@arm.com    bool blkValid = blk && blk->isValid();
98311051Sandreas.hansson@arm.com
98411452Sandreas.hansson@arm.com    if (cpu_pkt->req->isUncacheable() ||
98511745Sandreas.hansson@arm.com        (!blkValid && cpu_pkt->isUpgrade()) ||
98612349Snikos.nikoleris@arm.com        cpu_pkt->cmd == MemCmd::InvalidateReq || cpu_pkt->isClean()) {
98711452Sandreas.hansson@arm.com        // uncacheable requests and upgrades from upper-level caches
98811452Sandreas.hansson@arm.com        // that missed completely just go through as is
98911452Sandreas.hansson@arm.com        return nullptr;
99011051Sandreas.hansson@arm.com    }
99111051Sandreas.hansson@arm.com
99211051Sandreas.hansson@arm.com    assert(cpu_pkt->needsResponse());
99311051Sandreas.hansson@arm.com
99411051Sandreas.hansson@arm.com    MemCmd cmd;
99511051Sandreas.hansson@arm.com    // @TODO make useUpgrades a parameter.
99611051Sandreas.hansson@arm.com    // Note that ownership protocols require upgrade, otherwise a
99711051Sandreas.hansson@arm.com    // write miss on a shared owned block will generate a ReadExcl,
99811051Sandreas.hansson@arm.com    // which will clobber the owned copy.
99911051Sandreas.hansson@arm.com    const bool useUpgrades = true;
100011747Snikos.nikoleris@arm.com    if (cpu_pkt->cmd == MemCmd::WriteLineReq) {
100111747Snikos.nikoleris@arm.com        assert(!blkValid || !blk->isWritable());
100211747Snikos.nikoleris@arm.com        // forward as invalidate to all other caches, this gives us
100311747Snikos.nikoleris@arm.com        // the line in Exclusive state, and invalidates all other
100411747Snikos.nikoleris@arm.com        // copies
100511747Snikos.nikoleris@arm.com        cmd = MemCmd::InvalidateReq;
100611747Snikos.nikoleris@arm.com    } else if (blkValid && useUpgrades) {
100711284Sandreas.hansson@arm.com        // only reason to be here is that blk is read only and we need
100811284Sandreas.hansson@arm.com        // it to be writable
100911284Sandreas.hansson@arm.com        assert(needsWritable);
101011051Sandreas.hansson@arm.com        assert(!blk->isWritable());
101111051Sandreas.hansson@arm.com        cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq;
101211051Sandreas.hansson@arm.com    } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq ||
101311051Sandreas.hansson@arm.com               cpu_pkt->cmd == MemCmd::StoreCondFailReq) {
101411051Sandreas.hansson@arm.com        // Even though this SC will fail, we still need to send out the
101511051Sandreas.hansson@arm.com        // request and get the data to supply it to other snoopers in the case
101611051Sandreas.hansson@arm.com        // where the determination the StoreCond fails is delayed due to
101711051Sandreas.hansson@arm.com        // all caches not being on the same local bus.
101811051Sandreas.hansson@arm.com        cmd = MemCmd::SCUpgradeFailReq;
101911051Sandreas.hansson@arm.com    } else {
102011051Sandreas.hansson@arm.com        // block is invalid
102112425Snikos.nikoleris@arm.com
102212425Snikos.nikoleris@arm.com        // If the request does not need a writable there are two cases
102312425Snikos.nikoleris@arm.com        // where we need to ensure the response will not fetch the
102412425Snikos.nikoleris@arm.com        // block in dirty state:
102512425Snikos.nikoleris@arm.com        // * this cache is read only and it does not perform
102612425Snikos.nikoleris@arm.com        //   writebacks,
102712425Snikos.nikoleris@arm.com        // * this cache is mostly exclusive and will not fill (since
102812425Snikos.nikoleris@arm.com        //   it does not fill it will have to writeback the dirty data
102912425Snikos.nikoleris@arm.com        //   immediately which generates uneccesary writebacks).
103012425Snikos.nikoleris@arm.com        bool force_clean_rsp = isReadOnly || clusivity == Enums::mostly_excl;
103111284Sandreas.hansson@arm.com        cmd = needsWritable ? MemCmd::ReadExReq :
103212425Snikos.nikoleris@arm.com            (force_clean_rsp ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
103311051Sandreas.hansson@arm.com    }
103411051Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
103511051Sandreas.hansson@arm.com
103611284Sandreas.hansson@arm.com    // if there are upstream caches that have already marked the
103711284Sandreas.hansson@arm.com    // packet as having sharers (not passing writable), pass that info
103811284Sandreas.hansson@arm.com    // downstream
103911602Sandreas.hansson@arm.com    if (cpu_pkt->hasSharers() && !needsWritable) {
104011051Sandreas.hansson@arm.com        // note that cpu_pkt may have spent a considerable time in the
104111051Sandreas.hansson@arm.com        // MSHR queue and that the information could possibly be out
104211051Sandreas.hansson@arm.com        // of date, however, there is no harm in conservatively
104311284Sandreas.hansson@arm.com        // assuming the block has sharers
104411284Sandreas.hansson@arm.com        pkt->setHasSharers();
104511744Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s: passing hasSharers from %s to %s\n",
104611744Snikos.nikoleris@arm.com                __func__, cpu_pkt->print(), pkt->print());
104711051Sandreas.hansson@arm.com    }
104811051Sandreas.hansson@arm.com
104911051Sandreas.hansson@arm.com    // the packet should be block aligned
105011892Snikos.nikoleris@arm.com    assert(pkt->getAddr() == pkt->getBlockAddr(blkSize));
105111051Sandreas.hansson@arm.com
105211051Sandreas.hansson@arm.com    pkt->allocate();
105311744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: created %s from %s\n", __func__, pkt->print(),
105411744Snikos.nikoleris@arm.com            cpu_pkt->print());
105511051Sandreas.hansson@arm.com    return pkt;
105611051Sandreas.hansson@arm.com}
105711051Sandreas.hansson@arm.com
105811051Sandreas.hansson@arm.com
105911051Sandreas.hansson@arm.comTick
106011051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt)
106111051Sandreas.hansson@arm.com{
106211051Sandreas.hansson@arm.com    // We are in atomic mode so we pay just for lookupLatency here.
106311051Sandreas.hansson@arm.com    Cycles lat = lookupLatency;
106411051Sandreas.hansson@arm.com
106511051Sandreas.hansson@arm.com    // Forward the request if the system is in cache bypass mode.
106611051Sandreas.hansson@arm.com    if (system->bypassCaches())
106711051Sandreas.hansson@arm.com        return ticksToCycles(memSidePort->sendAtomic(pkt));
106811051Sandreas.hansson@arm.com
106911051Sandreas.hansson@arm.com    promoteWholeLineWrites(pkt);
107011051Sandreas.hansson@arm.com
107111333Sandreas.hansson@arm.com    // follow the same flow as in recvTimingReq, and check if a cache
107211333Sandreas.hansson@arm.com    // above us is responding
107312349Snikos.nikoleris@arm.com    if (pkt->cacheResponding() && !pkt->isClean()) {
107412349Snikos.nikoleris@arm.com        assert(!pkt->req->isCacheInvalidate());
107511744Snikos.nikoleris@arm.com        DPRINTF(Cache, "Cache above responding to %s: not responding\n",
107611744Snikos.nikoleris@arm.com                pkt->print());
107711333Sandreas.hansson@arm.com
107811333Sandreas.hansson@arm.com        // if a cache is responding, and it had the line in Owned
107911333Sandreas.hansson@arm.com        // rather than Modified state, we need to invalidate any
108011333Sandreas.hansson@arm.com        // copies that are not on the same path to memory
108111334Sandreas.hansson@arm.com        assert(pkt->needsWritable() && !pkt->responderHadWritable());
108211334Sandreas.hansson@arm.com        lat += ticksToCycles(memSidePort->sendAtomic(pkt));
108311051Sandreas.hansson@arm.com
108411051Sandreas.hansson@arm.com        return lat * clockPeriod();
108511051Sandreas.hansson@arm.com    }
108611051Sandreas.hansson@arm.com
108711051Sandreas.hansson@arm.com    // should assert here that there are no outstanding MSHRs or
108811051Sandreas.hansson@arm.com    // writebacks... that would mean that someone used an atomic
108911051Sandreas.hansson@arm.com    // access in timing mode
109011051Sandreas.hansson@arm.com
109111484Snikos.nikoleris@arm.com    CacheBlk *blk = nullptr;
109211051Sandreas.hansson@arm.com    PacketList writebacks;
109311051Sandreas.hansson@arm.com    bool satisfied = access(pkt, blk, lat, writebacks);
109411051Sandreas.hansson@arm.com
109512349Snikos.nikoleris@arm.com    if (pkt->isClean() && blk && blk->isDirty()) {
109612349Snikos.nikoleris@arm.com        // A cache clean opearation is looking for a dirty
109712349Snikos.nikoleris@arm.com        // block. If a dirty block is encountered a WriteClean
109812349Snikos.nikoleris@arm.com        // will update any copies to the path to the memory
109912349Snikos.nikoleris@arm.com        // until the point of reference.
110012349Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
110112349Snikos.nikoleris@arm.com                __func__, pkt->print(), blk->print());
110212351Snikos.nikoleris@arm.com        PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
110312349Snikos.nikoleris@arm.com        writebacks.push_back(wb_pkt);
110412349Snikos.nikoleris@arm.com        pkt->setSatisfied();
110512349Snikos.nikoleris@arm.com    }
110612349Snikos.nikoleris@arm.com
110711051Sandreas.hansson@arm.com    // handle writebacks resulting from the access here to ensure they
110811051Sandreas.hansson@arm.com    // logically proceed anything happening below
110911130Sali.jafri@arm.com    doWritebacksAtomic(writebacks);
111011051Sandreas.hansson@arm.com
111111051Sandreas.hansson@arm.com    if (!satisfied) {
111211051Sandreas.hansson@arm.com        // MISS
111311051Sandreas.hansson@arm.com
111411452Sandreas.hansson@arm.com        // deal with the packets that go through the write path of
111512345Snikos.nikoleris@arm.com        // the cache, i.e. any evictions and writes
111612345Snikos.nikoleris@arm.com        if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean ||
111711452Sandreas.hansson@arm.com            (pkt->req->isUncacheable() && pkt->isWrite())) {
111811452Sandreas.hansson@arm.com            lat += ticksToCycles(memSidePort->sendAtomic(pkt));
111911452Sandreas.hansson@arm.com            return lat * clockPeriod();
112011452Sandreas.hansson@arm.com        }
112111452Sandreas.hansson@arm.com        // only misses left
112211452Sandreas.hansson@arm.com
112311452Sandreas.hansson@arm.com        PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable());
112411051Sandreas.hansson@arm.com
112511484Snikos.nikoleris@arm.com        bool is_forward = (bus_pkt == nullptr);
112611051Sandreas.hansson@arm.com
112711051Sandreas.hansson@arm.com        if (is_forward) {
112811051Sandreas.hansson@arm.com            // just forwarding the same request to the next level
112911051Sandreas.hansson@arm.com            // no local cache operation involved
113011051Sandreas.hansson@arm.com            bus_pkt = pkt;
113111051Sandreas.hansson@arm.com        }
113211051Sandreas.hansson@arm.com
113311744Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s: Sending an atomic %s\n", __func__,
113411744Snikos.nikoleris@arm.com                bus_pkt->print());
113511051Sandreas.hansson@arm.com
113611051Sandreas.hansson@arm.com#if TRACING_ON
113711051Sandreas.hansson@arm.com        CacheBlk::State old_state = blk ? blk->status : 0;
113811051Sandreas.hansson@arm.com#endif
113911051Sandreas.hansson@arm.com
114011051Sandreas.hansson@arm.com        lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt));
114111051Sandreas.hansson@arm.com
114211452Sandreas.hansson@arm.com        bool is_invalidate = bus_pkt->isInvalidate();
114311452Sandreas.hansson@arm.com
114411051Sandreas.hansson@arm.com        // We are now dealing with the response handling
114511744Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s: Receive response: %s in state %i\n", __func__,
114611744Snikos.nikoleris@arm.com                bus_pkt->print(), old_state);
114711051Sandreas.hansson@arm.com
114811051Sandreas.hansson@arm.com        // If packet was a forward, the response (if any) is already
114911051Sandreas.hansson@arm.com        // in place in the bus_pkt == pkt structure, so we don't need
115011051Sandreas.hansson@arm.com        // to do anything.  Otherwise, use the separate bus_pkt to
115111051Sandreas.hansson@arm.com        // generate response to pkt and then delete it.
115211051Sandreas.hansson@arm.com        if (!is_forward) {
115311051Sandreas.hansson@arm.com            if (pkt->needsResponse()) {
115411051Sandreas.hansson@arm.com                assert(bus_pkt->isResponse());
115511051Sandreas.hansson@arm.com                if (bus_pkt->isError()) {
115611051Sandreas.hansson@arm.com                    pkt->makeAtomicResponse();
115711051Sandreas.hansson@arm.com                    pkt->copyError(bus_pkt);
115811051Sandreas.hansson@arm.com                } else if (pkt->cmd == MemCmd::WriteLineReq) {
115911051Sandreas.hansson@arm.com                    // note the use of pkt, not bus_pkt here.
116011051Sandreas.hansson@arm.com
116111051Sandreas.hansson@arm.com                    // write-line request to the cache that promoted
116211051Sandreas.hansson@arm.com                    // the write to a whole line
116311197Sandreas.hansson@arm.com                    blk = handleFill(pkt, blk, writebacks,
116411197Sandreas.hansson@arm.com                                     allocOnFill(pkt->cmd));
116511452Sandreas.hansson@arm.com                    assert(blk != NULL);
116611452Sandreas.hansson@arm.com                    is_invalidate = false;
116711601Sandreas.hansson@arm.com                    satisfyRequest(pkt, blk);
116811051Sandreas.hansson@arm.com                } else if (bus_pkt->isRead() ||
116911051Sandreas.hansson@arm.com                           bus_pkt->cmd == MemCmd::UpgradeResp) {
117011051Sandreas.hansson@arm.com                    // we're updating cache state to allow us to
117111051Sandreas.hansson@arm.com                    // satisfy the upstream request from the cache
117211197Sandreas.hansson@arm.com                    blk = handleFill(bus_pkt, blk, writebacks,
117311197Sandreas.hansson@arm.com                                     allocOnFill(pkt->cmd));
117411601Sandreas.hansson@arm.com                    satisfyRequest(pkt, blk);
117511601Sandreas.hansson@arm.com                    maintainClusivity(pkt->fromCache(), blk);
117611051Sandreas.hansson@arm.com                } else {
117711051Sandreas.hansson@arm.com                    // we're satisfying the upstream request without
117811051Sandreas.hansson@arm.com                    // modifying cache state, e.g., a write-through
117911051Sandreas.hansson@arm.com                    pkt->makeAtomicResponse();
118011051Sandreas.hansson@arm.com                }
118111051Sandreas.hansson@arm.com            }
118211051Sandreas.hansson@arm.com            delete bus_pkt;
118311051Sandreas.hansson@arm.com        }
118411452Sandreas.hansson@arm.com
118511452Sandreas.hansson@arm.com        if (is_invalidate && blk && blk->isValid()) {
118611452Sandreas.hansson@arm.com            invalidateBlock(blk);
118711452Sandreas.hansson@arm.com        }
118811051Sandreas.hansson@arm.com    }
118911051Sandreas.hansson@arm.com
119011051Sandreas.hansson@arm.com    // Note that we don't invoke the prefetcher at all in atomic mode.
119111051Sandreas.hansson@arm.com    // It's not clear how to do it properly, particularly for
119211051Sandreas.hansson@arm.com    // prefetchers that aggressively generate prefetch candidates and
119311051Sandreas.hansson@arm.com    // rely on bandwidth contention to throttle them; these will tend
119411051Sandreas.hansson@arm.com    // to pollute the cache in atomic mode since there is no bandwidth
119511051Sandreas.hansson@arm.com    // contention.  If we ever do want to enable prefetching in atomic
119611051Sandreas.hansson@arm.com    // mode, though, this is the place to do it... see timingAccess()
119711051Sandreas.hansson@arm.com    // for an example (though we'd want to issue the prefetch(es)
119811051Sandreas.hansson@arm.com    // immediately rather than calling requestMemSideBus() as we do
119911051Sandreas.hansson@arm.com    // there).
120011051Sandreas.hansson@arm.com
120111197Sandreas.hansson@arm.com    // do any writebacks resulting from the response handling
120211130Sali.jafri@arm.com    doWritebacksAtomic(writebacks);
120311051Sandreas.hansson@arm.com
120411197Sandreas.hansson@arm.com    // if we used temp block, check to see if its valid and if so
120511197Sandreas.hansson@arm.com    // clear it out, but only do so after the call to recvAtomic is
120611197Sandreas.hansson@arm.com    // finished so that any downstream observers (such as a snoop
120711197Sandreas.hansson@arm.com    // filter), first see the fill, and only then see the eviction
120811197Sandreas.hansson@arm.com    if (blk == tempBlock && tempBlock->isValid()) {
120911197Sandreas.hansson@arm.com        // the atomic CPU calls recvAtomic for fetch and load/store
121011197Sandreas.hansson@arm.com        // sequentuially, and we may already have a tempBlock
121111197Sandreas.hansson@arm.com        // writeback from the fetch that we have not yet sent
121211197Sandreas.hansson@arm.com        if (tempBlockWriteback) {
121311197Sandreas.hansson@arm.com            // if that is the case, write the prevoius one back, and
121411197Sandreas.hansson@arm.com            // do not schedule any new event
121511197Sandreas.hansson@arm.com            writebackTempBlockAtomic();
121611197Sandreas.hansson@arm.com        } else {
121711197Sandreas.hansson@arm.com            // the writeback/clean eviction happens after the call to
121811197Sandreas.hansson@arm.com            // recvAtomic has finished (but before any successive
121911197Sandreas.hansson@arm.com            // calls), so that the response handling from the fill is
122011197Sandreas.hansson@arm.com            // allowed to happen first
122111197Sandreas.hansson@arm.com            schedule(writebackTempBlockAtomicEvent, curTick());
122211197Sandreas.hansson@arm.com        }
122311197Sandreas.hansson@arm.com
122411199Sandreas.hansson@arm.com        tempBlockWriteback = (blk->isDirty() || writebackClean) ?
122511199Sandreas.hansson@arm.com            writebackBlk(blk) : cleanEvictBlk(blk);
122611867Snikos.nikoleris@arm.com        invalidateBlock(blk);
122711197Sandreas.hansson@arm.com    }
122811197Sandreas.hansson@arm.com
122911051Sandreas.hansson@arm.com    if (pkt->needsResponse()) {
123011051Sandreas.hansson@arm.com        pkt->makeAtomicResponse();
123111051Sandreas.hansson@arm.com    }
123211051Sandreas.hansson@arm.com
123311051Sandreas.hansson@arm.com    return lat * clockPeriod();
123411051Sandreas.hansson@arm.com}
123511051Sandreas.hansson@arm.com
123611051Sandreas.hansson@arm.com
123711051Sandreas.hansson@arm.comvoid
123811051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide)
123911051Sandreas.hansson@arm.com{
124011051Sandreas.hansson@arm.com    if (system->bypassCaches()) {
124111051Sandreas.hansson@arm.com        // Packets from the memory side are snoop request and
124211051Sandreas.hansson@arm.com        // shouldn't happen in bypass mode.
124311051Sandreas.hansson@arm.com        assert(fromCpuSide);
124411051Sandreas.hansson@arm.com
124511051Sandreas.hansson@arm.com        // The cache should be flushed if we are in cache bypass mode,
124611051Sandreas.hansson@arm.com        // so we don't need to check if we need to update anything.
124711051Sandreas.hansson@arm.com        memSidePort->sendFunctional(pkt);
124811051Sandreas.hansson@arm.com        return;
124911051Sandreas.hansson@arm.com    }
125011051Sandreas.hansson@arm.com
125111892Snikos.nikoleris@arm.com    Addr blk_addr = pkt->getBlockAddr(blkSize);
125211051Sandreas.hansson@arm.com    bool is_secure = pkt->isSecure();
125311051Sandreas.hansson@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
125411051Sandreas.hansson@arm.com    MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
125511051Sandreas.hansson@arm.com
125611051Sandreas.hansson@arm.com    pkt->pushLabel(name());
125711051Sandreas.hansson@arm.com
125811051Sandreas.hansson@arm.com    CacheBlkPrintWrapper cbpw(blk);
125911051Sandreas.hansson@arm.com
126011051Sandreas.hansson@arm.com    // Note that just because an L2/L3 has valid data doesn't mean an
126111051Sandreas.hansson@arm.com    // L1 doesn't have a more up-to-date modified copy that still
126211051Sandreas.hansson@arm.com    // needs to be found.  As a result we always update the request if
126311051Sandreas.hansson@arm.com    // we have it, but only declare it satisfied if we are the owner.
126411051Sandreas.hansson@arm.com
126511051Sandreas.hansson@arm.com    // see if we have data at all (owned or otherwise)
126611051Sandreas.hansson@arm.com    bool have_data = blk && blk->isValid()
126711051Sandreas.hansson@arm.com        && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize,
126811051Sandreas.hansson@arm.com                                blk->data);
126911051Sandreas.hansson@arm.com
127011284Sandreas.hansson@arm.com    // data we have is dirty if marked as such or if we have an
127111284Sandreas.hansson@arm.com    // in-service MSHR that is pending a modified line
127211051Sandreas.hansson@arm.com    bool have_dirty =
127311051Sandreas.hansson@arm.com        have_data && (blk->isDirty() ||
127411284Sandreas.hansson@arm.com                      (mshr && mshr->inService && mshr->isPendingModified()));
127511051Sandreas.hansson@arm.com
127611051Sandreas.hansson@arm.com    bool done = have_dirty
127711051Sandreas.hansson@arm.com        || cpuSidePort->checkFunctional(pkt)
127811051Sandreas.hansson@arm.com        || mshrQueue.checkFunctional(pkt, blk_addr)
127911051Sandreas.hansson@arm.com        || writeBuffer.checkFunctional(pkt, blk_addr)
128011051Sandreas.hansson@arm.com        || memSidePort->checkFunctional(pkt);
128111051Sandreas.hansson@arm.com
128211744Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__,  pkt->print(),
128311051Sandreas.hansson@arm.com            (blk && blk->isValid()) ? "valid " : "",
128411051Sandreas.hansson@arm.com            have_data ? "data " : "", done ? "done " : "");
128511051Sandreas.hansson@arm.com
128611051Sandreas.hansson@arm.com    // We're leaving the cache, so pop cache->name() label
128711051Sandreas.hansson@arm.com    pkt->popLabel();
128811051Sandreas.hansson@arm.com
128911051Sandreas.hansson@arm.com    if (done) {
129011051Sandreas.hansson@arm.com        pkt->makeResponse();
129111051Sandreas.hansson@arm.com    } else {
129211051Sandreas.hansson@arm.com        // if it came as a request from the CPU side then make sure it
129311051Sandreas.hansson@arm.com        // continues towards the memory side
129411051Sandreas.hansson@arm.com        if (fromCpuSide) {
129511051Sandreas.hansson@arm.com            memSidePort->sendFunctional(pkt);
129611485Snikos.nikoleris@arm.com        } else if (cpuSidePort->isSnooping()) {
129711051Sandreas.hansson@arm.com            // if it came from the memory side, it must be a snoop request
129811051Sandreas.hansson@arm.com            // and we should only forward it if we are forwarding snoops
129911051Sandreas.hansson@arm.com            cpuSidePort->sendFunctionalSnoop(pkt);
130011051Sandreas.hansson@arm.com        }
130111051Sandreas.hansson@arm.com    }
130211051Sandreas.hansson@arm.com}
130311051Sandreas.hansson@arm.com
130411051Sandreas.hansson@arm.com
130511051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
130611051Sandreas.hansson@arm.com//
130711051Sandreas.hansson@arm.com// Response handling: responses from the memory side
130811051Sandreas.hansson@arm.com//
130911051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
131011051Sandreas.hansson@arm.com
131111051Sandreas.hansson@arm.com
131211051Sandreas.hansson@arm.comvoid
131311375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt)
131411375Sandreas.hansson@arm.com{
131511375Sandreas.hansson@arm.com    Tick completion_time = clockEdge(responseLatency) +
131611375Sandreas.hansson@arm.com        pkt->headerDelay + pkt->payloadDelay;
131711375Sandreas.hansson@arm.com
131811453Sandreas.hansson@arm.com    // Reset the bus additional time as it is now accounted for
131911453Sandreas.hansson@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
132011375Sandreas.hansson@arm.com
132111453Sandreas.hansson@arm.com    cpuSidePort->schedTimingResp(pkt, completion_time, true);
132211375Sandreas.hansson@arm.com}
132311375Sandreas.hansson@arm.com
132411375Sandreas.hansson@arm.comvoid
132511051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt)
132611051Sandreas.hansson@arm.com{
132711051Sandreas.hansson@arm.com    assert(pkt->isResponse());
132811051Sandreas.hansson@arm.com
132911051Sandreas.hansson@arm.com    // all header delay should be paid for by the crossbar, unless
133011051Sandreas.hansson@arm.com    // this is a prefetch response from above
133111051Sandreas.hansson@arm.com    panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp,
133211051Sandreas.hansson@arm.com             "%s saw a non-zero packet delay\n", name());
133311051Sandreas.hansson@arm.com
133411051Sandreas.hansson@arm.com    bool is_error = pkt->isError();
133511051Sandreas.hansson@arm.com
133611051Sandreas.hansson@arm.com    if (is_error) {
133711744Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s: Cache received %s with error\n", __func__,
133811744Snikos.nikoleris@arm.com                pkt->print());
133911051Sandreas.hansson@arm.com    }
134011051Sandreas.hansson@arm.com
134111744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: Handling response %s\n", __func__,
134211744Snikos.nikoleris@arm.com            pkt->print());
134311051Sandreas.hansson@arm.com
134411375Sandreas.hansson@arm.com    // if this is a write, we should be looking at an uncacheable
134511375Sandreas.hansson@arm.com    // write
134611375Sandreas.hansson@arm.com    if (pkt->isWrite()) {
134711375Sandreas.hansson@arm.com        assert(pkt->req->isUncacheable());
134811375Sandreas.hansson@arm.com        handleUncacheableWriteResp(pkt);
134911375Sandreas.hansson@arm.com        return;
135011375Sandreas.hansson@arm.com    }
135111375Sandreas.hansson@arm.com
135211375Sandreas.hansson@arm.com    // we have dealt with any (uncacheable) writes above, from here on
135311375Sandreas.hansson@arm.com    // we know we are dealing with an MSHR due to a miss or a prefetch
135411453Sandreas.hansson@arm.com    MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState());
135511375Sandreas.hansson@arm.com    assert(mshr);
135611051Sandreas.hansson@arm.com
135711051Sandreas.hansson@arm.com    if (mshr == noTargetMSHR) {
135811051Sandreas.hansson@arm.com        // we always clear at least one target
135911051Sandreas.hansson@arm.com        clearBlocked(Blocked_NoTargets);
136011484Snikos.nikoleris@arm.com        noTargetMSHR = nullptr;
136111051Sandreas.hansson@arm.com    }
136211051Sandreas.hansson@arm.com
136311051Sandreas.hansson@arm.com    // Initial target is used just for stats
136411051Sandreas.hansson@arm.com    MSHR::Target *initial_tgt = mshr->getTarget();
136511051Sandreas.hansson@arm.com    int stats_cmd_idx = initial_tgt->pkt->cmdToIndex();
136611051Sandreas.hansson@arm.com    Tick miss_latency = curTick() - initial_tgt->recvTime;
136711051Sandreas.hansson@arm.com
136811051Sandreas.hansson@arm.com    if (pkt->req->isUncacheable()) {
136911051Sandreas.hansson@arm.com        assert(pkt->req->masterId() < system->maxMasters());
137011051Sandreas.hansson@arm.com        mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] +=
137111051Sandreas.hansson@arm.com            miss_latency;
137211051Sandreas.hansson@arm.com    } else {
137311051Sandreas.hansson@arm.com        assert(pkt->req->masterId() < system->maxMasters());
137411051Sandreas.hansson@arm.com        mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] +=
137511051Sandreas.hansson@arm.com            miss_latency;
137611051Sandreas.hansson@arm.com    }
137711051Sandreas.hansson@arm.com
137811375Sandreas.hansson@arm.com    bool wasFull = mshrQueue.isFull();
137911375Sandreas.hansson@arm.com
138011375Sandreas.hansson@arm.com    PacketList writebacks;
138111375Sandreas.hansson@arm.com
138211375Sandreas.hansson@arm.com    Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
138311375Sandreas.hansson@arm.com
138412348Snikos.nikoleris@arm.com    bool is_fill = !mshr->isForward &&
138512348Snikos.nikoleris@arm.com        (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp);
138612348Snikos.nikoleris@arm.com
138712348Snikos.nikoleris@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
138812348Snikos.nikoleris@arm.com    const bool valid_blk = blk && blk->isValid();
138912348Snikos.nikoleris@arm.com    // If the response indicates that there are no sharers and we
139012348Snikos.nikoleris@arm.com    // either had the block already or the response is filling we can
139112348Snikos.nikoleris@arm.com    // promote our copy to writable
139212349Snikos.nikoleris@arm.com    if (!pkt->hasSharers() &&
139312349Snikos.nikoleris@arm.com        (is_fill || (valid_blk && !pkt->req->isCacheInvalidate()))) {
139411284Sandreas.hansson@arm.com        mshr->promoteWritable();
139511177Sandreas.hansson@arm.com    }
139611177Sandreas.hansson@arm.com
139711051Sandreas.hansson@arm.com    if (is_fill && !is_error) {
139811051Sandreas.hansson@arm.com        DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n",
139911051Sandreas.hansson@arm.com                pkt->getAddr());
140011051Sandreas.hansson@arm.com
140111741Snikos.nikoleris@arm.com        blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill());
140211484Snikos.nikoleris@arm.com        assert(blk != nullptr);
140311051Sandreas.hansson@arm.com    }
140411051Sandreas.hansson@arm.com
140511051Sandreas.hansson@arm.com    // allow invalidation responses originating from write-line
140611051Sandreas.hansson@arm.com    // requests to be discarded
140711136Sandreas.hansson@arm.com    bool is_invalidate = pkt->isInvalidate();
140811051Sandreas.hansson@arm.com
140912349Snikos.nikoleris@arm.com    // The block was marked as not readable while there was a pending
141012349Snikos.nikoleris@arm.com    // cache maintenance operation, restore its flag.
141112349Snikos.nikoleris@arm.com    if (pkt->isClean() && !is_invalidate && valid_blk) {
141212349Snikos.nikoleris@arm.com        blk->status |= BlkReadable;
141312349Snikos.nikoleris@arm.com    }
141412349Snikos.nikoleris@arm.com
141511051Sandreas.hansson@arm.com    // First offset for critical word first calculations
141611051Sandreas.hansson@arm.com    int initial_offset = initial_tgt->pkt->getOffset(blkSize);
141711051Sandreas.hansson@arm.com
141811742Snikos.nikoleris@arm.com    MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
141911742Snikos.nikoleris@arm.com    for (auto &target: targets) {
142011742Snikos.nikoleris@arm.com        Packet *tgt_pkt = target.pkt;
142111742Snikos.nikoleris@arm.com        switch (target.source) {
142211051Sandreas.hansson@arm.com          case MSHR::Target::FromCPU:
142311051Sandreas.hansson@arm.com            Tick completion_time;
142411051Sandreas.hansson@arm.com            // Here we charge on completion_time the delay of the xbar if the
142511051Sandreas.hansson@arm.com            // packet comes from it, charged on headerDelay.
142611051Sandreas.hansson@arm.com            completion_time = pkt->headerDelay;
142711051Sandreas.hansson@arm.com
142811051Sandreas.hansson@arm.com            // Software prefetch handling for cache closest to core
142911051Sandreas.hansson@arm.com            if (tgt_pkt->cmd.isSWPrefetch()) {
143011483Snikos.nikoleris@arm.com                // a software prefetch would have already been ack'd
143111483Snikos.nikoleris@arm.com                // immediately with dummy data so the core would be able to
143211483Snikos.nikoleris@arm.com                // retire it. This request completes right here, so we
143311483Snikos.nikoleris@arm.com                // deallocate it.
143411051Sandreas.hansson@arm.com                delete tgt_pkt->req;
143511051Sandreas.hansson@arm.com                delete tgt_pkt;
143611051Sandreas.hansson@arm.com                break; // skip response
143711051Sandreas.hansson@arm.com            }
143811051Sandreas.hansson@arm.com
143911051Sandreas.hansson@arm.com            // unlike the other packet flows, where data is found in other
144011051Sandreas.hansson@arm.com            // caches or memory and brought back, write-line requests always
144111051Sandreas.hansson@arm.com            // have the data right away, so the above check for "is fill?"
144211051Sandreas.hansson@arm.com            // cannot actually be determined until examining the stored MSHR
144311051Sandreas.hansson@arm.com            // state. We "catch up" with that logic here, which is duplicated
144411051Sandreas.hansson@arm.com            // from above.
144511051Sandreas.hansson@arm.com            if (tgt_pkt->cmd == MemCmd::WriteLineReq) {
144611051Sandreas.hansson@arm.com                assert(!is_error);
144711284Sandreas.hansson@arm.com                // we got the block in a writable state, so promote
144811284Sandreas.hansson@arm.com                // any deferred targets if possible
144911284Sandreas.hansson@arm.com                mshr->promoteWritable();
145011051Sandreas.hansson@arm.com                // NB: we use the original packet here and not the response!
145111741Snikos.nikoleris@arm.com                blk = handleFill(tgt_pkt, blk, writebacks,
145211742Snikos.nikoleris@arm.com                                 targets.allocOnFill);
145311484Snikos.nikoleris@arm.com                assert(blk != nullptr);
145411051Sandreas.hansson@arm.com
145511051Sandreas.hansson@arm.com                // treat as a fill, and discard the invalidation
145611051Sandreas.hansson@arm.com                // response
145711051Sandreas.hansson@arm.com                is_fill = true;
145811136Sandreas.hansson@arm.com                is_invalidate = false;
145911051Sandreas.hansson@arm.com            }
146011051Sandreas.hansson@arm.com
146111051Sandreas.hansson@arm.com            if (is_fill) {
146211601Sandreas.hansson@arm.com                satisfyRequest(tgt_pkt, blk, true, mshr->hasPostDowngrade());
146311051Sandreas.hansson@arm.com
146411051Sandreas.hansson@arm.com                // How many bytes past the first request is this one
146511051Sandreas.hansson@arm.com                int transfer_offset =
146611051Sandreas.hansson@arm.com                    tgt_pkt->getOffset(blkSize) - initial_offset;
146711051Sandreas.hansson@arm.com                if (transfer_offset < 0) {
146811051Sandreas.hansson@arm.com                    transfer_offset += blkSize;
146911051Sandreas.hansson@arm.com                }
147011051Sandreas.hansson@arm.com
147111051Sandreas.hansson@arm.com                // If not critical word (offset) return payloadDelay.
147211051Sandreas.hansson@arm.com                // responseLatency is the latency of the return path
147311051Sandreas.hansson@arm.com                // from lower level caches/memory to an upper level cache or
147411051Sandreas.hansson@arm.com                // the core.
147511051Sandreas.hansson@arm.com                completion_time += clockEdge(responseLatency) +
147611051Sandreas.hansson@arm.com                    (transfer_offset ? pkt->payloadDelay : 0);
147711051Sandreas.hansson@arm.com
147811051Sandreas.hansson@arm.com                assert(!tgt_pkt->req->isUncacheable());
147911051Sandreas.hansson@arm.com
148011051Sandreas.hansson@arm.com                assert(tgt_pkt->req->masterId() < system->maxMasters());
148111051Sandreas.hansson@arm.com                missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] +=
148211742Snikos.nikoleris@arm.com                    completion_time - target.recvTime;
148311051Sandreas.hansson@arm.com            } else if (pkt->cmd == MemCmd::UpgradeFailResp) {
148411051Sandreas.hansson@arm.com                // failed StoreCond upgrade
148511051Sandreas.hansson@arm.com                assert(tgt_pkt->cmd == MemCmd::StoreCondReq ||
148611051Sandreas.hansson@arm.com                       tgt_pkt->cmd == MemCmd::StoreCondFailReq ||
148711051Sandreas.hansson@arm.com                       tgt_pkt->cmd == MemCmd::SCUpgradeFailReq);
148811051Sandreas.hansson@arm.com                // responseLatency is the latency of the return path
148911051Sandreas.hansson@arm.com                // from lower level caches/memory to an upper level cache or
149011051Sandreas.hansson@arm.com                // the core.
149111051Sandreas.hansson@arm.com                completion_time += clockEdge(responseLatency) +
149211051Sandreas.hansson@arm.com                    pkt->payloadDelay;
149311051Sandreas.hansson@arm.com                tgt_pkt->req->setExtraData(0);
149411051Sandreas.hansson@arm.com            } else {
149511750Snikos.nikoleris@arm.com                // We are about to send a response to a cache above
149611750Snikos.nikoleris@arm.com                // that asked for an invalidation; we need to
149711750Snikos.nikoleris@arm.com                // invalidate our copy immediately as the most
149811750Snikos.nikoleris@arm.com                // up-to-date copy of the block will now be in the
149911750Snikos.nikoleris@arm.com                // cache above. It will also prevent this cache from
150011750Snikos.nikoleris@arm.com                // responding (if the block was previously dirty) to
150111750Snikos.nikoleris@arm.com                // snoops as they should snoop the caches above where
150211750Snikos.nikoleris@arm.com                // they will get the response from.
150311750Snikos.nikoleris@arm.com                if (is_invalidate && blk && blk->isValid()) {
150411750Snikos.nikoleris@arm.com                    invalidateBlock(blk);
150511750Snikos.nikoleris@arm.com                }
150611051Sandreas.hansson@arm.com                // not a cache fill, just forwarding response
150711051Sandreas.hansson@arm.com                // responseLatency is the latency of the return path
150811051Sandreas.hansson@arm.com                // from lower level cahces/memory to the core.
150911051Sandreas.hansson@arm.com                completion_time += clockEdge(responseLatency) +
151011051Sandreas.hansson@arm.com                    pkt->payloadDelay;
151111051Sandreas.hansson@arm.com                if (pkt->isRead() && !is_error) {
151211051Sandreas.hansson@arm.com                    // sanity check
151311051Sandreas.hansson@arm.com                    assert(pkt->getAddr() == tgt_pkt->getAddr());
151411051Sandreas.hansson@arm.com                    assert(pkt->getSize() >= tgt_pkt->getSize());
151511051Sandreas.hansson@arm.com
151611051Sandreas.hansson@arm.com                    tgt_pkt->setData(pkt->getConstPtr<uint8_t>());
151711051Sandreas.hansson@arm.com                }
151811051Sandreas.hansson@arm.com            }
151911051Sandreas.hansson@arm.com            tgt_pkt->makeTimingResponse();
152011051Sandreas.hansson@arm.com            // if this packet is an error copy that to the new packet
152111051Sandreas.hansson@arm.com            if (is_error)
152211051Sandreas.hansson@arm.com                tgt_pkt->copyError(pkt);
152311051Sandreas.hansson@arm.com            if (tgt_pkt->cmd == MemCmd::ReadResp &&
152411136Sandreas.hansson@arm.com                (is_invalidate || mshr->hasPostInvalidate())) {
152511051Sandreas.hansson@arm.com                // If intermediate cache got ReadRespWithInvalidate,
152611051Sandreas.hansson@arm.com                // propagate that.  Response should not have
152711051Sandreas.hansson@arm.com                // isInvalidate() set otherwise.
152811051Sandreas.hansson@arm.com                tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate;
152911744Snikos.nikoleris@arm.com                DPRINTF(Cache, "%s: updated cmd to %s\n", __func__,
153011744Snikos.nikoleris@arm.com                        tgt_pkt->print());
153111051Sandreas.hansson@arm.com            }
153211051Sandreas.hansson@arm.com            // Reset the bus additional time as it is now accounted for
153311051Sandreas.hansson@arm.com            tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0;
153411194Sali.jafri@arm.com            cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true);
153511051Sandreas.hansson@arm.com            break;
153611051Sandreas.hansson@arm.com
153711051Sandreas.hansson@arm.com          case MSHR::Target::FromPrefetcher:
153811051Sandreas.hansson@arm.com            assert(tgt_pkt->cmd == MemCmd::HardPFReq);
153911051Sandreas.hansson@arm.com            if (blk)
154011051Sandreas.hansson@arm.com                blk->status |= BlkHWPrefetched;
154111051Sandreas.hansson@arm.com            delete tgt_pkt->req;
154211051Sandreas.hansson@arm.com            delete tgt_pkt;
154311051Sandreas.hansson@arm.com            break;
154411051Sandreas.hansson@arm.com
154511051Sandreas.hansson@arm.com          case MSHR::Target::FromSnoop:
154611051Sandreas.hansson@arm.com            // I don't believe that a snoop can be in an error state
154711051Sandreas.hansson@arm.com            assert(!is_error);
154811051Sandreas.hansson@arm.com            // response to snoop request
154911051Sandreas.hansson@arm.com            DPRINTF(Cache, "processing deferred snoop...\n");
155011749Snikos.nikoleris@arm.com            // If the response is invalidating, a snooping target can
155111749Snikos.nikoleris@arm.com            // be satisfied if it is also invalidating. If the reponse is, not
155212349Snikos.nikoleris@arm.com            // only invalidating, but more specifically an InvalidateResp and
155312349Snikos.nikoleris@arm.com            // the MSHR was created due to an InvalidateReq then a cache above
155412349Snikos.nikoleris@arm.com            // is waiting to satisfy a WriteLineReq. In this case even an
155511749Snikos.nikoleris@arm.com            // non-invalidating snoop is added as a target here since this is
155611749Snikos.nikoleris@arm.com            // the ordering point. When the InvalidateResp reaches this cache,
155711749Snikos.nikoleris@arm.com            // the snooping target will snoop further the cache above with the
155811749Snikos.nikoleris@arm.com            // WriteLineReq.
155912349Snikos.nikoleris@arm.com            assert(!is_invalidate || pkt->cmd == MemCmd::InvalidateResp ||
156012349Snikos.nikoleris@arm.com                   pkt->req->isCacheMaintenance() ||
156112349Snikos.nikoleris@arm.com                   mshr->hasPostInvalidate());
156211051Sandreas.hansson@arm.com            handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate());
156311051Sandreas.hansson@arm.com            break;
156411051Sandreas.hansson@arm.com
156511051Sandreas.hansson@arm.com          default:
156611742Snikos.nikoleris@arm.com            panic("Illegal target->source enum %d\n", target.source);
156711051Sandreas.hansson@arm.com        }
156811051Sandreas.hansson@arm.com    }
156911051Sandreas.hansson@arm.com
157012715Snikos.nikoleris@arm.com    maintainClusivity(targets.hasFromCache, blk);
157111601Sandreas.hansson@arm.com
157211051Sandreas.hansson@arm.com    if (blk && blk->isValid()) {
157311051Sandreas.hansson@arm.com        // an invalidate response stemming from a write line request
157411051Sandreas.hansson@arm.com        // should not invalidate the block, so check if the
157511051Sandreas.hansson@arm.com        // invalidation should be discarded
157611136Sandreas.hansson@arm.com        if (is_invalidate || mshr->hasPostInvalidate()) {
157711197Sandreas.hansson@arm.com            invalidateBlock(blk);
157811051Sandreas.hansson@arm.com        } else if (mshr->hasPostDowngrade()) {
157911051Sandreas.hansson@arm.com            blk->status &= ~BlkWritable;
158011051Sandreas.hansson@arm.com        }
158111051Sandreas.hansson@arm.com    }
158211051Sandreas.hansson@arm.com
158311051Sandreas.hansson@arm.com    if (mshr->promoteDeferredTargets()) {
158411051Sandreas.hansson@arm.com        // avoid later read getting stale data while write miss is
158511051Sandreas.hansson@arm.com        // outstanding.. see comment in timingAccess()
158611051Sandreas.hansson@arm.com        if (blk) {
158711051Sandreas.hansson@arm.com            blk->status &= ~BlkReadable;
158811051Sandreas.hansson@arm.com        }
158911375Sandreas.hansson@arm.com        mshrQueue.markPending(mshr);
159011051Sandreas.hansson@arm.com        schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
159111051Sandreas.hansson@arm.com    } else {
159211375Sandreas.hansson@arm.com        mshrQueue.deallocate(mshr);
159311375Sandreas.hansson@arm.com        if (wasFull && !mshrQueue.isFull()) {
159411375Sandreas.hansson@arm.com            clearBlocked(Blocked_NoMSHRs);
159511051Sandreas.hansson@arm.com        }
159611051Sandreas.hansson@arm.com
159711051Sandreas.hansson@arm.com        // Request the bus for a prefetch if this deallocation freed enough
159811051Sandreas.hansson@arm.com        // MSHRs for a prefetch to take place
159911375Sandreas.hansson@arm.com        if (prefetcher && mshrQueue.canPrefetch()) {
160011051Sandreas.hansson@arm.com            Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(),
160111051Sandreas.hansson@arm.com                                         clockEdge());
160211051Sandreas.hansson@arm.com            if (next_pf_time != MaxTick)
160311051Sandreas.hansson@arm.com                schedMemSideSendEvent(next_pf_time);
160411051Sandreas.hansson@arm.com        }
160511051Sandreas.hansson@arm.com    }
160611051Sandreas.hansson@arm.com    // reset the xbar additional timinig  as it is now accounted for
160711051Sandreas.hansson@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
160811051Sandreas.hansson@arm.com
160912700Snikos.nikoleris@arm.com    // if we used temp block, check to see if its valid and then clear it out
161012700Snikos.nikoleris@arm.com    if (blk == tempBlock && tempBlock->isValid()) {
161112700Snikos.nikoleris@arm.com        PacketPtr wb_pkt = tempBlock->isDirty() || writebackClean ?
161212700Snikos.nikoleris@arm.com            writebackBlk(blk) : cleanEvictBlk(blk);
161312700Snikos.nikoleris@arm.com        writebacks.push_back(wb_pkt);
161412700Snikos.nikoleris@arm.com        invalidateBlock(tempBlock);
161512700Snikos.nikoleris@arm.com    }
161612700Snikos.nikoleris@arm.com
161711051Sandreas.hansson@arm.com    // copy writebacks to write buffer
161811051Sandreas.hansson@arm.com    doWritebacks(writebacks, forward_time);
161911051Sandreas.hansson@arm.com
162011744Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print());
162111051Sandreas.hansson@arm.com    delete pkt;
162211051Sandreas.hansson@arm.com}
162311051Sandreas.hansson@arm.com
162411051Sandreas.hansson@arm.comPacketPtr
162511051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk)
162611051Sandreas.hansson@arm.com{
162711199Sandreas.hansson@arm.com    chatty_assert(!isReadOnly || writebackClean,
162811199Sandreas.hansson@arm.com                  "Writeback from read-only cache");
162911199Sandreas.hansson@arm.com    assert(blk && blk->isValid() && (blk->isDirty() || writebackClean));
163011051Sandreas.hansson@arm.com
163111051Sandreas.hansson@arm.com    writebacks[Request::wbMasterId]++;
163211051Sandreas.hansson@arm.com
163312574Sodanrc@yahoo.com.br    Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0,
163412574Sodanrc@yahoo.com.br                               Request::wbMasterId);
163511051Sandreas.hansson@arm.com    if (blk->isSecure())
163611199Sandreas.hansson@arm.com        req->setFlags(Request::SECURE);
163711051Sandreas.hansson@arm.com
163811199Sandreas.hansson@arm.com    req->taskId(blk->task_id);
163911051Sandreas.hansson@arm.com
164011199Sandreas.hansson@arm.com    PacketPtr pkt =
164111199Sandreas.hansson@arm.com        new Packet(req, blk->isDirty() ?
164211199Sandreas.hansson@arm.com                   MemCmd::WritebackDirty : MemCmd::WritebackClean);
164311199Sandreas.hansson@arm.com
164411744Snikos.nikoleris@arm.com    DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n",
164511744Snikos.nikoleris@arm.com            pkt->print(), blk->isWritable(), blk->isDirty());
164611199Sandreas.hansson@arm.com
164711051Sandreas.hansson@arm.com    if (blk->isWritable()) {
164811051Sandreas.hansson@arm.com        // not asserting shared means we pass the block in modified
164911051Sandreas.hansson@arm.com        // state, mark our own block non-writeable
165011051Sandreas.hansson@arm.com        blk->status &= ~BlkWritable;
165111051Sandreas.hansson@arm.com    } else {
165211284Sandreas.hansson@arm.com        // we are in the Owned state, tell the receiver
165311284Sandreas.hansson@arm.com        pkt->setHasSharers();
165411051Sandreas.hansson@arm.com    }
165511051Sandreas.hansson@arm.com
165611199Sandreas.hansson@arm.com    // make sure the block is not marked dirty
165711199Sandreas.hansson@arm.com    blk->status &= ~BlkDirty;
165811051Sandreas.hansson@arm.com
165911199Sandreas.hansson@arm.com    pkt->allocate();
166012633Sodanrc@yahoo.com.br    pkt->setDataFromBlock(blk->data, blkSize);
166111199Sandreas.hansson@arm.com
166211199Sandreas.hansson@arm.com    return pkt;
166311051Sandreas.hansson@arm.com}
166411051Sandreas.hansson@arm.com
166511051Sandreas.hansson@arm.comPacketPtr
166612351Snikos.nikoleris@arm.comCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id)
166712345Snikos.nikoleris@arm.com{
166812574Sodanrc@yahoo.com.br    Request *req = new Request(tags->regenerateBlkAddr(blk), blkSize, 0,
166912574Sodanrc@yahoo.com.br                               Request::wbMasterId);
167012345Snikos.nikoleris@arm.com    if (blk->isSecure()) {
167112345Snikos.nikoleris@arm.com        req->setFlags(Request::SECURE);
167212345Snikos.nikoleris@arm.com    }
167312345Snikos.nikoleris@arm.com    req->taskId(blk->task_id);
167412500Snikos.nikoleris@arm.com
167512351Snikos.nikoleris@arm.com    PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id);
167612500Snikos.nikoleris@arm.com
167712346Snikos.nikoleris@arm.com    if (dest) {
167812346Snikos.nikoleris@arm.com        req->setFlags(dest);
167912346Snikos.nikoleris@arm.com        pkt->setWriteThrough();
168012346Snikos.nikoleris@arm.com    }
168112500Snikos.nikoleris@arm.com
168212500Snikos.nikoleris@arm.com    DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(),
168312500Snikos.nikoleris@arm.com            blk->isWritable(), blk->isDirty());
168412500Snikos.nikoleris@arm.com
168512500Snikos.nikoleris@arm.com    if (blk->isWritable()) {
168612500Snikos.nikoleris@arm.com        // not asserting shared means we pass the block in modified
168712500Snikos.nikoleris@arm.com        // state, mark our own block non-writeable
168812500Snikos.nikoleris@arm.com        blk->status &= ~BlkWritable;
168912500Snikos.nikoleris@arm.com    } else {
169012500Snikos.nikoleris@arm.com        // we are in the Owned state, tell the receiver
169112500Snikos.nikoleris@arm.com        pkt->setHasSharers();
169212500Snikos.nikoleris@arm.com    }
169312500Snikos.nikoleris@arm.com
169412500Snikos.nikoleris@arm.com    // make sure the block is not marked dirty
169512500Snikos.nikoleris@arm.com    blk->status &= ~BlkDirty;
169612500Snikos.nikoleris@arm.com
169712500Snikos.nikoleris@arm.com    pkt->allocate();
169812633Sodanrc@yahoo.com.br    pkt->setDataFromBlock(blk->data, blkSize);
169912500Snikos.nikoleris@arm.com
170012345Snikos.nikoleris@arm.com    return pkt;
170112345Snikos.nikoleris@arm.com}
170212345Snikos.nikoleris@arm.com
170312345Snikos.nikoleris@arm.com
170412345Snikos.nikoleris@arm.comPacketPtr
170511051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk)
170611051Sandreas.hansson@arm.com{
170711199Sandreas.hansson@arm.com    assert(!writebackClean);
170811051Sandreas.hansson@arm.com    assert(blk && blk->isValid() && !blk->isDirty());
170911051Sandreas.hansson@arm.com    // Creating a zero sized write, a message to the snoop filter
171011051Sandreas.hansson@arm.com    Request *req =
171112574Sodanrc@yahoo.com.br        new Request(tags->regenerateBlkAddr(blk), blkSize, 0,
171211051Sandreas.hansson@arm.com                    Request::wbMasterId);
171311051Sandreas.hansson@arm.com    if (blk->isSecure())
171411051Sandreas.hansson@arm.com        req->setFlags(Request::SECURE);
171511051Sandreas.hansson@arm.com
171611051Sandreas.hansson@arm.com    req->taskId(blk->task_id);
171711051Sandreas.hansson@arm.com
171811051Sandreas.hansson@arm.com    PacketPtr pkt = new Packet(req, MemCmd::CleanEvict);
171911051Sandreas.hansson@arm.com    pkt->allocate();
172011744Snikos.nikoleris@arm.com    DPRINTF(Cache, "Create CleanEvict %s\n", pkt->print());
172111051Sandreas.hansson@arm.com
172211051Sandreas.hansson@arm.com    return pkt;
172311051Sandreas.hansson@arm.com}
172411051Sandreas.hansson@arm.com
172511051Sandreas.hansson@arm.comvoid
172611051Sandreas.hansson@arm.comCache::memWriteback()
172711051Sandreas.hansson@arm.com{
172811051Sandreas.hansson@arm.com    CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor);
172911051Sandreas.hansson@arm.com    tags->forEachBlk(visitor);
173011051Sandreas.hansson@arm.com}
173111051Sandreas.hansson@arm.com
173211051Sandreas.hansson@arm.comvoid
173311051Sandreas.hansson@arm.comCache::memInvalidate()
173411051Sandreas.hansson@arm.com{
173511051Sandreas.hansson@arm.com    CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor);
173611051Sandreas.hansson@arm.com    tags->forEachBlk(visitor);
173711051Sandreas.hansson@arm.com}
173811051Sandreas.hansson@arm.com
173911051Sandreas.hansson@arm.combool
174011051Sandreas.hansson@arm.comCache::isDirty() const
174111051Sandreas.hansson@arm.com{
174211051Sandreas.hansson@arm.com    CacheBlkIsDirtyVisitor visitor;
174311051Sandreas.hansson@arm.com    tags->forEachBlk(visitor);
174411051Sandreas.hansson@arm.com
174511051Sandreas.hansson@arm.com    return visitor.isDirty();
174611051Sandreas.hansson@arm.com}
174711051Sandreas.hansson@arm.com
174811051Sandreas.hansson@arm.combool
174911051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk)
175011051Sandreas.hansson@arm.com{
175111051Sandreas.hansson@arm.com    if (blk.isDirty()) {
175211051Sandreas.hansson@arm.com        assert(blk.isValid());
175311051Sandreas.hansson@arm.com
175412574Sodanrc@yahoo.com.br        Request request(tags->regenerateBlkAddr(&blk), blkSize, 0,
175512574Sodanrc@yahoo.com.br                        Request::funcMasterId);
175611051Sandreas.hansson@arm.com        request.taskId(blk.task_id);
175711865Snikos.nikoleris@arm.com        if (blk.isSecure()) {
175811865Snikos.nikoleris@arm.com            request.setFlags(Request::SECURE);
175911865Snikos.nikoleris@arm.com        }
176011051Sandreas.hansson@arm.com
176111051Sandreas.hansson@arm.com        Packet packet(&request, MemCmd::WriteReq);
176211051Sandreas.hansson@arm.com        packet.dataStatic(blk.data);
176311051Sandreas.hansson@arm.com
176411051Sandreas.hansson@arm.com        memSidePort->sendFunctional(&packet);
176511051Sandreas.hansson@arm.com
176611051Sandreas.hansson@arm.com        blk.status &= ~BlkDirty;
176711051Sandreas.hansson@arm.com    }
176811051Sandreas.hansson@arm.com
176911051Sandreas.hansson@arm.com    return true;
177011051Sandreas.hansson@arm.com}
177111051Sandreas.hansson@arm.com
177211051Sandreas.hansson@arm.combool
177311051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk)
177411051Sandreas.hansson@arm.com{
177511051Sandreas.hansson@arm.com
177611051Sandreas.hansson@arm.com    if (blk.isDirty())
177711051Sandreas.hansson@arm.com        warn_once("Invalidating dirty cache lines. Expect things to break.\n");
177811051Sandreas.hansson@arm.com
177911051Sandreas.hansson@arm.com    if (blk.isValid()) {
178011051Sandreas.hansson@arm.com        assert(!blk.isDirty());
178111867Snikos.nikoleris@arm.com        invalidateBlock(&blk);
178211051Sandreas.hansson@arm.com    }
178311051Sandreas.hansson@arm.com
178411051Sandreas.hansson@arm.com    return true;
178511051Sandreas.hansson@arm.com}
178611051Sandreas.hansson@arm.com
178711051Sandreas.hansson@arm.comCacheBlk*
178811051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks)
178911051Sandreas.hansson@arm.com{
179012600Sodanrc@yahoo.com.br    // Find replacement victim
179111051Sandreas.hansson@arm.com    CacheBlk *blk = tags->findVictim(addr);
179211051Sandreas.hansson@arm.com
179311484Snikos.nikoleris@arm.com    // It is valid to return nullptr if there is no victim
179411051Sandreas.hansson@arm.com    if (!blk)
179511051Sandreas.hansson@arm.com        return nullptr;
179611051Sandreas.hansson@arm.com
179711051Sandreas.hansson@arm.com    if (blk->isValid()) {
179812574Sodanrc@yahoo.com.br        Addr repl_addr = tags->regenerateBlkAddr(blk);
179911051Sandreas.hansson@arm.com        MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure());
180011051Sandreas.hansson@arm.com        if (repl_mshr) {
180112599Snikos.nikoleris@arm.com            // must be an outstanding upgrade or clean request
180211051Sandreas.hansson@arm.com            // on a block we're about to replace...
180312599Snikos.nikoleris@arm.com            assert((!blk->isWritable() && repl_mshr->needsWritable()) ||
180412599Snikos.nikoleris@arm.com                   repl_mshr->isCleaning());
180511051Sandreas.hansson@arm.com            // too hard to replace block with transient state
180611051Sandreas.hansson@arm.com            // allocation failed, block not inserted
180711484Snikos.nikoleris@arm.com            return nullptr;
180811051Sandreas.hansson@arm.com        } else {
180911483Snikos.nikoleris@arm.com            DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx "
181011483Snikos.nikoleris@arm.com                    "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns",
181111051Sandreas.hansson@arm.com                    addr, is_secure ? "s" : "ns",
181211051Sandreas.hansson@arm.com                    blk->isDirty() ? "writeback" : "clean");
181311051Sandreas.hansson@arm.com
181411436SRekai.GonzalezAlberquilla@arm.com            if (blk->wasPrefetched()) {
181511436SRekai.GonzalezAlberquilla@arm.com                unusedPrefetches++;
181611436SRekai.GonzalezAlberquilla@arm.com            }
181711051Sandreas.hansson@arm.com            // Will send up Writeback/CleanEvict snoops via isCachedAbove
181811051Sandreas.hansson@arm.com            // when pushing this writeback list into the write buffer.
181911199Sandreas.hansson@arm.com            if (blk->isDirty() || writebackClean) {
182011051Sandreas.hansson@arm.com                // Save writeback packet for handling by caller
182111051Sandreas.hansson@arm.com                writebacks.push_back(writebackBlk(blk));
182211051Sandreas.hansson@arm.com            } else {
182311051Sandreas.hansson@arm.com                writebacks.push_back(cleanEvictBlk(blk));
182411051Sandreas.hansson@arm.com            }
182512702Snikos.nikoleris@arm.com            replacements++;
182611051Sandreas.hansson@arm.com        }
182711051Sandreas.hansson@arm.com    }
182811051Sandreas.hansson@arm.com
182911051Sandreas.hansson@arm.com    return blk;
183011051Sandreas.hansson@arm.com}
183111051Sandreas.hansson@arm.com
183211197Sandreas.hansson@arm.comvoid
183311197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk)
183411197Sandreas.hansson@arm.com{
183511197Sandreas.hansson@arm.com    if (blk != tempBlock)
183611197Sandreas.hansson@arm.com        tags->invalidate(blk);
183711197Sandreas.hansson@arm.com    blk->invalidate();
183811197Sandreas.hansson@arm.com}
183911051Sandreas.hansson@arm.com
184011051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than
184111051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function
184211051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic
184311051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the
184411051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete).
184511051Sandreas.hansson@arm.comCacheBlk*
184611197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks,
184711197Sandreas.hansson@arm.com                  bool allocate)
184811051Sandreas.hansson@arm.com{
184911051Sandreas.hansson@arm.com    assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq);
185011051Sandreas.hansson@arm.com    Addr addr = pkt->getAddr();
185111051Sandreas.hansson@arm.com    bool is_secure = pkt->isSecure();
185211051Sandreas.hansson@arm.com#if TRACING_ON
185311051Sandreas.hansson@arm.com    CacheBlk::State old_state = blk ? blk->status : 0;
185411051Sandreas.hansson@arm.com#endif
185511051Sandreas.hansson@arm.com
185611375Sandreas.hansson@arm.com    // When handling a fill, we should have no writes to this line.
185711892Snikos.nikoleris@arm.com    assert(addr == pkt->getBlockAddr(blkSize));
185811375Sandreas.hansson@arm.com    assert(!writeBuffer.findMatch(addr, is_secure));
185911051Sandreas.hansson@arm.com
186011484Snikos.nikoleris@arm.com    if (blk == nullptr) {
186111051Sandreas.hansson@arm.com        // better have read new data...
186211051Sandreas.hansson@arm.com        assert(pkt->hasData());
186311051Sandreas.hansson@arm.com
186411051Sandreas.hansson@arm.com        // only read responses and write-line requests have data;
186511051Sandreas.hansson@arm.com        // note that we don't write the data here for write-line - that
186611601Sandreas.hansson@arm.com        // happens in the subsequent call to satisfyRequest
186711051Sandreas.hansson@arm.com        assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq);
186811051Sandreas.hansson@arm.com
186911197Sandreas.hansson@arm.com        // need to do a replacement if allocating, otherwise we stick
187011197Sandreas.hansson@arm.com        // with the temporary storage
187111484Snikos.nikoleris@arm.com        blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr;
187211197Sandreas.hansson@arm.com
187311484Snikos.nikoleris@arm.com        if (blk == nullptr) {
187411197Sandreas.hansson@arm.com            // No replaceable block or a mostly exclusive
187511197Sandreas.hansson@arm.com            // cache... just use temporary storage to complete the
187611197Sandreas.hansson@arm.com            // current request and then get rid of it
187711051Sandreas.hansson@arm.com            assert(!tempBlock->isValid());
187811051Sandreas.hansson@arm.com            blk = tempBlock;
187911051Sandreas.hansson@arm.com            tempBlock->set = tags->extractSet(addr);
188011051Sandreas.hansson@arm.com            tempBlock->tag = tags->extractTag(addr);
188112552Snikos.nikoleris@arm.com            if (is_secure) {
188212552Snikos.nikoleris@arm.com                tempBlock->status |= BlkSecure;
188312552Snikos.nikoleris@arm.com            }
188411051Sandreas.hansson@arm.com            DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr,
188511051Sandreas.hansson@arm.com                    is_secure ? "s" : "ns");
188611051Sandreas.hansson@arm.com        } else {
188711051Sandreas.hansson@arm.com            tags->insertBlock(pkt, blk);
188811051Sandreas.hansson@arm.com        }
188911051Sandreas.hansson@arm.com
189011051Sandreas.hansson@arm.com        // we should never be overwriting a valid block
189111051Sandreas.hansson@arm.com        assert(!blk->isValid());
189211051Sandreas.hansson@arm.com    } else {
189311051Sandreas.hansson@arm.com        // existing block... probably an upgrade
189411051Sandreas.hansson@arm.com        assert(blk->tag == tags->extractTag(addr));
189511051Sandreas.hansson@arm.com        // either we're getting new data or the block should already be valid
189611051Sandreas.hansson@arm.com        assert(pkt->hasData() || blk->isValid());
189711051Sandreas.hansson@arm.com        // don't clear block status... if block is already dirty we
189811051Sandreas.hansson@arm.com        // don't want to lose that
189911051Sandreas.hansson@arm.com    }
190011051Sandreas.hansson@arm.com
190111051Sandreas.hansson@arm.com    if (is_secure)
190211051Sandreas.hansson@arm.com        blk->status |= BlkSecure;
190311051Sandreas.hansson@arm.com    blk->status |= BlkValid | BlkReadable;
190411051Sandreas.hansson@arm.com
190511137Sandreas.hansson@arm.com    // sanity check for whole-line writes, which should always be
190611137Sandreas.hansson@arm.com    // marked as writable as part of the fill, and then later marked
190711601Sandreas.hansson@arm.com    // dirty as part of satisfyRequest
190811137Sandreas.hansson@arm.com    if (pkt->cmd == MemCmd::WriteLineReq) {
190911284Sandreas.hansson@arm.com        assert(!pkt->hasSharers());
191011137Sandreas.hansson@arm.com    }
191111137Sandreas.hansson@arm.com
191211284Sandreas.hansson@arm.com    // here we deal with setting the appropriate state of the line,
191311284Sandreas.hansson@arm.com    // and we start by looking at the hasSharers flag, and ignore the
191411284Sandreas.hansson@arm.com    // cacheResponding flag (normally signalling dirty data) if the
191511284Sandreas.hansson@arm.com    // packet has sharers, thus the line is never allocated as Owned
191611284Sandreas.hansson@arm.com    // (dirty but not writable), and always ends up being either
191711284Sandreas.hansson@arm.com    // Shared, Exclusive or Modified, see Packet::setCacheResponding
191811284Sandreas.hansson@arm.com    // for more details
191911284Sandreas.hansson@arm.com    if (!pkt->hasSharers()) {
192011284Sandreas.hansson@arm.com        // we could get a writable line from memory (rather than a
192111284Sandreas.hansson@arm.com        // cache) even in a read-only cache, note that we set this bit
192211284Sandreas.hansson@arm.com        // even for a read-only cache, possibly revisit this decision
192311051Sandreas.hansson@arm.com        blk->status |= BlkWritable;
192411051Sandreas.hansson@arm.com
192511284Sandreas.hansson@arm.com        // check if we got this via cache-to-cache transfer (i.e., from a
192611284Sandreas.hansson@arm.com        // cache that had the block in Modified or Owned state)
192711284Sandreas.hansson@arm.com        if (pkt->cacheResponding()) {
192811284Sandreas.hansson@arm.com            // we got the block in Modified state, and invalidated the
192911284Sandreas.hansson@arm.com            // owners copy
193011051Sandreas.hansson@arm.com            blk->status |= BlkDirty;
193111051Sandreas.hansson@arm.com
193211051Sandreas.hansson@arm.com            chatty_assert(!isReadOnly, "Should never see dirty snoop response "
193311051Sandreas.hansson@arm.com                          "in read-only cache %s\n", name());
193411051Sandreas.hansson@arm.com        }
193511051Sandreas.hansson@arm.com    }
193611051Sandreas.hansson@arm.com
193711051Sandreas.hansson@arm.com    DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n",
193811051Sandreas.hansson@arm.com            addr, is_secure ? "s" : "ns", old_state, blk->print());
193911051Sandreas.hansson@arm.com
194011051Sandreas.hansson@arm.com    // if we got new data, copy it in (checking for a read response
194111051Sandreas.hansson@arm.com    // and a response that has data is the same in the end)
194211051Sandreas.hansson@arm.com    if (pkt->isRead()) {
194311051Sandreas.hansson@arm.com        // sanity checks
194411051Sandreas.hansson@arm.com        assert(pkt->hasData());
194511051Sandreas.hansson@arm.com        assert(pkt->getSize() == blkSize);
194611051Sandreas.hansson@arm.com
194712633Sodanrc@yahoo.com.br        pkt->writeDataToBlock(blk->data, blkSize);
194811051Sandreas.hansson@arm.com    }
194911051Sandreas.hansson@arm.com    // We pay for fillLatency here.
195011051Sandreas.hansson@arm.com    blk->whenReady = clockEdge() + fillLatency * clockPeriod() +
195111051Sandreas.hansson@arm.com        pkt->payloadDelay;
195211051Sandreas.hansson@arm.com
195311051Sandreas.hansson@arm.com    return blk;
195411051Sandreas.hansson@arm.com}
195511051Sandreas.hansson@arm.com
195611051Sandreas.hansson@arm.com
195711051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
195811051Sandreas.hansson@arm.com//
195911051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side
196011051Sandreas.hansson@arm.com//
196111051Sandreas.hansson@arm.com/////////////////////////////////////////////////////
196211051Sandreas.hansson@arm.com
196311051Sandreas.hansson@arm.comvoid
196411051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data,
196511051Sandreas.hansson@arm.com                              bool already_copied, bool pending_inval)
196611051Sandreas.hansson@arm.com{
196711051Sandreas.hansson@arm.com    // sanity check
196811051Sandreas.hansson@arm.com    assert(req_pkt->isRequest());
196911051Sandreas.hansson@arm.com    assert(req_pkt->needsResponse());
197011051Sandreas.hansson@arm.com
197111744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: for %s\n", __func__, req_pkt->print());
197211051Sandreas.hansson@arm.com    // timing-mode snoop responses require a new packet, unless we
197311051Sandreas.hansson@arm.com    // already made a copy...
197411051Sandreas.hansson@arm.com    PacketPtr pkt = req_pkt;
197511051Sandreas.hansson@arm.com    if (!already_copied)
197611051Sandreas.hansson@arm.com        // do not clear flags, and allocate space for data if the
197711051Sandreas.hansson@arm.com        // packet needs it (the only packets that carry data are read
197811051Sandreas.hansson@arm.com        // responses)
197911051Sandreas.hansson@arm.com        pkt = new Packet(req_pkt, false, req_pkt->isRead());
198011051Sandreas.hansson@arm.com
198111051Sandreas.hansson@arm.com    assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() ||
198211284Sandreas.hansson@arm.com           pkt->hasSharers());
198311051Sandreas.hansson@arm.com    pkt->makeTimingResponse();
198411051Sandreas.hansson@arm.com    if (pkt->isRead()) {
198511051Sandreas.hansson@arm.com        pkt->setDataFromBlock(blk_data, blkSize);
198611051Sandreas.hansson@arm.com    }
198711051Sandreas.hansson@arm.com    if (pkt->cmd == MemCmd::ReadResp && pending_inval) {
198811051Sandreas.hansson@arm.com        // Assume we defer a response to a read from a far-away cache
198911051Sandreas.hansson@arm.com        // A, then later defer a ReadExcl from a cache B on the same
199011284Sandreas.hansson@arm.com        // bus as us. We'll assert cacheResponding in both cases, but
199111284Sandreas.hansson@arm.com        // in the latter case cacheResponding will keep the
199211284Sandreas.hansson@arm.com        // invalidation from reaching cache A. This special response
199311284Sandreas.hansson@arm.com        // tells cache A that it gets the block to satisfy its read,
199411284Sandreas.hansson@arm.com        // but must immediately invalidate it.
199511051Sandreas.hansson@arm.com        pkt->cmd = MemCmd::ReadRespWithInvalidate;
199611051Sandreas.hansson@arm.com    }
199711051Sandreas.hansson@arm.com    // Here we consider forward_time, paying for just forward latency and
199811051Sandreas.hansson@arm.com    // also charging the delay provided by the xbar.
199911051Sandreas.hansson@arm.com    // forward_time is used as send_time in next allocateWriteBuffer().
200011051Sandreas.hansson@arm.com    Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay;
200111051Sandreas.hansson@arm.com    // Here we reset the timing of the packet.
200211051Sandreas.hansson@arm.com    pkt->headerDelay = pkt->payloadDelay = 0;
200311744Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s: created response: %s tick: %lu\n", __func__,
200411744Snikos.nikoleris@arm.com            pkt->print(), forward_time);
200511051Sandreas.hansson@arm.com    memSidePort->schedTimingSnoopResp(pkt, forward_time, true);
200611051Sandreas.hansson@arm.com}
200711051Sandreas.hansson@arm.com
200811127Sandreas.hansson@arm.comuint32_t
200911051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing,
201011051Sandreas.hansson@arm.com                   bool is_deferred, bool pending_inval)
201111051Sandreas.hansson@arm.com{
201211744Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print());
201311051Sandreas.hansson@arm.com    // deferred snoops can only happen in timing mode
201411051Sandreas.hansson@arm.com    assert(!(is_deferred && !is_timing));
201511051Sandreas.hansson@arm.com    // pending_inval only makes sense on deferred snoops
201611051Sandreas.hansson@arm.com    assert(!(pending_inval && !is_deferred));
201711051Sandreas.hansson@arm.com    assert(pkt->isRequest());
201811051Sandreas.hansson@arm.com
201911051Sandreas.hansson@arm.com    // the packet may get modified if we or a forwarded snooper
202011051Sandreas.hansson@arm.com    // responds in atomic mode, so remember a few things about the
202111051Sandreas.hansson@arm.com    // original packet up front
202211051Sandreas.hansson@arm.com    bool invalidate = pkt->isInvalidate();
202311284Sandreas.hansson@arm.com    bool M5_VAR_USED needs_writable = pkt->needsWritable();
202411051Sandreas.hansson@arm.com
202511285Sandreas.hansson@arm.com    // at the moment we could get an uncacheable write which does not
202611285Sandreas.hansson@arm.com    // have the invalidate flag, and we need a suitable way of dealing
202711285Sandreas.hansson@arm.com    // with this case
202811285Sandreas.hansson@arm.com    panic_if(invalidate && pkt->req->isUncacheable(),
202911744Snikos.nikoleris@arm.com             "%s got an invalidating uncacheable snoop request %s",
203011744Snikos.nikoleris@arm.com             name(), pkt->print());
203111285Sandreas.hansson@arm.com
203211127Sandreas.hansson@arm.com    uint32_t snoop_delay = 0;
203311127Sandreas.hansson@arm.com
203411051Sandreas.hansson@arm.com    if (forwardSnoops) {
203511051Sandreas.hansson@arm.com        // first propagate snoop upward to see if anyone above us wants to
203611051Sandreas.hansson@arm.com        // handle it.  save & restore packet src since it will get
203711051Sandreas.hansson@arm.com        // rewritten to be relative to cpu-side bus (if any)
203811284Sandreas.hansson@arm.com        bool alreadyResponded = pkt->cacheResponding();
203911051Sandreas.hansson@arm.com        if (is_timing) {
204011051Sandreas.hansson@arm.com            // copy the packet so that we can clear any flags before
204111051Sandreas.hansson@arm.com            // forwarding it upwards, we also allocate data (passing
204211051Sandreas.hansson@arm.com            // the pointer along in case of static data), in case
204311051Sandreas.hansson@arm.com            // there is a snoop hit in upper levels
204411051Sandreas.hansson@arm.com            Packet snoopPkt(pkt, true, true);
204511051Sandreas.hansson@arm.com            snoopPkt.setExpressSnoop();
204611051Sandreas.hansson@arm.com            // the snoop packet does not need to wait any additional
204711051Sandreas.hansson@arm.com            // time
204811051Sandreas.hansson@arm.com            snoopPkt.headerDelay = snoopPkt.payloadDelay = 0;
204911051Sandreas.hansson@arm.com            cpuSidePort->sendTimingSnoopReq(&snoopPkt);
205011127Sandreas.hansson@arm.com
205111127Sandreas.hansson@arm.com            // add the header delay (including crossbar and snoop
205211127Sandreas.hansson@arm.com            // delays) of the upward snoop to the snoop delay for this
205311127Sandreas.hansson@arm.com            // cache
205411127Sandreas.hansson@arm.com            snoop_delay += snoopPkt.headerDelay;
205511127Sandreas.hansson@arm.com
205611284Sandreas.hansson@arm.com            if (snoopPkt.cacheResponding()) {
205711051Sandreas.hansson@arm.com                // cache-to-cache response from some upper cache
205811051Sandreas.hansson@arm.com                assert(!alreadyResponded);
205911284Sandreas.hansson@arm.com                pkt->setCacheResponding();
206011051Sandreas.hansson@arm.com            }
206111284Sandreas.hansson@arm.com            // upstream cache has the block, or has an outstanding
206211284Sandreas.hansson@arm.com            // MSHR, pass the flag on
206311284Sandreas.hansson@arm.com            if (snoopPkt.hasSharers()) {
206411284Sandreas.hansson@arm.com                pkt->setHasSharers();
206511051Sandreas.hansson@arm.com            }
206611051Sandreas.hansson@arm.com            // If this request is a prefetch or clean evict and an upper level
206711051Sandreas.hansson@arm.com            // signals block present, make sure to propagate the block
206811051Sandreas.hansson@arm.com            // presence to the requester.
206911051Sandreas.hansson@arm.com            if (snoopPkt.isBlockCached()) {
207011051Sandreas.hansson@arm.com                pkt->setBlockCached();
207111051Sandreas.hansson@arm.com            }
207212349Snikos.nikoleris@arm.com            // If the request was satisfied by snooping the cache
207312349Snikos.nikoleris@arm.com            // above, mark the original packet as satisfied too.
207412349Snikos.nikoleris@arm.com            if (snoopPkt.satisfied()) {
207512349Snikos.nikoleris@arm.com                pkt->setSatisfied();
207612349Snikos.nikoleris@arm.com            }
207711051Sandreas.hansson@arm.com        } else {
207811051Sandreas.hansson@arm.com            cpuSidePort->sendAtomicSnoop(pkt);
207911284Sandreas.hansson@arm.com            if (!alreadyResponded && pkt->cacheResponding()) {
208011051Sandreas.hansson@arm.com                // cache-to-cache response from some upper cache:
208111051Sandreas.hansson@arm.com                // forward response to original requester
208211051Sandreas.hansson@arm.com                assert(pkt->isResponse());
208311051Sandreas.hansson@arm.com            }
208411051Sandreas.hansson@arm.com        }
208511051Sandreas.hansson@arm.com    }
208611051Sandreas.hansson@arm.com
208712349Snikos.nikoleris@arm.com    bool respond = false;
208812349Snikos.nikoleris@arm.com    bool blk_valid = blk && blk->isValid();
208912349Snikos.nikoleris@arm.com    if (pkt->isClean()) {
209012349Snikos.nikoleris@arm.com        if (blk_valid && blk->isDirty()) {
209112349Snikos.nikoleris@arm.com            DPRINTF(CacheVerbose, "%s: packet (snoop) %s found block: %s\n",
209212349Snikos.nikoleris@arm.com                    __func__, pkt->print(), blk->print());
209312351Snikos.nikoleris@arm.com            PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id);
209412349Snikos.nikoleris@arm.com            PacketList writebacks;
209512349Snikos.nikoleris@arm.com            writebacks.push_back(wb_pkt);
209612349Snikos.nikoleris@arm.com
209712349Snikos.nikoleris@arm.com            if (is_timing) {
209812349Snikos.nikoleris@arm.com                // anything that is merely forwarded pays for the forward
209912349Snikos.nikoleris@arm.com                // latency and the delay provided by the crossbar
210012349Snikos.nikoleris@arm.com                Tick forward_time = clockEdge(forwardLatency) +
210112349Snikos.nikoleris@arm.com                    pkt->headerDelay;
210212349Snikos.nikoleris@arm.com                doWritebacks(writebacks, forward_time);
210312349Snikos.nikoleris@arm.com            } else {
210412349Snikos.nikoleris@arm.com                doWritebacksAtomic(writebacks);
210512349Snikos.nikoleris@arm.com            }
210612349Snikos.nikoleris@arm.com            pkt->setSatisfied();
210712349Snikos.nikoleris@arm.com        }
210812349Snikos.nikoleris@arm.com    } else if (!blk_valid) {
210911744Snikos.nikoleris@arm.com        DPRINTF(CacheVerbose, "%s: snoop miss for %s\n", __func__,
211011744Snikos.nikoleris@arm.com                pkt->print());
211111493Sandreas.hansson@arm.com        if (is_deferred) {
211211493Sandreas.hansson@arm.com            // we no longer have the block, and will not respond, but a
211311493Sandreas.hansson@arm.com            // packet was allocated in MSHR::handleSnoop and we have
211411493Sandreas.hansson@arm.com            // to delete it
211511493Sandreas.hansson@arm.com            assert(pkt->needsResponse());
211611493Sandreas.hansson@arm.com
211711493Sandreas.hansson@arm.com            // we have passed the block to a cache upstream, that
211811493Sandreas.hansson@arm.com            // cache should be responding
211911493Sandreas.hansson@arm.com            assert(pkt->cacheResponding());
212011493Sandreas.hansson@arm.com
212111493Sandreas.hansson@arm.com            delete pkt;
212211493Sandreas.hansson@arm.com        }
212311127Sandreas.hansson@arm.com        return snoop_delay;
212411051Sandreas.hansson@arm.com    } else {
212511744Snikos.nikoleris@arm.com        DPRINTF(Cache, "%s: snoop hit for %s, old state is %s\n", __func__,
212611744Snikos.nikoleris@arm.com                pkt->print(), blk->print());
212712349Snikos.nikoleris@arm.com
212812349Snikos.nikoleris@arm.com        // We may end up modifying both the block state and the packet (if
212912349Snikos.nikoleris@arm.com        // we respond in atomic mode), so just figure out what to do now
213012349Snikos.nikoleris@arm.com        // and then do it later. We respond to all snoops that need
213112349Snikos.nikoleris@arm.com        // responses provided we have the block in dirty state. The
213212349Snikos.nikoleris@arm.com        // invalidation itself is taken care of below. We don't respond to
213312349Snikos.nikoleris@arm.com        // cache maintenance operations as this is done by the destination
213412349Snikos.nikoleris@arm.com        // xbar.
213512349Snikos.nikoleris@arm.com        respond = blk->isDirty() && pkt->needsResponse();
213612349Snikos.nikoleris@arm.com
213712349Snikos.nikoleris@arm.com        chatty_assert(!(isReadOnly && blk->isDirty()), "Should never have "
213812349Snikos.nikoleris@arm.com                      "a dirty block in a read-only cache %s\n", name());
213911051Sandreas.hansson@arm.com    }
214011051Sandreas.hansson@arm.com
214111051Sandreas.hansson@arm.com    // Invalidate any prefetch's from below that would strip write permissions
214211051Sandreas.hansson@arm.com    // MemCmd::HardPFReq is only observed by upstream caches.  After missing
214311051Sandreas.hansson@arm.com    // above and in it's own cache, a new MemCmd::ReadReq is created that
214411051Sandreas.hansson@arm.com    // downstream caches observe.
214511051Sandreas.hansson@arm.com    if (pkt->mustCheckAbove()) {
214611483Snikos.nikoleris@arm.com        DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s "
214711744Snikos.nikoleris@arm.com                "from lower cache\n", pkt->getAddr(), pkt->print());
214811051Sandreas.hansson@arm.com        pkt->setBlockCached();
214911127Sandreas.hansson@arm.com        return snoop_delay;
215011051Sandreas.hansson@arm.com    }
215111051Sandreas.hansson@arm.com
215211285Sandreas.hansson@arm.com    if (pkt->isRead() && !invalidate) {
215311285Sandreas.hansson@arm.com        // reading without requiring the line in a writable state
215411284Sandreas.hansson@arm.com        assert(!needs_writable);
215511284Sandreas.hansson@arm.com        pkt->setHasSharers();
215611285Sandreas.hansson@arm.com
215711285Sandreas.hansson@arm.com        // if the requesting packet is uncacheable, retain the line in
215811285Sandreas.hansson@arm.com        // the current state, otherwhise unset the writable flag,
215911285Sandreas.hansson@arm.com        // which means we go from Modified to Owned (and will respond
216011285Sandreas.hansson@arm.com        // below), remain in Owned (and will respond below), from
216111285Sandreas.hansson@arm.com        // Exclusive to Shared, or remain in Shared
216211285Sandreas.hansson@arm.com        if (!pkt->req->isUncacheable())
216311285Sandreas.hansson@arm.com            blk->status &= ~BlkWritable;
216412349Snikos.nikoleris@arm.com        DPRINTF(Cache, "new state is %s\n", blk->print());
216511051Sandreas.hansson@arm.com    }
216611051Sandreas.hansson@arm.com
216711051Sandreas.hansson@arm.com    if (respond) {
216811051Sandreas.hansson@arm.com        // prevent anyone else from responding, cache as well as
216911051Sandreas.hansson@arm.com        // memory, and also prevent any memory from even seeing the
217011284Sandreas.hansson@arm.com        // request
217111284Sandreas.hansson@arm.com        pkt->setCacheResponding();
217212349Snikos.nikoleris@arm.com        if (!pkt->isClean() && blk->isWritable()) {
217311284Sandreas.hansson@arm.com            // inform the cache hierarchy that this cache had the line
217411284Sandreas.hansson@arm.com            // in the Modified state so that we avoid unnecessary
217511284Sandreas.hansson@arm.com            // invalidations (see Packet::setResponderHadWritable)
217611284Sandreas.hansson@arm.com            pkt->setResponderHadWritable();
217711284Sandreas.hansson@arm.com
217811081Sandreas.hansson@arm.com            // in the case of an uncacheable request there is no point
217911284Sandreas.hansson@arm.com            // in setting the responderHadWritable flag, but since the
218011284Sandreas.hansson@arm.com            // recipient does not care there is no harm in doing so
218111284Sandreas.hansson@arm.com        } else {
218211284Sandreas.hansson@arm.com            // if the packet has needsWritable set we invalidate our
218311284Sandreas.hansson@arm.com            // copy below and all other copies will be invalidates
218411284Sandreas.hansson@arm.com            // through express snoops, and if needsWritable is not set
218511284Sandreas.hansson@arm.com            // we already called setHasSharers above
218611051Sandreas.hansson@arm.com        }
218711284Sandreas.hansson@arm.com
218811285Sandreas.hansson@arm.com        // if we are returning a writable and dirty (Modified) line,
218911285Sandreas.hansson@arm.com        // we should be invalidating the line
219011285Sandreas.hansson@arm.com        panic_if(!invalidate && !pkt->hasSharers(),
219111744Snikos.nikoleris@arm.com                 "%s is passing a Modified line through %s, "
219211744Snikos.nikoleris@arm.com                 "but keeping the block", name(), pkt->print());
219311285Sandreas.hansson@arm.com
219411051Sandreas.hansson@arm.com        if (is_timing) {
219511051Sandreas.hansson@arm.com            doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval);
219611051Sandreas.hansson@arm.com        } else {
219711051Sandreas.hansson@arm.com            pkt->makeAtomicResponse();
219811286Sandreas.hansson@arm.com            // packets such as upgrades do not actually have any data
219911286Sandreas.hansson@arm.com            // payload
220011286Sandreas.hansson@arm.com            if (pkt->hasData())
220111286Sandreas.hansson@arm.com                pkt->setDataFromBlock(blk->data, blkSize);
220211051Sandreas.hansson@arm.com        }
220311051Sandreas.hansson@arm.com    }
220411051Sandreas.hansson@arm.com
220511602Sandreas.hansson@arm.com    if (!respond && is_deferred) {
220611051Sandreas.hansson@arm.com        assert(pkt->needsResponse());
220711602Sandreas.hansson@arm.com
220811602Sandreas.hansson@arm.com        // if we copied the deferred packet with the intention to
220911602Sandreas.hansson@arm.com        // respond, but are not responding, then a cache above us must
221011602Sandreas.hansson@arm.com        // be, and we can use this as the indication of whether this
221111602Sandreas.hansson@arm.com        // is a packet where we created a copy of the request or not
221211602Sandreas.hansson@arm.com        if (!pkt->cacheResponding()) {
221311602Sandreas.hansson@arm.com            delete pkt->req;
221411602Sandreas.hansson@arm.com        }
221511602Sandreas.hansson@arm.com
221611051Sandreas.hansson@arm.com        delete pkt;
221711051Sandreas.hansson@arm.com    }
221811051Sandreas.hansson@arm.com
221911051Sandreas.hansson@arm.com    // Do this last in case it deallocates block data or something
222011051Sandreas.hansson@arm.com    // like that
222112349Snikos.nikoleris@arm.com    if (blk_valid && invalidate) {
222211197Sandreas.hansson@arm.com        invalidateBlock(blk);
222312349Snikos.nikoleris@arm.com        DPRINTF(Cache, "new state is %s\n", blk->print());
222411051Sandreas.hansson@arm.com    }
222511051Sandreas.hansson@arm.com
222611127Sandreas.hansson@arm.com    return snoop_delay;
222711051Sandreas.hansson@arm.com}
222811051Sandreas.hansson@arm.com
222911051Sandreas.hansson@arm.com
223011051Sandreas.hansson@arm.comvoid
223111051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt)
223211051Sandreas.hansson@arm.com{
223311744Snikos.nikoleris@arm.com    DPRINTF(CacheVerbose, "%s: for %s\n", __func__, pkt->print());
223411051Sandreas.hansson@arm.com
223511051Sandreas.hansson@arm.com    // Snoops shouldn't happen when bypassing caches
223611051Sandreas.hansson@arm.com    assert(!system->bypassCaches());
223711051Sandreas.hansson@arm.com
223811130Sali.jafri@arm.com    // no need to snoop requests that are not in range
223911051Sandreas.hansson@arm.com    if (!inRange(pkt->getAddr())) {
224011051Sandreas.hansson@arm.com        return;
224111051Sandreas.hansson@arm.com    }
224211051Sandreas.hansson@arm.com
224311051Sandreas.hansson@arm.com    bool is_secure = pkt->isSecure();
224411051Sandreas.hansson@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
224511051Sandreas.hansson@arm.com
224611892Snikos.nikoleris@arm.com    Addr blk_addr = pkt->getBlockAddr(blkSize);
224711051Sandreas.hansson@arm.com    MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure);
224811051Sandreas.hansson@arm.com
224911127Sandreas.hansson@arm.com    // Update the latency cost of the snoop so that the crossbar can
225011127Sandreas.hansson@arm.com    // account for it. Do not overwrite what other neighbouring caches
225111127Sandreas.hansson@arm.com    // have already done, rather take the maximum. The update is
225211127Sandreas.hansson@arm.com    // tentative, for cases where we return before an upward snoop
225311127Sandreas.hansson@arm.com    // happens below.
225411127Sandreas.hansson@arm.com    pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay,
225511127Sandreas.hansson@arm.com                                         lookupLatency * clockPeriod());
225611127Sandreas.hansson@arm.com
225711051Sandreas.hansson@arm.com    // Inform request(Prefetch, CleanEvict or Writeback) from below of
225811051Sandreas.hansson@arm.com    // MSHR hit, set setBlockCached.
225911051Sandreas.hansson@arm.com    if (mshr && pkt->mustCheckAbove()) {
226011744Snikos.nikoleris@arm.com        DPRINTF(Cache, "Setting block cached for %s from lower cache on "
226111744Snikos.nikoleris@arm.com                "mshr hit\n", pkt->print());
226211051Sandreas.hansson@arm.com        pkt->setBlockCached();
226311051Sandreas.hansson@arm.com        return;
226411051Sandreas.hansson@arm.com    }
226511051Sandreas.hansson@arm.com
226612349Snikos.nikoleris@arm.com    // Bypass any existing cache maintenance requests if the request
226712349Snikos.nikoleris@arm.com    // has been satisfied already (i.e., the dirty block has been
226812349Snikos.nikoleris@arm.com    // found).
226912349Snikos.nikoleris@arm.com    if (mshr && pkt->req->isCacheMaintenance() && pkt->satisfied()) {
227012349Snikos.nikoleris@arm.com        return;
227112349Snikos.nikoleris@arm.com    }
227212349Snikos.nikoleris@arm.com
227311051Sandreas.hansson@arm.com    // Let the MSHR itself track the snoop and decide whether we want
227411051Sandreas.hansson@arm.com    // to go ahead and do the regular cache snoop
227511051Sandreas.hansson@arm.com    if (mshr && mshr->handleSnoop(pkt, order++)) {
227611051Sandreas.hansson@arm.com        DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)."
227711051Sandreas.hansson@arm.com                "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns",
227811051Sandreas.hansson@arm.com                mshr->print());
227911051Sandreas.hansson@arm.com
228011051Sandreas.hansson@arm.com        if (mshr->getNumTargets() > numTarget)
228111051Sandreas.hansson@arm.com            warn("allocating bonus target for snoop"); //handle later
228211051Sandreas.hansson@arm.com        return;
228311051Sandreas.hansson@arm.com    }
228411051Sandreas.hansson@arm.com
228511051Sandreas.hansson@arm.com    //We also need to check the writeback buffers and handle those
228611375Sandreas.hansson@arm.com    WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure);
228711375Sandreas.hansson@arm.com    if (wb_entry) {
228811051Sandreas.hansson@arm.com        DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n",
228911051Sandreas.hansson@arm.com                pkt->getAddr(), is_secure ? "s" : "ns");
229011051Sandreas.hansson@arm.com        // Expect to see only Writebacks and/or CleanEvicts here, both of
229111051Sandreas.hansson@arm.com        // which should not be generated for uncacheable data.
229211051Sandreas.hansson@arm.com        assert(!wb_entry->isUncacheable());
229311051Sandreas.hansson@arm.com        // There should only be a single request responsible for generating
229411051Sandreas.hansson@arm.com        // Writebacks/CleanEvicts.
229511051Sandreas.hansson@arm.com        assert(wb_entry->getNumTargets() == 1);
229611051Sandreas.hansson@arm.com        PacketPtr wb_pkt = wb_entry->getTarget()->pkt;
229712345Snikos.nikoleris@arm.com        assert(wb_pkt->isEviction() || wb_pkt->cmd == MemCmd::WriteClean);
229811051Sandreas.hansson@arm.com
229911199Sandreas.hansson@arm.com        if (pkt->isEviction()) {
230011051Sandreas.hansson@arm.com            // if the block is found in the write queue, set the BLOCK_CACHED
230111051Sandreas.hansson@arm.com            // flag for Writeback/CleanEvict snoop. On return the snoop will
230211051Sandreas.hansson@arm.com            // propagate the BLOCK_CACHED flag in Writeback packets and prevent
230311051Sandreas.hansson@arm.com            // any CleanEvicts from travelling down the memory hierarchy.
230411051Sandreas.hansson@arm.com            pkt->setBlockCached();
230511744Snikos.nikoleris@arm.com            DPRINTF(Cache, "%s: Squashing %s from lower cache on writequeue "
230611744Snikos.nikoleris@arm.com                    "hit\n", __func__, pkt->print());
230711051Sandreas.hansson@arm.com            return;
230811051Sandreas.hansson@arm.com        }
230911051Sandreas.hansson@arm.com
231011332Sandreas.hansson@arm.com        // conceptually writebacks are no different to other blocks in
231111332Sandreas.hansson@arm.com        // this cache, so the behaviour is modelled after handleSnoop,
231211332Sandreas.hansson@arm.com        // the difference being that instead of querying the block
231311332Sandreas.hansson@arm.com        // state to determine if it is dirty and writable, we use the
231411332Sandreas.hansson@arm.com        // command and fields of the writeback packet
231511332Sandreas.hansson@arm.com        bool respond = wb_pkt->cmd == MemCmd::WritebackDirty &&
231611751Snikos.nikoleris@arm.com            pkt->needsResponse();
231711332Sandreas.hansson@arm.com        bool have_writable = !wb_pkt->hasSharers();
231811332Sandreas.hansson@arm.com        bool invalidate = pkt->isInvalidate();
231911332Sandreas.hansson@arm.com
232011332Sandreas.hansson@arm.com        if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) {
232111332Sandreas.hansson@arm.com            assert(!pkt->needsWritable());
232211332Sandreas.hansson@arm.com            pkt->setHasSharers();
232311332Sandreas.hansson@arm.com            wb_pkt->setHasSharers();
232411332Sandreas.hansson@arm.com        }
232511332Sandreas.hansson@arm.com
232611332Sandreas.hansson@arm.com        if (respond) {
232711284Sandreas.hansson@arm.com            pkt->setCacheResponding();
232811332Sandreas.hansson@arm.com
232911332Sandreas.hansson@arm.com            if (have_writable) {
233011332Sandreas.hansson@arm.com                pkt->setResponderHadWritable();
233111051Sandreas.hansson@arm.com            }
233211332Sandreas.hansson@arm.com
233311051Sandreas.hansson@arm.com            doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(),
233411051Sandreas.hansson@arm.com                                   false, false);
233511051Sandreas.hansson@arm.com        }
233611051Sandreas.hansson@arm.com
233712349Snikos.nikoleris@arm.com        if (invalidate && wb_pkt->cmd != MemCmd::WriteClean) {
233811051Sandreas.hansson@arm.com            // Invalidation trumps our writeback... discard here
233911051Sandreas.hansson@arm.com            // Note: markInService will remove entry from writeback buffer.
234011375Sandreas.hansson@arm.com            markInService(wb_entry);
234111051Sandreas.hansson@arm.com            delete wb_pkt;
234211051Sandreas.hansson@arm.com        }
234311051Sandreas.hansson@arm.com    }
234411051Sandreas.hansson@arm.com
234511051Sandreas.hansson@arm.com    // If this was a shared writeback, there may still be
234611051Sandreas.hansson@arm.com    // other shared copies above that require invalidation.
234711051Sandreas.hansson@arm.com    // We could be more selective and return here if the
234811051Sandreas.hansson@arm.com    // request is non-exclusive or if the writeback is
234911051Sandreas.hansson@arm.com    // exclusive.
235011127Sandreas.hansson@arm.com    uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false);
235111127Sandreas.hansson@arm.com
235211127Sandreas.hansson@arm.com    // Override what we did when we first saw the snoop, as we now
235311127Sandreas.hansson@arm.com    // also have the cost of the upwards snoops to account for
235411127Sandreas.hansson@arm.com    pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay +
235511127Sandreas.hansson@arm.com                                         lookupLatency * clockPeriod());
235611051Sandreas.hansson@arm.com}
235711051Sandreas.hansson@arm.com
235811051Sandreas.hansson@arm.combool
235911051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt)
236011051Sandreas.hansson@arm.com{
236111051Sandreas.hansson@arm.com    // Express snoop responses from master to slave, e.g., from L1 to L2
236211051Sandreas.hansson@arm.com    cache->recvTimingSnoopResp(pkt);
236311051Sandreas.hansson@arm.com    return true;
236411051Sandreas.hansson@arm.com}
236511051Sandreas.hansson@arm.com
236611051Sandreas.hansson@arm.comTick
236711051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt)
236811051Sandreas.hansson@arm.com{
236911051Sandreas.hansson@arm.com    // Snoops shouldn't happen when bypassing caches
237011051Sandreas.hansson@arm.com    assert(!system->bypassCaches());
237111051Sandreas.hansson@arm.com
237211130Sali.jafri@arm.com    // no need to snoop requests that are not in range.
237311130Sali.jafri@arm.com    if (!inRange(pkt->getAddr())) {
237411051Sandreas.hansson@arm.com        return 0;
237511051Sandreas.hansson@arm.com    }
237611051Sandreas.hansson@arm.com
237711051Sandreas.hansson@arm.com    CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
237811127Sandreas.hansson@arm.com    uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false);
237911127Sandreas.hansson@arm.com    return snoop_delay + lookupLatency * clockPeriod();
238011051Sandreas.hansson@arm.com}
238111051Sandreas.hansson@arm.com
238211051Sandreas.hansson@arm.com
238311375Sandreas.hansson@arm.comQueueEntry*
238411375Sandreas.hansson@arm.comCache::getNextQueueEntry()
238511051Sandreas.hansson@arm.com{
238611051Sandreas.hansson@arm.com    // Check both MSHR queue and write buffer for potential requests,
238711051Sandreas.hansson@arm.com    // note that null does not mean there is no request, it could
238811051Sandreas.hansson@arm.com    // simply be that it is not ready
238911375Sandreas.hansson@arm.com    MSHR *miss_mshr  = mshrQueue.getNext();
239011375Sandreas.hansson@arm.com    WriteQueueEntry *wq_entry = writeBuffer.getNext();
239111051Sandreas.hansson@arm.com
239211051Sandreas.hansson@arm.com    // If we got a write buffer request ready, first priority is a
239311453Sandreas.hansson@arm.com    // full write buffer, otherwise we favour the miss requests
239411453Sandreas.hansson@arm.com    if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) {
239511051Sandreas.hansson@arm.com        // need to search MSHR queue for conflicting earlier miss.
239611051Sandreas.hansson@arm.com        MSHR *conflict_mshr =
239711375Sandreas.hansson@arm.com            mshrQueue.findPending(wq_entry->blkAddr,
239811375Sandreas.hansson@arm.com                                  wq_entry->isSecure);
239911375Sandreas.hansson@arm.com
240011375Sandreas.hansson@arm.com        if (conflict_mshr && conflict_mshr->order < wq_entry->order) {
240111051Sandreas.hansson@arm.com            // Service misses in order until conflict is cleared.
240211051Sandreas.hansson@arm.com            return conflict_mshr;
240311051Sandreas.hansson@arm.com
240411051Sandreas.hansson@arm.com            // @todo Note that we ignore the ready time of the conflict here
240511051Sandreas.hansson@arm.com        }
240611051Sandreas.hansson@arm.com
240711051Sandreas.hansson@arm.com        // No conflicts; issue write
240811375Sandreas.hansson@arm.com        return wq_entry;
240911051Sandreas.hansson@arm.com    } else if (miss_mshr) {
241011051Sandreas.hansson@arm.com        // need to check for conflicting earlier writeback
241111375Sandreas.hansson@arm.com        WriteQueueEntry *conflict_mshr =
241211051Sandreas.hansson@arm.com            writeBuffer.findPending(miss_mshr->blkAddr,
241311051Sandreas.hansson@arm.com                                    miss_mshr->isSecure);
241411051Sandreas.hansson@arm.com        if (conflict_mshr) {
241511051Sandreas.hansson@arm.com            // not sure why we don't check order here... it was in the
241611051Sandreas.hansson@arm.com            // original code but commented out.
241711051Sandreas.hansson@arm.com
241811051Sandreas.hansson@arm.com            // The only way this happens is if we are
241911051Sandreas.hansson@arm.com            // doing a write and we didn't have permissions
242011051Sandreas.hansson@arm.com            // then subsequently saw a writeback (owned got evicted)
242111051Sandreas.hansson@arm.com            // We need to make sure to perform the writeback first
242211051Sandreas.hansson@arm.com            // To preserve the dirty data, then we can issue the write
242311051Sandreas.hansson@arm.com
242411375Sandreas.hansson@arm.com            // should we return wq_entry here instead?  I.e. do we
242511051Sandreas.hansson@arm.com            // have to flush writes in order?  I don't think so... not
242611051Sandreas.hansson@arm.com            // for Alpha anyway.  Maybe for x86?
242711051Sandreas.hansson@arm.com            return conflict_mshr;
242811051Sandreas.hansson@arm.com
242911051Sandreas.hansson@arm.com            // @todo Note that we ignore the ready time of the conflict here
243011051Sandreas.hansson@arm.com        }
243111051Sandreas.hansson@arm.com
243211051Sandreas.hansson@arm.com        // No conflicts; issue read
243311051Sandreas.hansson@arm.com        return miss_mshr;
243411051Sandreas.hansson@arm.com    }
243511051Sandreas.hansson@arm.com
243611051Sandreas.hansson@arm.com    // fall through... no pending requests.  Try a prefetch.
243711375Sandreas.hansson@arm.com    assert(!miss_mshr && !wq_entry);
243811051Sandreas.hansson@arm.com    if (prefetcher && mshrQueue.canPrefetch()) {
243911051Sandreas.hansson@arm.com        // If we have a miss queue slot, we can try a prefetch
244011051Sandreas.hansson@arm.com        PacketPtr pkt = prefetcher->getPacket();
244111051Sandreas.hansson@arm.com        if (pkt) {
244211892Snikos.nikoleris@arm.com            Addr pf_addr = pkt->getBlockAddr(blkSize);
244311051Sandreas.hansson@arm.com            if (!tags->findBlock(pf_addr, pkt->isSecure()) &&
244411051Sandreas.hansson@arm.com                !mshrQueue.findMatch(pf_addr, pkt->isSecure()) &&
244511051Sandreas.hansson@arm.com                !writeBuffer.findMatch(pf_addr, pkt->isSecure())) {
244611051Sandreas.hansson@arm.com                // Update statistic on number of prefetches issued
244711051Sandreas.hansson@arm.com                // (hwpf_mshr_misses)
244811051Sandreas.hansson@arm.com                assert(pkt->req->masterId() < system->maxMasters());
244911051Sandreas.hansson@arm.com                mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
245011051Sandreas.hansson@arm.com
245111051Sandreas.hansson@arm.com                // allocate an MSHR and return it, note
245211051Sandreas.hansson@arm.com                // that we send the packet straight away, so do not
245311051Sandreas.hansson@arm.com                // schedule the send
245411051Sandreas.hansson@arm.com                return allocateMissBuffer(pkt, curTick(), false);
245511051Sandreas.hansson@arm.com            } else {
245611051Sandreas.hansson@arm.com                // free the request and packet
245711051Sandreas.hansson@arm.com                delete pkt->req;
245811051Sandreas.hansson@arm.com                delete pkt;
245911051Sandreas.hansson@arm.com            }
246011051Sandreas.hansson@arm.com        }
246111051Sandreas.hansson@arm.com    }
246211051Sandreas.hansson@arm.com
246311375Sandreas.hansson@arm.com    return nullptr;
246411051Sandreas.hansson@arm.com}
246511051Sandreas.hansson@arm.com
246611051Sandreas.hansson@arm.combool
246711130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const
246811051Sandreas.hansson@arm.com{
246911051Sandreas.hansson@arm.com    if (!forwardSnoops)
247011051Sandreas.hansson@arm.com        return false;
247111051Sandreas.hansson@arm.com    // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and
247211051Sandreas.hansson@arm.com    // Writeback snoops into upper level caches to check for copies of the
247311051Sandreas.hansson@arm.com    // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict
247411051Sandreas.hansson@arm.com    // packet, the cache can inform the crossbar below of presence or absence
247511051Sandreas.hansson@arm.com    // of the block.
247611130Sali.jafri@arm.com    if (is_timing) {
247711130Sali.jafri@arm.com        Packet snoop_pkt(pkt, true, false);
247811130Sali.jafri@arm.com        snoop_pkt.setExpressSnoop();
247911130Sali.jafri@arm.com        // Assert that packet is either Writeback or CleanEvict and not a
248011130Sali.jafri@arm.com        // prefetch request because prefetch requests need an MSHR and may
248111130Sali.jafri@arm.com        // generate a snoop response.
248212345Snikos.nikoleris@arm.com        assert(pkt->isEviction() || pkt->cmd == MemCmd::WriteClean);
248311484Snikos.nikoleris@arm.com        snoop_pkt.senderState = nullptr;
248411130Sali.jafri@arm.com        cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
248511130Sali.jafri@arm.com        // Writeback/CleanEvict snoops do not generate a snoop response.
248611284Sandreas.hansson@arm.com        assert(!(snoop_pkt.cacheResponding()));
248711130Sali.jafri@arm.com        return snoop_pkt.isBlockCached();
248811130Sali.jafri@arm.com    } else {
248911130Sali.jafri@arm.com        cpuSidePort->sendAtomicSnoop(pkt);
249011130Sali.jafri@arm.com        return pkt->isBlockCached();
249111130Sali.jafri@arm.com    }
249211051Sandreas.hansson@arm.com}
249311051Sandreas.hansson@arm.com
249411375Sandreas.hansson@arm.comTick
249511375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const
249611051Sandreas.hansson@arm.com{
249711375Sandreas.hansson@arm.com    Tick nextReady = std::min(mshrQueue.nextReadyTime(),
249811375Sandreas.hansson@arm.com                              writeBuffer.nextReadyTime());
249911375Sandreas.hansson@arm.com
250011375Sandreas.hansson@arm.com    // Don't signal prefetch ready time if no MSHRs available
250111375Sandreas.hansson@arm.com    // Will signal once enoguh MSHRs are deallocated
250211375Sandreas.hansson@arm.com    if (prefetcher && mshrQueue.canPrefetch()) {
250311375Sandreas.hansson@arm.com        nextReady = std::min(nextReady,
250411375Sandreas.hansson@arm.com                             prefetcher->nextPrefetchReadyTime());
250511051Sandreas.hansson@arm.com    }
250611051Sandreas.hansson@arm.com
250711375Sandreas.hansson@arm.com    return nextReady;
250811375Sandreas.hansson@arm.com}
250911375Sandreas.hansson@arm.com
251011375Sandreas.hansson@arm.combool
251111375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr)
251211375Sandreas.hansson@arm.com{
251311375Sandreas.hansson@arm.com    assert(mshr);
251411375Sandreas.hansson@arm.com
251511051Sandreas.hansson@arm.com    // use request from 1st target
251611051Sandreas.hansson@arm.com    PacketPtr tgt_pkt = mshr->getTarget()->pkt;
251711375Sandreas.hansson@arm.com
251811744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print());
251911051Sandreas.hansson@arm.com
252011051Sandreas.hansson@arm.com    CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure);
252111051Sandreas.hansson@arm.com
252211051Sandreas.hansson@arm.com    if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) {
252311375Sandreas.hansson@arm.com        // we should never have hardware prefetches to allocated
252411375Sandreas.hansson@arm.com        // blocks
252511484Snikos.nikoleris@arm.com        assert(blk == nullptr);
252611375Sandreas.hansson@arm.com
252711051Sandreas.hansson@arm.com        // We need to check the caches above us to verify that
252811051Sandreas.hansson@arm.com        // they don't have a copy of this block in the dirty state
252911051Sandreas.hansson@arm.com        // at the moment. Without this check we could get a stale
253011051Sandreas.hansson@arm.com        // copy from memory that might get used in place of the
253111051Sandreas.hansson@arm.com        // dirty one.
253211051Sandreas.hansson@arm.com        Packet snoop_pkt(tgt_pkt, true, false);
253311051Sandreas.hansson@arm.com        snoop_pkt.setExpressSnoop();
253411275Sandreas.hansson@arm.com        // We are sending this packet upwards, but if it hits we will
253511275Sandreas.hansson@arm.com        // get a snoop response that we end up treating just like a
253611275Sandreas.hansson@arm.com        // normal response, hence it needs the MSHR as its sender
253711275Sandreas.hansson@arm.com        // state
253811051Sandreas.hansson@arm.com        snoop_pkt.senderState = mshr;
253911051Sandreas.hansson@arm.com        cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
254011051Sandreas.hansson@arm.com
254111051Sandreas.hansson@arm.com        // Check to see if the prefetch was squashed by an upper cache (to
254211051Sandreas.hansson@arm.com        // prevent us from grabbing the line) or if a Check to see if a
254311051Sandreas.hansson@arm.com        // writeback arrived between the time the prefetch was placed in
254411051Sandreas.hansson@arm.com        // the MSHRs and when it was selected to be sent or if the
254511051Sandreas.hansson@arm.com        // prefetch was squashed by an upper cache.
254611051Sandreas.hansson@arm.com
254711284Sandreas.hansson@arm.com        // It is important to check cacheResponding before
254811284Sandreas.hansson@arm.com        // prefetchSquashed. If another cache has committed to
254911284Sandreas.hansson@arm.com        // responding, it will be sending a dirty response which will
255011284Sandreas.hansson@arm.com        // arrive at the MSHR allocated for this request. Checking the
255111284Sandreas.hansson@arm.com        // prefetchSquash first may result in the MSHR being
255211284Sandreas.hansson@arm.com        // prematurely deallocated.
255311284Sandreas.hansson@arm.com        if (snoop_pkt.cacheResponding()) {
255411276Sandreas.hansson@arm.com            auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req);
255511276Sandreas.hansson@arm.com            assert(r.second);
255611284Sandreas.hansson@arm.com
255711284Sandreas.hansson@arm.com            // if we are getting a snoop response with no sharers it
255811284Sandreas.hansson@arm.com            // will be allocated as Modified
255911284Sandreas.hansson@arm.com            bool pending_modified_resp = !snoop_pkt.hasSharers();
256011284Sandreas.hansson@arm.com            markInService(mshr, pending_modified_resp);
256111284Sandreas.hansson@arm.com
256211051Sandreas.hansson@arm.com            DPRINTF(Cache, "Upward snoop of prefetch for addr"
256311051Sandreas.hansson@arm.com                    " %#x (%s) hit\n",
256411051Sandreas.hansson@arm.com                    tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns");
256511375Sandreas.hansson@arm.com            return false;
256611051Sandreas.hansson@arm.com        }
256711051Sandreas.hansson@arm.com
256811375Sandreas.hansson@arm.com        if (snoop_pkt.isBlockCached()) {
256911051Sandreas.hansson@arm.com            DPRINTF(Cache, "Block present, prefetch squashed by cache.  "
257011051Sandreas.hansson@arm.com                    "Deallocating mshr target %#x.\n",
257111051Sandreas.hansson@arm.com                    mshr->blkAddr);
257211375Sandreas.hansson@arm.com
257311051Sandreas.hansson@arm.com            // Deallocate the mshr target
257411375Sandreas.hansson@arm.com            if (mshrQueue.forceDeallocateTarget(mshr)) {
257511277Sandreas.hansson@arm.com                // Clear block if this deallocation resulted freed an
257611277Sandreas.hansson@arm.com                // mshr when all had previously been utilized
257711375Sandreas.hansson@arm.com                clearBlocked(Blocked_NoMSHRs);
257811051Sandreas.hansson@arm.com            }
257912167Spau.cabre@metempsy.com
258012167Spau.cabre@metempsy.com            // given that no response is expected, delete Request and Packet
258112167Spau.cabre@metempsy.com            delete tgt_pkt->req;
258212167Spau.cabre@metempsy.com            delete tgt_pkt;
258312167Spau.cabre@metempsy.com
258411375Sandreas.hansson@arm.com            return false;
258511051Sandreas.hansson@arm.com        }
258611051Sandreas.hansson@arm.com    }
258711051Sandreas.hansson@arm.com
258811375Sandreas.hansson@arm.com    // either a prefetch that is not present upstream, or a normal
258911375Sandreas.hansson@arm.com    // MSHR request, proceed to get the packet to send downstream
259011452Sandreas.hansson@arm.com    PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable());
259111375Sandreas.hansson@arm.com
259211484Snikos.nikoleris@arm.com    mshr->isForward = (pkt == nullptr);
259311375Sandreas.hansson@arm.com
259411375Sandreas.hansson@arm.com    if (mshr->isForward) {
259511375Sandreas.hansson@arm.com        // not a cache block request, but a response is expected
259611375Sandreas.hansson@arm.com        // make copy of current packet to forward, keep current
259711375Sandreas.hansson@arm.com        // copy for response handling
259811375Sandreas.hansson@arm.com        pkt = new Packet(tgt_pkt, false, true);
259911375Sandreas.hansson@arm.com        assert(!pkt->isWrite());
260011375Sandreas.hansson@arm.com    }
260111375Sandreas.hansson@arm.com
260211375Sandreas.hansson@arm.com    // play it safe and append (rather than set) the sender state,
260311375Sandreas.hansson@arm.com    // as forwarded packets may already have existing state
260411375Sandreas.hansson@arm.com    pkt->pushSenderState(mshr);
260511375Sandreas.hansson@arm.com
260612349Snikos.nikoleris@arm.com    if (pkt->isClean() && blk && blk->isDirty()) {
260712349Snikos.nikoleris@arm.com        // A cache clean opearation is looking for a dirty block. Mark
260812349Snikos.nikoleris@arm.com        // the packet so that the destination xbar can determine that
260912349Snikos.nikoleris@arm.com        // there will be a follow-up write packet as well.
261012349Snikos.nikoleris@arm.com        pkt->setSatisfied();
261112349Snikos.nikoleris@arm.com    }
261212349Snikos.nikoleris@arm.com
261311375Sandreas.hansson@arm.com    if (!memSidePort->sendTimingReq(pkt)) {
261411375Sandreas.hansson@arm.com        // we are awaiting a retry, but we
261511375Sandreas.hansson@arm.com        // delete the packet and will be creating a new packet
261611375Sandreas.hansson@arm.com        // when we get the opportunity
261711375Sandreas.hansson@arm.com        delete pkt;
261811375Sandreas.hansson@arm.com
261911375Sandreas.hansson@arm.com        // note that we have now masked any requestBus and
262011375Sandreas.hansson@arm.com        // schedSendEvent (we will wait for a retry before
262111375Sandreas.hansson@arm.com        // doing anything), and this is so even if we do not
262211375Sandreas.hansson@arm.com        // care about this packet and might override it before
262311375Sandreas.hansson@arm.com        // it gets retried
262411375Sandreas.hansson@arm.com        return true;
262511375Sandreas.hansson@arm.com    } else {
262611375Sandreas.hansson@arm.com        // As part of the call to sendTimingReq the packet is
262711375Sandreas.hansson@arm.com        // forwarded to all neighbouring caches (and any caches
262811375Sandreas.hansson@arm.com        // above them) as a snoop. Thus at this point we know if
262911375Sandreas.hansson@arm.com        // any of the neighbouring caches are responding, and if
263011375Sandreas.hansson@arm.com        // so, we know it is dirty, and we can determine if it is
263111375Sandreas.hansson@arm.com        // being passed as Modified, making our MSHR the ordering
263211375Sandreas.hansson@arm.com        // point
263311375Sandreas.hansson@arm.com        bool pending_modified_resp = !pkt->hasSharers() &&
263411375Sandreas.hansson@arm.com            pkt->cacheResponding();
263511375Sandreas.hansson@arm.com        markInService(mshr, pending_modified_resp);
263612349Snikos.nikoleris@arm.com        if (pkt->isClean() && blk && blk->isDirty()) {
263712349Snikos.nikoleris@arm.com            // A cache clean opearation is looking for a dirty
263812349Snikos.nikoleris@arm.com            // block. If a dirty block is encountered a WriteClean
263912349Snikos.nikoleris@arm.com            // will update any copies to the path to the memory
264012349Snikos.nikoleris@arm.com            // until the point of reference.
264112349Snikos.nikoleris@arm.com            DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n",
264212349Snikos.nikoleris@arm.com                    __func__, pkt->print(), blk->print());
264312351Snikos.nikoleris@arm.com            PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(),
264412351Snikos.nikoleris@arm.com                                             pkt->id);
264512349Snikos.nikoleris@arm.com            PacketList writebacks;
264612349Snikos.nikoleris@arm.com            writebacks.push_back(wb_pkt);
264712349Snikos.nikoleris@arm.com            doWritebacks(writebacks, 0);
264812349Snikos.nikoleris@arm.com        }
264912349Snikos.nikoleris@arm.com
265011375Sandreas.hansson@arm.com        return false;
265111375Sandreas.hansson@arm.com    }
265211375Sandreas.hansson@arm.com}
265311375Sandreas.hansson@arm.com
265411375Sandreas.hansson@arm.combool
265511375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry)
265611375Sandreas.hansson@arm.com{
265711375Sandreas.hansson@arm.com    assert(wq_entry);
265811375Sandreas.hansson@arm.com
265911375Sandreas.hansson@arm.com    // always a single target for write queue entries
266011375Sandreas.hansson@arm.com    PacketPtr tgt_pkt = wq_entry->getTarget()->pkt;
266111375Sandreas.hansson@arm.com
266211744Snikos.nikoleris@arm.com    DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print());
266311375Sandreas.hansson@arm.com
266411453Sandreas.hansson@arm.com    // forward as is, both for evictions and uncacheable writes
266511453Sandreas.hansson@arm.com    if (!memSidePort->sendTimingReq(tgt_pkt)) {
266611375Sandreas.hansson@arm.com        // note that we have now masked any requestBus and
266711375Sandreas.hansson@arm.com        // schedSendEvent (we will wait for a retry before
266811375Sandreas.hansson@arm.com        // doing anything), and this is so even if we do not
266911375Sandreas.hansson@arm.com        // care about this packet and might override it before
267011375Sandreas.hansson@arm.com        // it gets retried
267111375Sandreas.hansson@arm.com        return true;
267211375Sandreas.hansson@arm.com    } else {
267311375Sandreas.hansson@arm.com        markInService(wq_entry);
267411375Sandreas.hansson@arm.com        return false;
267511051Sandreas.hansson@arm.com    }
267611051Sandreas.hansson@arm.com}
267711051Sandreas.hansson@arm.com
267811051Sandreas.hansson@arm.comvoid
267911051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const
268011051Sandreas.hansson@arm.com{
268111051Sandreas.hansson@arm.com    bool dirty(isDirty());
268211051Sandreas.hansson@arm.com
268311051Sandreas.hansson@arm.com    if (dirty) {
268411051Sandreas.hansson@arm.com        warn("*** The cache still contains dirty data. ***\n");
268511051Sandreas.hansson@arm.com        warn("    Make sure to drain the system using the correct flags.\n");
268611483Snikos.nikoleris@arm.com        warn("    This checkpoint will not restore correctly and dirty data "
268711483Snikos.nikoleris@arm.com             "    in the cache will be lost!\n");
268811051Sandreas.hansson@arm.com    }
268911051Sandreas.hansson@arm.com
269011051Sandreas.hansson@arm.com    // Since we don't checkpoint the data in the cache, any dirty data
269111051Sandreas.hansson@arm.com    // will be lost when restoring from a checkpoint of a system that
269211051Sandreas.hansson@arm.com    // wasn't drained properly. Flag the checkpoint as invalid if the
269311051Sandreas.hansson@arm.com    // cache contains dirty data.
269411051Sandreas.hansson@arm.com    bool bad_checkpoint(dirty);
269511051Sandreas.hansson@arm.com    SERIALIZE_SCALAR(bad_checkpoint);
269611051Sandreas.hansson@arm.com}
269711051Sandreas.hansson@arm.com
269811051Sandreas.hansson@arm.comvoid
269911051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp)
270011051Sandreas.hansson@arm.com{
270111051Sandreas.hansson@arm.com    bool bad_checkpoint;
270211051Sandreas.hansson@arm.com    UNSERIALIZE_SCALAR(bad_checkpoint);
270311051Sandreas.hansson@arm.com    if (bad_checkpoint) {
270411051Sandreas.hansson@arm.com        fatal("Restoring from checkpoints with dirty caches is not supported "
270511051Sandreas.hansson@arm.com              "in the classic memory system. Please remove any caches or "
270611051Sandreas.hansson@arm.com              " drain them properly before taking checkpoints.\n");
270711051Sandreas.hansson@arm.com    }
270811051Sandreas.hansson@arm.com}
270911051Sandreas.hansson@arm.com
271011051Sandreas.hansson@arm.com///////////////
271111051Sandreas.hansson@arm.com//
271211051Sandreas.hansson@arm.com// CpuSidePort
271311051Sandreas.hansson@arm.com//
271411051Sandreas.hansson@arm.com///////////////
271511051Sandreas.hansson@arm.com
271611051Sandreas.hansson@arm.comAddrRangeList
271711051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const
271811051Sandreas.hansson@arm.com{
271911051Sandreas.hansson@arm.com    return cache->getAddrRanges();
272011051Sandreas.hansson@arm.com}
272111051Sandreas.hansson@arm.com
272211051Sandreas.hansson@arm.combool
272312343Snikos.nikoleris@arm.comCache::CpuSidePort::tryTiming(PacketPtr pkt)
272412343Snikos.nikoleris@arm.com{
272512343Snikos.nikoleris@arm.com    assert(!cache->system->bypassCaches());
272612343Snikos.nikoleris@arm.com
272712343Snikos.nikoleris@arm.com    // always let express snoop packets through if even if blocked
272812343Snikos.nikoleris@arm.com    if (pkt->isExpressSnoop()) {
272912343Snikos.nikoleris@arm.com        return true;
273012343Snikos.nikoleris@arm.com    } else if (isBlocked() || mustSendRetry) {
273112343Snikos.nikoleris@arm.com        // either already committed to send a retry, or blocked
273212343Snikos.nikoleris@arm.com        mustSendRetry = true;
273312343Snikos.nikoleris@arm.com        return false;
273412343Snikos.nikoleris@arm.com    }
273512343Snikos.nikoleris@arm.com    mustSendRetry = false;
273612343Snikos.nikoleris@arm.com    return true;
273712343Snikos.nikoleris@arm.com}
273812343Snikos.nikoleris@arm.com
273912343Snikos.nikoleris@arm.combool
274011051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt)
274111051Sandreas.hansson@arm.com{
274211051Sandreas.hansson@arm.com    assert(!cache->system->bypassCaches());
274311051Sandreas.hansson@arm.com
274411334Sandreas.hansson@arm.com    // always let express snoop packets through if even if blocked
274512630Snikos.nikoleris@arm.com    if (pkt->isExpressSnoop() || tryTiming(pkt)) {
274612630Snikos.nikoleris@arm.com        cache->recvTimingReq(pkt);
274711051Sandreas.hansson@arm.com        return true;
274811051Sandreas.hansson@arm.com    }
274912630Snikos.nikoleris@arm.com    return false;
275011051Sandreas.hansson@arm.com}
275111051Sandreas.hansson@arm.com
275211051Sandreas.hansson@arm.comTick
275311051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt)
275411051Sandreas.hansson@arm.com{
275511051Sandreas.hansson@arm.com    return cache->recvAtomic(pkt);
275611051Sandreas.hansson@arm.com}
275711051Sandreas.hansson@arm.com
275811051Sandreas.hansson@arm.comvoid
275911051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt)
276011051Sandreas.hansson@arm.com{
276111051Sandreas.hansson@arm.com    // functional request
276211051Sandreas.hansson@arm.com    cache->functionalAccess(pkt, true);
276311051Sandreas.hansson@arm.com}
276411051Sandreas.hansson@arm.com
276511051Sandreas.hansson@arm.comCache::
276611051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache,
276711051Sandreas.hansson@arm.com                         const std::string &_label)
276811051Sandreas.hansson@arm.com    : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache)
276911051Sandreas.hansson@arm.com{
277011051Sandreas.hansson@arm.com}
277111051Sandreas.hansson@arm.com
277211053Sandreas.hansson@arm.comCache*
277311053Sandreas.hansson@arm.comCacheParams::create()
277411053Sandreas.hansson@arm.com{
277511053Sandreas.hansson@arm.com    assert(tags);
277612600Sodanrc@yahoo.com.br    assert(replacement_policy);
277711053Sandreas.hansson@arm.com
277811053Sandreas.hansson@arm.com    return new Cache(this);
277911053Sandreas.hansson@arm.com}
278011051Sandreas.hansson@arm.com///////////////
278111051Sandreas.hansson@arm.com//
278211051Sandreas.hansson@arm.com// MemSidePort
278311051Sandreas.hansson@arm.com//
278411051Sandreas.hansson@arm.com///////////////
278511051Sandreas.hansson@arm.com
278611051Sandreas.hansson@arm.combool
278711051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt)
278811051Sandreas.hansson@arm.com{
278911051Sandreas.hansson@arm.com    cache->recvTimingResp(pkt);
279011051Sandreas.hansson@arm.com    return true;
279111051Sandreas.hansson@arm.com}
279211051Sandreas.hansson@arm.com
279311051Sandreas.hansson@arm.com// Express snooping requests to memside port
279411051Sandreas.hansson@arm.comvoid
279511051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt)
279611051Sandreas.hansson@arm.com{
279711051Sandreas.hansson@arm.com    // handle snooping requests
279811051Sandreas.hansson@arm.com    cache->recvTimingSnoopReq(pkt);
279911051Sandreas.hansson@arm.com}
280011051Sandreas.hansson@arm.com
280111051Sandreas.hansson@arm.comTick
280211051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt)
280311051Sandreas.hansson@arm.com{
280411051Sandreas.hansson@arm.com    return cache->recvAtomicSnoop(pkt);
280511051Sandreas.hansson@arm.com}
280611051Sandreas.hansson@arm.com
280711051Sandreas.hansson@arm.comvoid
280811051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt)
280911051Sandreas.hansson@arm.com{
281011051Sandreas.hansson@arm.com    // functional snoop (note that in contrast to atomic we don't have
281111051Sandreas.hansson@arm.com    // a specific functionalSnoop method, as they have the same
281211051Sandreas.hansson@arm.com    // behaviour regardless)
281311051Sandreas.hansson@arm.com    cache->functionalAccess(pkt, false);
281411051Sandreas.hansson@arm.com}
281511051Sandreas.hansson@arm.com
281611051Sandreas.hansson@arm.comvoid
281711051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket()
281811051Sandreas.hansson@arm.com{
281911051Sandreas.hansson@arm.com    // sanity check
282011051Sandreas.hansson@arm.com    assert(!waitingOnRetry);
282111051Sandreas.hansson@arm.com
282211051Sandreas.hansson@arm.com    // there should never be any deferred request packets in the
282311051Sandreas.hansson@arm.com    // queue, instead we resly on the cache to provide the packets
282411051Sandreas.hansson@arm.com    // from the MSHR queue or write queue
282511051Sandreas.hansson@arm.com    assert(deferredPacketReadyTime() == MaxTick);
282611051Sandreas.hansson@arm.com
282711051Sandreas.hansson@arm.com    // check for request packets (requests & writebacks)
282811375Sandreas.hansson@arm.com    QueueEntry* entry = cache.getNextQueueEntry();
282911375Sandreas.hansson@arm.com
283011375Sandreas.hansson@arm.com    if (!entry) {
283111051Sandreas.hansson@arm.com        // can happen if e.g. we attempt a writeback and fail, but
283211051Sandreas.hansson@arm.com        // before the retry, the writeback is eliminated because
283311051Sandreas.hansson@arm.com        // we snoop another cache's ReadEx.
283411051Sandreas.hansson@arm.com    } else {
283511051Sandreas.hansson@arm.com        // let our snoop responses go first if there are responses to
283611375Sandreas.hansson@arm.com        // the same addresses
283711375Sandreas.hansson@arm.com        if (checkConflictingSnoop(entry->blkAddr)) {
283811051Sandreas.hansson@arm.com            return;
283911051Sandreas.hansson@arm.com        }
284011375Sandreas.hansson@arm.com        waitingOnRetry = entry->sendPacket(cache);
284111051Sandreas.hansson@arm.com    }
284211051Sandreas.hansson@arm.com
284311051Sandreas.hansson@arm.com    // if we succeeded and are not waiting for a retry, schedule the
284411375Sandreas.hansson@arm.com    // next send considering when the next queue is ready, note that
284511051Sandreas.hansson@arm.com    // snoop responses have their own packet queue and thus schedule
284611051Sandreas.hansson@arm.com    // their own events
284711051Sandreas.hansson@arm.com    if (!waitingOnRetry) {
284811375Sandreas.hansson@arm.com        schedSendEvent(cache.nextQueueReadyTime());
284911051Sandreas.hansson@arm.com    }
285011051Sandreas.hansson@arm.com}
285111051Sandreas.hansson@arm.com
285211051Sandreas.hansson@arm.comCache::
285311051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache,
285411051Sandreas.hansson@arm.com                         const std::string &_label)
285511051Sandreas.hansson@arm.com    : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue),
285611051Sandreas.hansson@arm.com      _reqQueue(*_cache, *this, _snoopRespQueue, _label),
285711051Sandreas.hansson@arm.com      _snoopRespQueue(*_cache, *this, _label), cache(_cache)
285811051Sandreas.hansson@arm.com{
285911051Sandreas.hansson@arm.com}
2860