cache.cc revision 11600
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2010-2016 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111288Ssteve.reinhardt@amd.com#include "debug/CacheVerbose.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6411051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6511051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6611051Sandreas.hansson@arm.com 6711053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6811053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6911051Sandreas.hansson@arm.com tags(p->tags), 7011051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7111051Sandreas.hansson@arm.com doFastWrites(true), 7211197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7311197Sandreas.hansson@arm.com clusivity(p->clusivity), 7411199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7511197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7611197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent(this, false, 7711197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7811051Sandreas.hansson@arm.com{ 7911051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 8011051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8111051Sandreas.hansson@arm.com 8211051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8311051Sandreas.hansson@arm.com "CpuSidePort"); 8411051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8511051Sandreas.hansson@arm.com "MemSidePort"); 8611051Sandreas.hansson@arm.com 8711051Sandreas.hansson@arm.com tags->setCache(this); 8811051Sandreas.hansson@arm.com if (prefetcher) 8911051Sandreas.hansson@arm.com prefetcher->setCache(this); 9011051Sandreas.hansson@arm.com} 9111051Sandreas.hansson@arm.com 9211051Sandreas.hansson@arm.comCache::~Cache() 9311051Sandreas.hansson@arm.com{ 9411051Sandreas.hansson@arm.com delete [] tempBlock->data; 9511051Sandreas.hansson@arm.com delete tempBlock; 9611051Sandreas.hansson@arm.com 9711051Sandreas.hansson@arm.com delete cpuSidePort; 9811051Sandreas.hansson@arm.com delete memSidePort; 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comvoid 10211051Sandreas.hansson@arm.comCache::regStats() 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com BaseCache::regStats(); 10511051Sandreas.hansson@arm.com} 10611051Sandreas.hansson@arm.com 10711051Sandreas.hansson@arm.comvoid 10811051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10911051Sandreas.hansson@arm.com{ 11011051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11111051Sandreas.hansson@arm.com 11211051Sandreas.hansson@arm.com uint64_t overwrite_val; 11311051Sandreas.hansson@arm.com bool overwrite_mem; 11411051Sandreas.hansson@arm.com uint64_t condition_val64; 11511051Sandreas.hansson@arm.com uint32_t condition_val32; 11611051Sandreas.hansson@arm.com 11711051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11811051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11911051Sandreas.hansson@arm.com 12011051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12111051Sandreas.hansson@arm.com 12211051Sandreas.hansson@arm.com overwrite_mem = true; 12311051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12411051Sandreas.hansson@arm.com // memory address into the packet 12511051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12611051Sandreas.hansson@arm.com pkt->setData(blk_data); 12711051Sandreas.hansson@arm.com 12811051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12911051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 13011051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13111051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13211051Sandreas.hansson@arm.com sizeof(uint64_t)); 13311051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13411051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13511051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13611051Sandreas.hansson@arm.com sizeof(uint32_t)); 13711051Sandreas.hansson@arm.com } else 13811051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13911051Sandreas.hansson@arm.com } 14011051Sandreas.hansson@arm.com 14111051Sandreas.hansson@arm.com if (overwrite_mem) { 14211051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14411051Sandreas.hansson@arm.com } 14511051Sandreas.hansson@arm.com} 14611051Sandreas.hansson@arm.com 14711051Sandreas.hansson@arm.com 14811051Sandreas.hansson@arm.comvoid 14911051Sandreas.hansson@arm.comCache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 15011051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15111051Sandreas.hansson@arm.com{ 15211051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15311051Sandreas.hansson@arm.com 15411051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15511051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15611051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15711051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15811051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15911051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 16011051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16111284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16211051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16311051Sandreas.hansson@arm.com 16411051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16511051Sandreas.hansson@arm.com // isWrite() will be true for them 16611051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16711051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16811051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16911284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 17011284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17111284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17211284Sandreas.hansson@arm.com // Exclusive, and never Modified 17311051Sandreas.hansson@arm.com assert(blk->isWritable()); 17411284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17511051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17611051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17711051Sandreas.hansson@arm.com } 17811284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 17911284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 18011284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18111284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18311288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (write)\n", 18411288Ssteve.reinhardt@amd.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 18511051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18611051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18711051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18811051Sandreas.hansson@arm.com } 18911286Sandreas.hansson@arm.com 19011286Sandreas.hansson@arm.com // all read responses have a data payload 19111286Sandreas.hansson@arm.com assert(pkt->hasRespData()); 19211051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 19311286Sandreas.hansson@arm.com 19411600Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache or not 19511600Sandreas.hansson@arm.com if (pkt->fromCache()) { 19611051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19711051Sandreas.hansson@arm.com // special handling for coherent block requests from 19811051Sandreas.hansson@arm.com // upper-level caches 19911284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20011051Sandreas.hansson@arm.com // sanity check 20111051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20211051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20311051Sandreas.hansson@arm.com 20411051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20511284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20611051Sandreas.hansson@arm.com if (blk->isDirty()) { 20711284Sandreas.hansson@arm.com pkt->setCacheResponding(); 20811051Sandreas.hansson@arm.com } 20911197Sandreas.hansson@arm.com // on ReadExReq we give up our copy unconditionally, 21011197Sandreas.hansson@arm.com // even if this cache is mostly inclusive, we may want 21111197Sandreas.hansson@arm.com // to revisit this 21211197Sandreas.hansson@arm.com invalidateBlock(blk); 21311051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21411284Sandreas.hansson@arm.com !pkt->hasSharers() && 21511051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21611284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21711284Sandreas.hansson@arm.com // request if: 21811284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 21911051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 22011051Sandreas.hansson@arm.com // signaling another read request 22111051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22211284Sandreas.hansson@arm.com // would have set hasSharers flag when 22311284Sandreas.hansson@arm.com // snooping the packet) 22411284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22511284Sandreas.hansson@arm.com // copy of the line 22611051Sandreas.hansson@arm.com if (blk->isDirty()) { 22711051Sandreas.hansson@arm.com // special considerations if we're owner: 22811051Sandreas.hansson@arm.com if (!deferred_response) { 22911284Sandreas.hansson@arm.com // respond with the line in Modified state 23011284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23111284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23211197Sandreas.hansson@arm.com 23311284Sandreas.hansson@arm.com if (clusivity == Enums::mostly_excl) { 23411284Sandreas.hansson@arm.com // if this cache is mostly exclusive with 23511284Sandreas.hansson@arm.com // respect to the cache above, drop the 23611284Sandreas.hansson@arm.com // block, no need to first unset the dirty 23711284Sandreas.hansson@arm.com // bit 23811284Sandreas.hansson@arm.com invalidateBlock(blk); 23911284Sandreas.hansson@arm.com } else { 24011284Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 24111284Sandreas.hansson@arm.com // keep the block in the Exclusive state, 24211284Sandreas.hansson@arm.com // and pass it upwards as Modified 24311284Sandreas.hansson@arm.com // (writable and dirty), hence we have 24411284Sandreas.hansson@arm.com // multiple caches, all on the same path 24511284Sandreas.hansson@arm.com // towards memory, all considering the 24611284Sandreas.hansson@arm.com // same block writable, but only one 24711284Sandreas.hansson@arm.com // considering it Modified 24811197Sandreas.hansson@arm.com 24911284Sandreas.hansson@arm.com // we get away with multiple caches (on 25011284Sandreas.hansson@arm.com // the same path to memory) considering 25111284Sandreas.hansson@arm.com // the block writeable as we always enter 25211284Sandreas.hansson@arm.com // the cache hierarchy through a cache, 25311284Sandreas.hansson@arm.com // and first snoop upwards in all other 25411284Sandreas.hansson@arm.com // branches 25511284Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 25611197Sandreas.hansson@arm.com } 25711051Sandreas.hansson@arm.com } else { 25811051Sandreas.hansson@arm.com // if we're responding after our own miss, 25911051Sandreas.hansson@arm.com // there's a window where the recipient didn't 26011051Sandreas.hansson@arm.com // know it was getting ownership and may not 26111051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 26211284Sandreas.hansson@arm.com // have to respond with a shared line 26311284Sandreas.hansson@arm.com pkt->setHasSharers(); 26411051Sandreas.hansson@arm.com } 26511051Sandreas.hansson@arm.com } 26611051Sandreas.hansson@arm.com } else { 26711051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 26811284Sandreas.hansson@arm.com pkt->setHasSharers(); 26911051Sandreas.hansson@arm.com } 27011051Sandreas.hansson@arm.com } 27111051Sandreas.hansson@arm.com } else { 27211284Sandreas.hansson@arm.com // Upgrade or Invalidate 27311051Sandreas.hansson@arm.com assert(pkt->isUpgrade() || pkt->isInvalidate()); 27411197Sandreas.hansson@arm.com 27511197Sandreas.hansson@arm.com // for invalidations we could be looking at the temp block 27611197Sandreas.hansson@arm.com // (for upgrades we always allocate) 27711197Sandreas.hansson@arm.com invalidateBlock(blk); 27811288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d (invalidation)\n", 27911051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 28011051Sandreas.hansson@arm.com } 28111051Sandreas.hansson@arm.com} 28211051Sandreas.hansson@arm.com 28311051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28411051Sandreas.hansson@arm.com// 28511051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 28611051Sandreas.hansson@arm.com// 28711051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28811051Sandreas.hansson@arm.com 28911051Sandreas.hansson@arm.combool 29011051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 29111051Sandreas.hansson@arm.com PacketList &writebacks) 29211051Sandreas.hansson@arm.com{ 29311051Sandreas.hansson@arm.com // sanity check 29411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 29511051Sandreas.hansson@arm.com 29611051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 29711051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 29811051Sandreas.hansson@arm.com name()); 29911051Sandreas.hansson@arm.com 30011288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 30111051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 30211051Sandreas.hansson@arm.com 30311051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 30411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), 30511051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 30611051Sandreas.hansson@arm.com pkt->getAddr()); 30711051Sandreas.hansson@arm.com 30811051Sandreas.hansson@arm.com // flush and invalidate any existing block 30911051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 31011051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 31111199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 31211051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 31311051Sandreas.hansson@arm.com else 31411051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 31511051Sandreas.hansson@arm.com tags->invalidate(old_blk); 31611051Sandreas.hansson@arm.com old_blk->invalidate(); 31711051Sandreas.hansson@arm.com } 31811051Sandreas.hansson@arm.com 31911484Snikos.nikoleris@arm.com blk = nullptr; 32011051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 32111051Sandreas.hansson@arm.com lat = lookupLatency; 32211051Sandreas.hansson@arm.com return false; 32311051Sandreas.hansson@arm.com } 32411051Sandreas.hansson@arm.com 32511051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 32611051Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 32711051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 32811051Sandreas.hansson@arm.com // that can modify its value. 32911051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 33011051Sandreas.hansson@arm.com 33111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(), 33211051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 33311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns", 33411051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 33511051Sandreas.hansson@arm.com 33611051Sandreas.hansson@arm.com 33711199Sandreas.hansson@arm.com if (pkt->isEviction()) { 33811051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 33911051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 34011051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 34111051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 34211051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 34311051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 34411051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 34511051Sandreas.hansson@arm.com // by crossbar. 34611375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 34711375Sandreas.hansson@arm.com pkt->isSecure()); 34811375Sandreas.hansson@arm.com if (wb_entry) { 34911199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 35011199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 35111199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 35211199Sandreas.hansson@arm.com 35311199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 35411199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 35511199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 35611199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 35711199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 35811199Sandreas.hansson@arm.com // the other upper level caches connected to this 35911199Sandreas.hansson@arm.com // cache have the block, so we can clear the 36011199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 36111199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 36211199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 36311199Sandreas.hansson@arm.com return true; 36411199Sandreas.hansson@arm.com } else { 36511199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 36611199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 36711199Sandreas.hansson@arm.com // writeback... discard here 36811199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 36911375Sandreas.hansson@arm.com markInService(wb_entry); 37011199Sandreas.hansson@arm.com delete wbPkt; 37111199Sandreas.hansson@arm.com } 37211051Sandreas.hansson@arm.com } 37311051Sandreas.hansson@arm.com } 37411051Sandreas.hansson@arm.com 37511051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 37611051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 37711199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 37811051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 37911199Sandreas.hansson@arm.com 38011199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 38111199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 38211199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 38311199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 38411199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 38511199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 38611199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 38711199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 38811199Sandreas.hansson@arm.com return true; 38911199Sandreas.hansson@arm.com } 39011199Sandreas.hansson@arm.com 39111484Snikos.nikoleris@arm.com if (blk == nullptr) { 39211051Sandreas.hansson@arm.com // need to do a replacement 39311051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 39411484Snikos.nikoleris@arm.com if (blk == nullptr) { 39511051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 39611051Sandreas.hansson@arm.com incMissCount(pkt); 39711051Sandreas.hansson@arm.com return false; 39811051Sandreas.hansson@arm.com } 39911051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 40011051Sandreas.hansson@arm.com 40111051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 40211051Sandreas.hansson@arm.com if (pkt->isSecure()) { 40311051Sandreas.hansson@arm.com blk->status |= BlkSecure; 40411051Sandreas.hansson@arm.com } 40511051Sandreas.hansson@arm.com } 40611199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 40711199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 40811199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 40911199Sandreas.hansson@arm.com blk->status |= BlkDirty; 41011199Sandreas.hansson@arm.com } 41111284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 41211284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 41311284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 41411284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 41511051Sandreas.hansson@arm.com blk->status |= BlkWritable; 41611051Sandreas.hansson@arm.com } 41711051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 41811051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 41911051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 42011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 42111051Sandreas.hansson@arm.com incHitCount(pkt); 42211051Sandreas.hansson@arm.com return true; 42311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 42411484Snikos.nikoleris@arm.com if (blk != nullptr) { 42511051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 42611051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 42711051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 42811051Sandreas.hansson@arm.com // it. 42911051Sandreas.hansson@arm.com return true; 43011051Sandreas.hansson@arm.com } 43111051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 43211051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 43311051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 43411051Sandreas.hansson@arm.com // go to next level. 43511051Sandreas.hansson@arm.com return false; 43611484Snikos.nikoleris@arm.com } else if ((blk != nullptr) && 43711483Snikos.nikoleris@arm.com (pkt->needsWritable() ? blk->isWritable() : 43811483Snikos.nikoleris@arm.com blk->isReadable())) { 43911051Sandreas.hansson@arm.com // OK to satisfy access 44011051Sandreas.hansson@arm.com incHitCount(pkt); 44111051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 44211051Sandreas.hansson@arm.com return true; 44311051Sandreas.hansson@arm.com } 44411051Sandreas.hansson@arm.com 44511484Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 44611284Sandreas.hansson@arm.com // or have block but need writable 44711051Sandreas.hansson@arm.com 44811051Sandreas.hansson@arm.com incMissCount(pkt); 44911051Sandreas.hansson@arm.com 45011484Snikos.nikoleris@arm.com if (blk == nullptr && pkt->isLLSC() && pkt->isWrite()) { 45111051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 45211051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 45311051Sandreas.hansson@arm.com return true; 45411051Sandreas.hansson@arm.com } 45511051Sandreas.hansson@arm.com 45611051Sandreas.hansson@arm.com return false; 45711051Sandreas.hansson@arm.com} 45811051Sandreas.hansson@arm.com 45911051Sandreas.hansson@arm.comvoid 46011051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 46111051Sandreas.hansson@arm.com{ 46211051Sandreas.hansson@arm.com while (!writebacks.empty()) { 46311051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 46411051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 46511051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 46611051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 46711051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 46811051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 46911051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 47011051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 47111051Sandreas.hansson@arm.com // packet destructor will delete the request object because 47211051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 47311051Sandreas.hansson@arm.com // response. 47411051Sandreas.hansson@arm.com delete wbPkt; 47511199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 47611199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 47711199Sandreas.hansson@arm.com // still cached above 47811199Sandreas.hansson@arm.com assert(writebackClean); 47911199Sandreas.hansson@arm.com delete wbPkt; 48011051Sandreas.hansson@arm.com } else { 48111199Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty); 48211051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 48311051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 48411051Sandreas.hansson@arm.com // address in the snoop filter below. 48511051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 48611051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 48711051Sandreas.hansson@arm.com } 48811051Sandreas.hansson@arm.com } else { 48911051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 49011051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 49111051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 49211051Sandreas.hansson@arm.com // below. 49311051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 49411051Sandreas.hansson@arm.com } 49511051Sandreas.hansson@arm.com writebacks.pop_front(); 49611051Sandreas.hansson@arm.com } 49711051Sandreas.hansson@arm.com} 49811051Sandreas.hansson@arm.com 49911130Sali.jafri@arm.comvoid 50011130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 50111130Sali.jafri@arm.com{ 50211130Sali.jafri@arm.com while (!writebacks.empty()) { 50311130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 50411130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 50511130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 50611130Sali.jafri@arm.com // and discard CleanEvicts. 50711130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 50811199Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty) { 50911130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 51011130Sali.jafri@arm.com // so that the Writeback does not reset the bit 51111130Sali.jafri@arm.com // corresponding to this address in the snoop filter 51211130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 51311130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 51411130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 51511130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 51611130Sali.jafri@arm.com } 51711130Sali.jafri@arm.com } else { 51811130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 51911130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 52011130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 52111130Sali.jafri@arm.com // below. 52211130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 52311130Sali.jafri@arm.com } 52411130Sali.jafri@arm.com writebacks.pop_front(); 52511130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 52611130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 52711130Sali.jafri@arm.com // does not require a response. 52811130Sali.jafri@arm.com delete wbPkt; 52911130Sali.jafri@arm.com } 53011130Sali.jafri@arm.com} 53111130Sali.jafri@arm.com 53211051Sandreas.hansson@arm.com 53311051Sandreas.hansson@arm.comvoid 53411051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 53511051Sandreas.hansson@arm.com{ 53611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 53711051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 53811051Sandreas.hansson@arm.com 53911051Sandreas.hansson@arm.com assert(pkt->isResponse()); 54011051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 54111051Sandreas.hansson@arm.com 54211276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 54311276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 54411276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 54511276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 54611276Sandreas.hansson@arm.com outstandingSnoop.end(); 54711276Sandreas.hansson@arm.com 54811276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 54911276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 55011276Sandreas.hansson@arm.com // forward it 55111051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 55211276Sandreas.hansson@arm.com 55311276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 55411276Sandreas.hansson@arm.com 55511276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 55611276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 55711051Sandreas.hansson@arm.com recvTimingResp(pkt); 55811051Sandreas.hansson@arm.com return; 55911051Sandreas.hansson@arm.com } 56011051Sandreas.hansson@arm.com 56111051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 56211051Sandreas.hansson@arm.com // upper level cache. 56311051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 56411051Sandreas.hansson@arm.com // we charge also headerDelay. 56511051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 56611051Sandreas.hansson@arm.com // Reset the timing of the packet. 56711051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 56811051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 56911051Sandreas.hansson@arm.com} 57011051Sandreas.hansson@arm.com 57111051Sandreas.hansson@arm.comvoid 57211051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 57311051Sandreas.hansson@arm.com{ 57411051Sandreas.hansson@arm.com // Cache line clearing instructions 57511051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 57611051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 57711051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 57811051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 57911051Sandreas.hansson@arm.com } 58011051Sandreas.hansson@arm.com} 58111051Sandreas.hansson@arm.com 58211051Sandreas.hansson@arm.combool 58311051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 58411051Sandreas.hansson@arm.com{ 58511051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 58611051Sandreas.hansson@arm.com 58711051Sandreas.hansson@arm.com assert(pkt->isRequest()); 58811051Sandreas.hansson@arm.com 58911051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 59011051Sandreas.hansson@arm.com if (system->bypassCaches()) { 59111051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 59211051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 59311051Sandreas.hansson@arm.com assert(success); 59411051Sandreas.hansson@arm.com return true; 59511051Sandreas.hansson@arm.com } 59611051Sandreas.hansson@arm.com 59711051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 59811051Sandreas.hansson@arm.com 59911284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 60011051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 60111284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 60211284Sandreas.hansson@arm.com // in Modified or Owned state 60311284Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %#llx (%s): " 60411284Sandreas.hansson@arm.com "not responding\n", 60511051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 60611051Sandreas.hansson@arm.com 60711284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 60811284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 60911284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 61011284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 61111284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 61211334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 61311284Sandreas.hansson@arm.com 61411334Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 61511334Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 61611334Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 61711334Sandreas.hansson@arm.com // cache hierarchy to another 61811284Sandreas.hansson@arm.com 61911334Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 62011334Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 62111334Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 62211334Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 62311334Sandreas.hansson@arm.com // block in the current cache or any other cache on the 62411334Sandreas.hansson@arm.com // path to memory 62511051Sandreas.hansson@arm.com 62611334Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 62711334Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 62811334Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 62911334Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 63011051Sandreas.hansson@arm.com 63111334Sandreas.hansson@arm.com // also reset the bus time that the original packet has 63211334Sandreas.hansson@arm.com // not yet paid for 63311334Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 63411051Sandreas.hansson@arm.com 63511334Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 63611334Sandreas.hansson@arm.com // other caches in the system know that the another cache 63711334Sandreas.hansson@arm.com // is responding, because we have found the authorative 63811334Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 63911334Sandreas.hansson@arm.com // data 64011334Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 64111334Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 64211051Sandreas.hansson@arm.com 64311334Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 64411334Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 64511334Sandreas.hansson@arm.com // every cache in the system 64611334Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 64711334Sandreas.hansson@arm.com // express snoops always succeed 64811334Sandreas.hansson@arm.com assert(success); 64911334Sandreas.hansson@arm.com 65011334Sandreas.hansson@arm.com // main memory will delete the snoop packet 65111051Sandreas.hansson@arm.com 65211284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 65311284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 65411190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 65511051Sandreas.hansson@arm.com 65611334Sandreas.hansson@arm.com // no need to take any further action in this particular cache 65711334Sandreas.hansson@arm.com // as an upstram cache has already committed to responding, 65811334Sandreas.hansson@arm.com // and we have already sent out any express snoops in the 65911334Sandreas.hansson@arm.com // section above to ensure all other copies in the system are 66011334Sandreas.hansson@arm.com // invalidated 66111051Sandreas.hansson@arm.com return true; 66211051Sandreas.hansson@arm.com } 66311051Sandreas.hansson@arm.com 66411051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 66511051Sandreas.hansson@arm.com // the delay provided by the crossbar 66611051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 66711051Sandreas.hansson@arm.com 66811051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 66911051Sandreas.hansson@arm.com // to access. 67011051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 67111484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 67211051Sandreas.hansson@arm.com bool satisfied = false; 67311051Sandreas.hansson@arm.com { 67411051Sandreas.hansson@arm.com PacketList writebacks; 67511051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 67611051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 67711051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 67811051Sandreas.hansson@arm.com 67911051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 68011051Sandreas.hansson@arm.com // proceed anything happening below 68111051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 68211051Sandreas.hansson@arm.com } 68311051Sandreas.hansson@arm.com 68411051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 68511051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 68611051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 68711051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 68811051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 68911051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 69011051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 69111051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 69211051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 69311051Sandreas.hansson@arm.com 69411051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 69511051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 69611051Sandreas.hansson@arm.com 69711051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 69811051Sandreas.hansson@arm.com 69911051Sandreas.hansson@arm.com if (satisfied) { 70011051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 70111051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 70211051Sandreas.hansson@arm.com // lookup 70311051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 70411051Sandreas.hansson@arm.com 70511051Sandreas.hansson@arm.com // hit (for all other request types) 70611051Sandreas.hansson@arm.com 70711483Snikos.nikoleris@arm.com if (prefetcher && (prefetchOnAccess || 70811483Snikos.nikoleris@arm.com (blk && blk->wasPrefetched()))) { 70911051Sandreas.hansson@arm.com if (blk) 71011051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 71111051Sandreas.hansson@arm.com 71211051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 71311051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 71411051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 71511051Sandreas.hansson@arm.com } 71611051Sandreas.hansson@arm.com 71711051Sandreas.hansson@arm.com if (needsResponse) { 71811051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 71911051Sandreas.hansson@arm.com // @todo: Make someone pay for this 72011051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 72111051Sandreas.hansson@arm.com 72211051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 72311051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 72411051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 72511051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 72611051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 72711194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 72811051Sandreas.hansson@arm.com } else { 72911199Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n", 73011558Snikos.nikoleris@arm.com __func__, pkt->cmdString(), pkt->getAddr()); 73111199Sandreas.hansson@arm.com 73211190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 73311190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 73411190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 73511190Sandreas.hansson@arm.com // here as well 73611190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 73711051Sandreas.hansson@arm.com } 73811051Sandreas.hansson@arm.com } else { 73911051Sandreas.hansson@arm.com // miss 74011051Sandreas.hansson@arm.com 74111051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 74211051Sandreas.hansson@arm.com 74311051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 74411051Sandreas.hansson@arm.com // uncacheable request 74511051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 74611051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 74711051Sandreas.hansson@arm.com 74811051Sandreas.hansson@arm.com // Software prefetch handling: 74911051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 75011051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 75111051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 75211051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 75311051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 75411051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 75511051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 75611051Sandreas.hansson@arm.com // into the MSHRs, not the original. 75711051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 75811051Sandreas.hansson@arm.com assert(needsResponse); 75911051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 76011051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 76111051Sandreas.hansson@arm.com 76211051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 76311051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 76411051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 76511051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 76611051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 76711051Sandreas.hansson@arm.com 76811051Sandreas.hansson@arm.com if (!mshr) { 76911051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 77011051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 77111051Sandreas.hansson@arm.com pkt->req->getSize(), 77211051Sandreas.hansson@arm.com pkt->req->getFlags(), 77311051Sandreas.hansson@arm.com pkt->req->masterId()); 77411051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 77511051Sandreas.hansson@arm.com pf->allocate(); 77611051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 77711051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 77811051Sandreas.hansson@arm.com } 77911051Sandreas.hansson@arm.com 78011051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 78111286Sandreas.hansson@arm.com 78211051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 78311051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 78411194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 78511051Sandreas.hansson@arm.com 78611051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 78711051Sandreas.hansson@arm.com // MSHR) this is set to null 78811051Sandreas.hansson@arm.com pkt = pf; 78911051Sandreas.hansson@arm.com } 79011051Sandreas.hansson@arm.com 79111051Sandreas.hansson@arm.com if (mshr) { 79211051Sandreas.hansson@arm.com /// MSHR hit 79311051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 79411051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 79511051Sandreas.hansson@arm.com 79611051Sandreas.hansson@arm.com //@todo remove hw_pf here 79711051Sandreas.hansson@arm.com 79811051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 79911051Sandreas.hansson@arm.com if (pkt) { 80011199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 80111199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 80211199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 80311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 80411190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 80511051Sandreas.hansson@arm.com } else { 80611483Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx " 80711483Snikos.nikoleris@arm.com "size %d\n", __func__, pkt->cmdString(), 80811483Snikos.nikoleris@arm.com pkt->getAddr(), pkt->getSize()); 80911051Sandreas.hansson@arm.com 81011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 81111051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 81211051Sandreas.hansson@arm.com // We use forward_time here because it is the same 81311051Sandreas.hansson@arm.com // considering new targets. We have multiple 81411051Sandreas.hansson@arm.com // requests for the same address here. It 81511051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 81611051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 81711051Sandreas.hansson@arm.com // port and also takes into account the additional 81811051Sandreas.hansson@arm.com // delay of the xbar. 81911197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 82011197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 82111051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 82211051Sandreas.hansson@arm.com noTargetMSHR = mshr; 82311051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 82411051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 82511051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 82611051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 82711051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 82811051Sandreas.hansson@arm.com } 82911051Sandreas.hansson@arm.com } 83011051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 83111483Snikos.nikoleris@arm.com // satisfied or not, reguardless if the request is in the MSHR 83211483Snikos.nikoleris@arm.com // or not. The request could be a ReadReq hit, but still not 83311051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 83411051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 83511483Snikos.nikoleris@arm.com // already allocated for this, we need to let the prefetcher 83611483Snikos.nikoleris@arm.com // know about the request 83711051Sandreas.hansson@arm.com if (prefetcher) { 83811051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 83911051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 84011051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 84111051Sandreas.hansson@arm.com } 84211051Sandreas.hansson@arm.com } 84311051Sandreas.hansson@arm.com } else { 84411051Sandreas.hansson@arm.com // no MSHR 84511051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 84611051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 84711051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 84811051Sandreas.hansson@arm.com } else { 84911051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 85011051Sandreas.hansson@arm.com } 85111051Sandreas.hansson@arm.com 85211199Sandreas.hansson@arm.com if (pkt->isEviction() || 85311051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 85411051Sandreas.hansson@arm.com // We use forward_time here because there is an 85511051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 85611051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 85711051Sandreas.hansson@arm.com } else { 85811051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 85911051Sandreas.hansson@arm.com // should have flushed and have no valid block 86011051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 86111051Sandreas.hansson@arm.com 86211051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 86311051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 86411051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 86511051Sandreas.hansson@arm.com // write miss, the read could return stale data 86611051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 86711051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 86811051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 86911051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 87011051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 87111051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 87211051Sandreas.hansson@arm.com // new data) when the write miss completes. 87311051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 87411051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 87511051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 87611051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 87711284Sandreas.hansson@arm.com assert(pkt->needsWritable()); 87811051Sandreas.hansson@arm.com assert(!blk->isWritable()); 87911051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 88011051Sandreas.hansson@arm.com } 88111051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 88211051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 88311051Sandreas.hansson@arm.com // lookupLatency component. 88411051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 88511051Sandreas.hansson@arm.com } 88611051Sandreas.hansson@arm.com 88711051Sandreas.hansson@arm.com if (prefetcher) { 88811051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 88911051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 89011051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 89111051Sandreas.hansson@arm.com } 89211051Sandreas.hansson@arm.com } 89311051Sandreas.hansson@arm.com } 89411051Sandreas.hansson@arm.com 89511051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 89611051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 89711051Sandreas.hansson@arm.com 89811051Sandreas.hansson@arm.com return true; 89911051Sandreas.hansson@arm.com} 90011051Sandreas.hansson@arm.com 90111051Sandreas.hansson@arm.comPacketPtr 90211452Sandreas.hansson@arm.comCache::createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, 90311452Sandreas.hansson@arm.com bool needsWritable) const 90411051Sandreas.hansson@arm.com{ 90511452Sandreas.hansson@arm.com // should never see evictions here 90611452Sandreas.hansson@arm.com assert(!cpu_pkt->isEviction()); 90711452Sandreas.hansson@arm.com 90811051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 90911051Sandreas.hansson@arm.com 91011452Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable() || 91111452Sandreas.hansson@arm.com (!blkValid && cpu_pkt->isUpgrade())) { 91211452Sandreas.hansson@arm.com // uncacheable requests and upgrades from upper-level caches 91311452Sandreas.hansson@arm.com // that missed completely just go through as is 91411452Sandreas.hansson@arm.com return nullptr; 91511051Sandreas.hansson@arm.com } 91611051Sandreas.hansson@arm.com 91711051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com MemCmd cmd; 92011051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 92111051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 92211051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 92311051Sandreas.hansson@arm.com // which will clobber the owned copy. 92411051Sandreas.hansson@arm.com const bool useUpgrades = true; 92511051Sandreas.hansson@arm.com if (blkValid && useUpgrades) { 92611284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 92711284Sandreas.hansson@arm.com // it to be writable 92811284Sandreas.hansson@arm.com assert(needsWritable); 92911051Sandreas.hansson@arm.com assert(!blk->isWritable()); 93011051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 93111051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 93211051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 93311051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 93411051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 93511051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 93611051Sandreas.hansson@arm.com // all caches not being on the same local bus. 93711051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 93811352Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::WriteLineReq || 93911352Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::InvalidateReq) { 94011051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 94111284Sandreas.hansson@arm.com // the line in Exclusive state, and invalidates all other 94211051Sandreas.hansson@arm.com // copies 94311051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 94411051Sandreas.hansson@arm.com } else { 94511051Sandreas.hansson@arm.com // block is invalid 94611284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 94711051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 94811051Sandreas.hansson@arm.com } 94911051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 95011051Sandreas.hansson@arm.com 95111284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 95211284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 95311284Sandreas.hansson@arm.com // downstream 95411284Sandreas.hansson@arm.com if (cpu_pkt->hasSharers()) { 95511051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 95611051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 95711051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 95811284Sandreas.hansson@arm.com // assuming the block has sharers 95911284Sandreas.hansson@arm.com pkt->setHasSharers(); 96011284Sandreas.hansson@arm.com DPRINTF(Cache, "%s passing hasSharers from %s to %s addr %#llx " 96111284Sandreas.hansson@arm.com "size %d\n", 96211051Sandreas.hansson@arm.com __func__, cpu_pkt->cmdString(), pkt->cmdString(), 96311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize()); 96411051Sandreas.hansson@arm.com } 96511051Sandreas.hansson@arm.com 96611051Sandreas.hansson@arm.com // the packet should be block aligned 96711051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 96811051Sandreas.hansson@arm.com 96911051Sandreas.hansson@arm.com pkt->allocate(); 97011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n", 97111051Sandreas.hansson@arm.com __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(), 97211051Sandreas.hansson@arm.com pkt->getSize()); 97311051Sandreas.hansson@arm.com return pkt; 97411051Sandreas.hansson@arm.com} 97511051Sandreas.hansson@arm.com 97611051Sandreas.hansson@arm.com 97711051Sandreas.hansson@arm.comTick 97811051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 97911051Sandreas.hansson@arm.com{ 98011051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 98111051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 98211051Sandreas.hansson@arm.com 98311051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 98411051Sandreas.hansson@arm.com if (system->bypassCaches()) 98511051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 98611051Sandreas.hansson@arm.com 98711051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 98811051Sandreas.hansson@arm.com 98911333Sandreas.hansson@arm.com // follow the same flow as in recvTimingReq, and check if a cache 99011333Sandreas.hansson@arm.com // above us is responding 99111284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 99211333Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %#llx (%s): " 99311333Sandreas.hansson@arm.com "not responding\n", 99411333Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 99511333Sandreas.hansson@arm.com 99611333Sandreas.hansson@arm.com // if a cache is responding, and it had the line in Owned 99711333Sandreas.hansson@arm.com // rather than Modified state, we need to invalidate any 99811333Sandreas.hansson@arm.com // copies that are not on the same path to memory 99911334Sandreas.hansson@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 100011334Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 100111051Sandreas.hansson@arm.com 100211051Sandreas.hansson@arm.com return lat * clockPeriod(); 100311051Sandreas.hansson@arm.com } 100411051Sandreas.hansson@arm.com 100511051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 100611051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 100711051Sandreas.hansson@arm.com // access in timing mode 100811051Sandreas.hansson@arm.com 100911484Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 101011051Sandreas.hansson@arm.com PacketList writebacks; 101111051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 101211051Sandreas.hansson@arm.com 101311051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 101411051Sandreas.hansson@arm.com // logically proceed anything happening below 101511130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 101611051Sandreas.hansson@arm.com 101711051Sandreas.hansson@arm.com if (!satisfied) { 101811051Sandreas.hansson@arm.com // MISS 101911051Sandreas.hansson@arm.com 102011452Sandreas.hansson@arm.com // deal with the packets that go through the write path of 102111452Sandreas.hansson@arm.com // the cache, i.e. any evictions and uncacheable writes 102211452Sandreas.hansson@arm.com if (pkt->isEviction() || 102311452Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 102411452Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 102511452Sandreas.hansson@arm.com return lat * clockPeriod(); 102611452Sandreas.hansson@arm.com } 102711452Sandreas.hansson@arm.com // only misses left 102811452Sandreas.hansson@arm.com 102911452Sandreas.hansson@arm.com PacketPtr bus_pkt = createMissPacket(pkt, blk, pkt->needsWritable()); 103011051Sandreas.hansson@arm.com 103111484Snikos.nikoleris@arm.com bool is_forward = (bus_pkt == nullptr); 103211051Sandreas.hansson@arm.com 103311051Sandreas.hansson@arm.com if (is_forward) { 103411051Sandreas.hansson@arm.com // just forwarding the same request to the next level 103511051Sandreas.hansson@arm.com // no local cache operation involved 103611051Sandreas.hansson@arm.com bus_pkt = pkt; 103711051Sandreas.hansson@arm.com } 103811051Sandreas.hansson@arm.com 103911051Sandreas.hansson@arm.com DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n", 104011051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 104111051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns"); 104211051Sandreas.hansson@arm.com 104311051Sandreas.hansson@arm.com#if TRACING_ON 104411051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 104511051Sandreas.hansson@arm.com#endif 104611051Sandreas.hansson@arm.com 104711051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 104811051Sandreas.hansson@arm.com 104911452Sandreas.hansson@arm.com bool is_invalidate = bus_pkt->isInvalidate(); 105011452Sandreas.hansson@arm.com 105111051Sandreas.hansson@arm.com // We are now dealing with the response handling 105211483Snikos.nikoleris@arm.com DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in " 105311483Snikos.nikoleris@arm.com "state %i\n", bus_pkt->cmdString(), bus_pkt->getAddr(), 105411051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns", 105511051Sandreas.hansson@arm.com old_state); 105611051Sandreas.hansson@arm.com 105711051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 105811051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 105911051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 106011051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 106111051Sandreas.hansson@arm.com if (!is_forward) { 106211051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 106311051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 106411051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 106511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 106611051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 106711051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 106811051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 106911051Sandreas.hansson@arm.com 107011051Sandreas.hansson@arm.com // write-line request to the cache that promoted 107111051Sandreas.hansson@arm.com // the write to a whole line 107211197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 107311197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 107411452Sandreas.hansson@arm.com assert(blk != NULL); 107511452Sandreas.hansson@arm.com is_invalidate = false; 107611051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 107711051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 107811051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 107911051Sandreas.hansson@arm.com // we're updating cache state to allow us to 108011051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 108111197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 108211197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 108311051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 108411051Sandreas.hansson@arm.com } else { 108511051Sandreas.hansson@arm.com // we're satisfying the upstream request without 108611051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 108711051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 108811051Sandreas.hansson@arm.com } 108911051Sandreas.hansson@arm.com } 109011051Sandreas.hansson@arm.com delete bus_pkt; 109111051Sandreas.hansson@arm.com } 109211452Sandreas.hansson@arm.com 109311452Sandreas.hansson@arm.com if (is_invalidate && blk && blk->isValid()) { 109411452Sandreas.hansson@arm.com invalidateBlock(blk); 109511452Sandreas.hansson@arm.com } 109611051Sandreas.hansson@arm.com } 109711051Sandreas.hansson@arm.com 109811051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 109911051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 110011051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 110111051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 110211051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 110311051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 110411051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 110511051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 110611051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 110711051Sandreas.hansson@arm.com // there). 110811051Sandreas.hansson@arm.com 110911197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 111011130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 111111051Sandreas.hansson@arm.com 111211197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 111311197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 111411197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 111511197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 111611197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 111711197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 111811197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 111911197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 112011197Sandreas.hansson@arm.com if (tempBlockWriteback) { 112111197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 112211197Sandreas.hansson@arm.com // do not schedule any new event 112311197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 112411197Sandreas.hansson@arm.com } else { 112511197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 112611197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 112711197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 112811197Sandreas.hansson@arm.com // allowed to happen first 112911197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 113011197Sandreas.hansson@arm.com } 113111197Sandreas.hansson@arm.com 113211199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 113311199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 113411197Sandreas.hansson@arm.com blk->invalidate(); 113511197Sandreas.hansson@arm.com } 113611197Sandreas.hansson@arm.com 113711051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 113811051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 113911051Sandreas.hansson@arm.com } 114011051Sandreas.hansson@arm.com 114111051Sandreas.hansson@arm.com return lat * clockPeriod(); 114211051Sandreas.hansson@arm.com} 114311051Sandreas.hansson@arm.com 114411051Sandreas.hansson@arm.com 114511051Sandreas.hansson@arm.comvoid 114611051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 114711051Sandreas.hansson@arm.com{ 114811051Sandreas.hansson@arm.com if (system->bypassCaches()) { 114911051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 115011051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 115111051Sandreas.hansson@arm.com assert(fromCpuSide); 115211051Sandreas.hansson@arm.com 115311051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 115411051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 115511051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 115611051Sandreas.hansson@arm.com return; 115711051Sandreas.hansson@arm.com } 115811051Sandreas.hansson@arm.com 115911051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 116011051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 116111051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 116211051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 116311051Sandreas.hansson@arm.com 116411051Sandreas.hansson@arm.com pkt->pushLabel(name()); 116511051Sandreas.hansson@arm.com 116611051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 116711051Sandreas.hansson@arm.com 116811051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 116911051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 117011051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 117111051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 117211051Sandreas.hansson@arm.com 117311051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 117411051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 117511051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 117611051Sandreas.hansson@arm.com blk->data); 117711051Sandreas.hansson@arm.com 117811284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 117911284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 118011051Sandreas.hansson@arm.com bool have_dirty = 118111051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 118211284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 118311051Sandreas.hansson@arm.com 118411051Sandreas.hansson@arm.com bool done = have_dirty 118511051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 118611051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 118711051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 118811051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 118911051Sandreas.hansson@arm.com 119011288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "functional %s %#llx (%s) %s%s%s\n", 119111051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns", 119211051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 119311051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 119411051Sandreas.hansson@arm.com 119511051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 119611051Sandreas.hansson@arm.com pkt->popLabel(); 119711051Sandreas.hansson@arm.com 119811051Sandreas.hansson@arm.com if (done) { 119911051Sandreas.hansson@arm.com pkt->makeResponse(); 120011051Sandreas.hansson@arm.com } else { 120111051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 120211051Sandreas.hansson@arm.com // continues towards the memory side 120311051Sandreas.hansson@arm.com if (fromCpuSide) { 120411051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 120511485Snikos.nikoleris@arm.com } else if (cpuSidePort->isSnooping()) { 120611051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 120711051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 120811051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 120911051Sandreas.hansson@arm.com } 121011051Sandreas.hansson@arm.com } 121111051Sandreas.hansson@arm.com} 121211051Sandreas.hansson@arm.com 121311051Sandreas.hansson@arm.com 121411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 121511051Sandreas.hansson@arm.com// 121611051Sandreas.hansson@arm.com// Response handling: responses from the memory side 121711051Sandreas.hansson@arm.com// 121811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 121911051Sandreas.hansson@arm.com 122011051Sandreas.hansson@arm.com 122111051Sandreas.hansson@arm.comvoid 122211375Sandreas.hansson@arm.comCache::handleUncacheableWriteResp(PacketPtr pkt) 122311375Sandreas.hansson@arm.com{ 122411375Sandreas.hansson@arm.com Tick completion_time = clockEdge(responseLatency) + 122511375Sandreas.hansson@arm.com pkt->headerDelay + pkt->payloadDelay; 122611375Sandreas.hansson@arm.com 122711453Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 122811453Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 122911375Sandreas.hansson@arm.com 123011453Sandreas.hansson@arm.com cpuSidePort->schedTimingResp(pkt, completion_time, true); 123111375Sandreas.hansson@arm.com} 123211375Sandreas.hansson@arm.com 123311375Sandreas.hansson@arm.comvoid 123411051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 123511051Sandreas.hansson@arm.com{ 123611051Sandreas.hansson@arm.com assert(pkt->isResponse()); 123711051Sandreas.hansson@arm.com 123811051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 123911051Sandreas.hansson@arm.com // this is a prefetch response from above 124011051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 124111051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 124211051Sandreas.hansson@arm.com 124311051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 124411051Sandreas.hansson@arm.com 124511051Sandreas.hansson@arm.com if (is_error) { 124611051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), " 124711051Sandreas.hansson@arm.com "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", 124811051Sandreas.hansson@arm.com pkt->cmdString()); 124911051Sandreas.hansson@arm.com } 125011051Sandreas.hansson@arm.com 125111051Sandreas.hansson@arm.com DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n", 125211051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 125311051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 125411051Sandreas.hansson@arm.com 125511375Sandreas.hansson@arm.com // if this is a write, we should be looking at an uncacheable 125611375Sandreas.hansson@arm.com // write 125711375Sandreas.hansson@arm.com if (pkt->isWrite()) { 125811375Sandreas.hansson@arm.com assert(pkt->req->isUncacheable()); 125911375Sandreas.hansson@arm.com handleUncacheableWriteResp(pkt); 126011375Sandreas.hansson@arm.com return; 126111375Sandreas.hansson@arm.com } 126211375Sandreas.hansson@arm.com 126311375Sandreas.hansson@arm.com // we have dealt with any (uncacheable) writes above, from here on 126411375Sandreas.hansson@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 126511453Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 126611375Sandreas.hansson@arm.com assert(mshr); 126711051Sandreas.hansson@arm.com 126811051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 126911051Sandreas.hansson@arm.com // we always clear at least one target 127011051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 127111484Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 127211051Sandreas.hansson@arm.com } 127311051Sandreas.hansson@arm.com 127411051Sandreas.hansson@arm.com // Initial target is used just for stats 127511051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 127611051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 127711051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 127811051Sandreas.hansson@arm.com 127911051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 128011051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 128111051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 128211051Sandreas.hansson@arm.com miss_latency; 128311051Sandreas.hansson@arm.com } else { 128411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 128511051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 128611051Sandreas.hansson@arm.com miss_latency; 128711051Sandreas.hansson@arm.com } 128811051Sandreas.hansson@arm.com 128911375Sandreas.hansson@arm.com bool wasFull = mshrQueue.isFull(); 129011375Sandreas.hansson@arm.com 129111375Sandreas.hansson@arm.com PacketList writebacks; 129211375Sandreas.hansson@arm.com 129311375Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 129411375Sandreas.hansson@arm.com 129511284Sandreas.hansson@arm.com // upgrade deferred targets if the response has no sharers, and is 129611284Sandreas.hansson@arm.com // thus passing writable 129711284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 129811284Sandreas.hansson@arm.com mshr->promoteWritable(); 129911177Sandreas.hansson@arm.com } 130011177Sandreas.hansson@arm.com 130111051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 130211051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 130311051Sandreas.hansson@arm.com 130411177Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 130511177Sandreas.hansson@arm.com 130611051Sandreas.hansson@arm.com if (is_fill && !is_error) { 130711051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 130811051Sandreas.hansson@arm.com pkt->getAddr()); 130911051Sandreas.hansson@arm.com 131011197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill); 131111484Snikos.nikoleris@arm.com assert(blk != nullptr); 131211051Sandreas.hansson@arm.com } 131311051Sandreas.hansson@arm.com 131411051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 131511051Sandreas.hansson@arm.com // requests to be discarded 131611136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 131711051Sandreas.hansson@arm.com 131811051Sandreas.hansson@arm.com // First offset for critical word first calculations 131911051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 132011051Sandreas.hansson@arm.com 132111051Sandreas.hansson@arm.com while (mshr->hasTargets()) { 132211051Sandreas.hansson@arm.com MSHR::Target *target = mshr->getTarget(); 132311051Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 132411051Sandreas.hansson@arm.com 132511051Sandreas.hansson@arm.com switch (target->source) { 132611051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 132711051Sandreas.hansson@arm.com Tick completion_time; 132811051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 132911051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 133011051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 133111051Sandreas.hansson@arm.com 133211051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 133311051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 133411483Snikos.nikoleris@arm.com // a software prefetch would have already been ack'd 133511483Snikos.nikoleris@arm.com // immediately with dummy data so the core would be able to 133611483Snikos.nikoleris@arm.com // retire it. This request completes right here, so we 133711483Snikos.nikoleris@arm.com // deallocate it. 133811051Sandreas.hansson@arm.com delete tgt_pkt->req; 133911051Sandreas.hansson@arm.com delete tgt_pkt; 134011051Sandreas.hansson@arm.com break; // skip response 134111051Sandreas.hansson@arm.com } 134211051Sandreas.hansson@arm.com 134311051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 134411051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 134511051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 134611051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 134711051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 134811051Sandreas.hansson@arm.com // from above. 134911051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 135011051Sandreas.hansson@arm.com assert(!is_error); 135111284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 135211284Sandreas.hansson@arm.com // any deferred targets if possible 135311284Sandreas.hansson@arm.com mshr->promoteWritable(); 135411051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 135511197Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill); 135611484Snikos.nikoleris@arm.com assert(blk != nullptr); 135711051Sandreas.hansson@arm.com 135811051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 135911051Sandreas.hansson@arm.com // response 136011051Sandreas.hansson@arm.com is_fill = true; 136111136Sandreas.hansson@arm.com is_invalidate = false; 136211051Sandreas.hansson@arm.com } 136311051Sandreas.hansson@arm.com 136411051Sandreas.hansson@arm.com if (is_fill) { 136511051Sandreas.hansson@arm.com satisfyCpuSideRequest(tgt_pkt, blk, 136611051Sandreas.hansson@arm.com true, mshr->hasPostDowngrade()); 136711051Sandreas.hansson@arm.com 136811051Sandreas.hansson@arm.com // How many bytes past the first request is this one 136911051Sandreas.hansson@arm.com int transfer_offset = 137011051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 137111051Sandreas.hansson@arm.com if (transfer_offset < 0) { 137211051Sandreas.hansson@arm.com transfer_offset += blkSize; 137311051Sandreas.hansson@arm.com } 137411051Sandreas.hansson@arm.com 137511051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 137611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 137711051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 137811051Sandreas.hansson@arm.com // the core. 137911051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 138011051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 138111051Sandreas.hansson@arm.com 138211051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 138311051Sandreas.hansson@arm.com 138411051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 138511051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 138611051Sandreas.hansson@arm.com completion_time - target->recvTime; 138711051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 138811051Sandreas.hansson@arm.com // failed StoreCond upgrade 138911051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 139011051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 139111051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 139211051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 139311051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 139411051Sandreas.hansson@arm.com // the core. 139511051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 139611051Sandreas.hansson@arm.com pkt->payloadDelay; 139711051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 139811051Sandreas.hansson@arm.com } else { 139911051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 140011051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 140111051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 140211051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 140311051Sandreas.hansson@arm.com pkt->payloadDelay; 140411051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 140511051Sandreas.hansson@arm.com // sanity check 140611051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 140711051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 140811051Sandreas.hansson@arm.com 140911051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 141011051Sandreas.hansson@arm.com } 141111051Sandreas.hansson@arm.com } 141211051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 141311051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 141411051Sandreas.hansson@arm.com if (is_error) 141511051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 141611051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 141711136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 141811051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 141911051Sandreas.hansson@arm.com // propagate that. Response should not have 142011051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 142111051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 142211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n", 142311051Sandreas.hansson@arm.com __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr()); 142411051Sandreas.hansson@arm.com } 142511051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 142611051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 142711194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 142811051Sandreas.hansson@arm.com break; 142911051Sandreas.hansson@arm.com 143011051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 143111051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 143211051Sandreas.hansson@arm.com if (blk) 143311051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 143411051Sandreas.hansson@arm.com delete tgt_pkt->req; 143511051Sandreas.hansson@arm.com delete tgt_pkt; 143611051Sandreas.hansson@arm.com break; 143711051Sandreas.hansson@arm.com 143811051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 143911051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 144011051Sandreas.hansson@arm.com assert(!is_error); 144111051Sandreas.hansson@arm.com // response to snoop request 144211051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 144311136Sandreas.hansson@arm.com assert(!(is_invalidate && !mshr->hasPostInvalidate())); 144411051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 144511051Sandreas.hansson@arm.com break; 144611051Sandreas.hansson@arm.com 144711051Sandreas.hansson@arm.com default: 144811051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target->source); 144911051Sandreas.hansson@arm.com } 145011051Sandreas.hansson@arm.com 145111051Sandreas.hansson@arm.com mshr->popTarget(); 145211051Sandreas.hansson@arm.com } 145311051Sandreas.hansson@arm.com 145411051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 145511051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 145611051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 145711051Sandreas.hansson@arm.com // invalidation should be discarded 145811136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 145911197Sandreas.hansson@arm.com invalidateBlock(blk); 146011051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 146111051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 146211051Sandreas.hansson@arm.com } 146311051Sandreas.hansson@arm.com } 146411051Sandreas.hansson@arm.com 146511051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 146611051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 146711051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 146811051Sandreas.hansson@arm.com if (blk) { 146911051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 147011051Sandreas.hansson@arm.com } 147111375Sandreas.hansson@arm.com mshrQueue.markPending(mshr); 147211051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 147311051Sandreas.hansson@arm.com } else { 147411375Sandreas.hansson@arm.com mshrQueue.deallocate(mshr); 147511375Sandreas.hansson@arm.com if (wasFull && !mshrQueue.isFull()) { 147611375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 147711051Sandreas.hansson@arm.com } 147811051Sandreas.hansson@arm.com 147911051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 148011051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 148111375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 148211051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 148311051Sandreas.hansson@arm.com clockEdge()); 148411051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 148511051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 148611051Sandreas.hansson@arm.com } 148711051Sandreas.hansson@arm.com } 148811051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 148911051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 149011051Sandreas.hansson@arm.com 149111051Sandreas.hansson@arm.com // copy writebacks to write buffer 149211051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 149311051Sandreas.hansson@arm.com 149411051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 149511051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 149611051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 149711051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 149811051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 149911051Sandreas.hansson@arm.com // queued port. 150011199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 150111051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 150211051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 150311051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 150411051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 150511051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 150611051Sandreas.hansson@arm.com } else { 150711051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 150811051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 150911051Sandreas.hansson@arm.com // write buffer 151011051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 151111051Sandreas.hansson@arm.com delete wcPkt; 151211051Sandreas.hansson@arm.com else 151311051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 151411051Sandreas.hansson@arm.com } 151511051Sandreas.hansson@arm.com blk->invalidate(); 151611051Sandreas.hansson@arm.com } 151711051Sandreas.hansson@arm.com 151811288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "Leaving %s with %s for addr %#llx\n", __func__, 151911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 152011051Sandreas.hansson@arm.com delete pkt; 152111051Sandreas.hansson@arm.com} 152211051Sandreas.hansson@arm.com 152311051Sandreas.hansson@arm.comPacketPtr 152411051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 152511051Sandreas.hansson@arm.com{ 152611199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 152711199Sandreas.hansson@arm.com "Writeback from read-only cache"); 152811199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 152911051Sandreas.hansson@arm.com 153011051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 153111051Sandreas.hansson@arm.com 153211199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 153311199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 153411051Sandreas.hansson@arm.com if (blk->isSecure()) 153511199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 153611051Sandreas.hansson@arm.com 153711199Sandreas.hansson@arm.com req->taskId(blk->task_id); 153811051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 153911051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 154011051Sandreas.hansson@arm.com 154111199Sandreas.hansson@arm.com PacketPtr pkt = 154211199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 154311199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 154411199Sandreas.hansson@arm.com 154511199Sandreas.hansson@arm.com DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n", 154611199Sandreas.hansson@arm.com pkt->getAddr(), blk->isWritable(), blk->isDirty()); 154711199Sandreas.hansson@arm.com 154811051Sandreas.hansson@arm.com if (blk->isWritable()) { 154911051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 155011051Sandreas.hansson@arm.com // state, mark our own block non-writeable 155111051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 155211051Sandreas.hansson@arm.com } else { 155311284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 155411284Sandreas.hansson@arm.com pkt->setHasSharers(); 155511051Sandreas.hansson@arm.com } 155611051Sandreas.hansson@arm.com 155711199Sandreas.hansson@arm.com // make sure the block is not marked dirty 155811199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 155911051Sandreas.hansson@arm.com 156011199Sandreas.hansson@arm.com pkt->allocate(); 156111199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 156211199Sandreas.hansson@arm.com 156311199Sandreas.hansson@arm.com return pkt; 156411051Sandreas.hansson@arm.com} 156511051Sandreas.hansson@arm.com 156611051Sandreas.hansson@arm.comPacketPtr 156711051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 156811051Sandreas.hansson@arm.com{ 156911199Sandreas.hansson@arm.com assert(!writebackClean); 157011051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 157111051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 157211051Sandreas.hansson@arm.com Request *req = 157311051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 157411051Sandreas.hansson@arm.com Request::wbMasterId); 157511051Sandreas.hansson@arm.com if (blk->isSecure()) 157611051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 157711051Sandreas.hansson@arm.com 157811051Sandreas.hansson@arm.com req->taskId(blk->task_id); 157911051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 158011051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 158111051Sandreas.hansson@arm.com 158211051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 158311051Sandreas.hansson@arm.com pkt->allocate(); 158411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(), 158511051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 158611051Sandreas.hansson@arm.com pkt->getAddr()); 158711051Sandreas.hansson@arm.com 158811051Sandreas.hansson@arm.com return pkt; 158911051Sandreas.hansson@arm.com} 159011051Sandreas.hansson@arm.com 159111051Sandreas.hansson@arm.comvoid 159211051Sandreas.hansson@arm.comCache::memWriteback() 159311051Sandreas.hansson@arm.com{ 159411051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 159511051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 159611051Sandreas.hansson@arm.com} 159711051Sandreas.hansson@arm.com 159811051Sandreas.hansson@arm.comvoid 159911051Sandreas.hansson@arm.comCache::memInvalidate() 160011051Sandreas.hansson@arm.com{ 160111051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 160211051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 160311051Sandreas.hansson@arm.com} 160411051Sandreas.hansson@arm.com 160511051Sandreas.hansson@arm.combool 160611051Sandreas.hansson@arm.comCache::isDirty() const 160711051Sandreas.hansson@arm.com{ 160811051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 160911051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 161011051Sandreas.hansson@arm.com 161111051Sandreas.hansson@arm.com return visitor.isDirty(); 161211051Sandreas.hansson@arm.com} 161311051Sandreas.hansson@arm.com 161411051Sandreas.hansson@arm.combool 161511051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 161611051Sandreas.hansson@arm.com{ 161711051Sandreas.hansson@arm.com if (blk.isDirty()) { 161811051Sandreas.hansson@arm.com assert(blk.isValid()); 161911051Sandreas.hansson@arm.com 162011051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 162111051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 162211051Sandreas.hansson@arm.com request.taskId(blk.task_id); 162311051Sandreas.hansson@arm.com 162411051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 162511051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 162611051Sandreas.hansson@arm.com 162711051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 162811051Sandreas.hansson@arm.com 162911051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 163011051Sandreas.hansson@arm.com } 163111051Sandreas.hansson@arm.com 163211051Sandreas.hansson@arm.com return true; 163311051Sandreas.hansson@arm.com} 163411051Sandreas.hansson@arm.com 163511051Sandreas.hansson@arm.combool 163611051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 163711051Sandreas.hansson@arm.com{ 163811051Sandreas.hansson@arm.com 163911051Sandreas.hansson@arm.com if (blk.isDirty()) 164011051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 164111051Sandreas.hansson@arm.com 164211051Sandreas.hansson@arm.com if (blk.isValid()) { 164311051Sandreas.hansson@arm.com assert(!blk.isDirty()); 164411051Sandreas.hansson@arm.com tags->invalidate(&blk); 164511051Sandreas.hansson@arm.com blk.invalidate(); 164611051Sandreas.hansson@arm.com } 164711051Sandreas.hansson@arm.com 164811051Sandreas.hansson@arm.com return true; 164911051Sandreas.hansson@arm.com} 165011051Sandreas.hansson@arm.com 165111051Sandreas.hansson@arm.comCacheBlk* 165211051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 165311051Sandreas.hansson@arm.com{ 165411051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 165511051Sandreas.hansson@arm.com 165611484Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 165711051Sandreas.hansson@arm.com if (!blk) 165811051Sandreas.hansson@arm.com return nullptr; 165911051Sandreas.hansson@arm.com 166011051Sandreas.hansson@arm.com if (blk->isValid()) { 166111051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 166211051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 166311051Sandreas.hansson@arm.com if (repl_mshr) { 166411051Sandreas.hansson@arm.com // must be an outstanding upgrade request 166511051Sandreas.hansson@arm.com // on a block we're about to replace... 166611051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 166711284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 166811051Sandreas.hansson@arm.com // too hard to replace block with transient state 166911051Sandreas.hansson@arm.com // allocation failed, block not inserted 167011484Snikos.nikoleris@arm.com return nullptr; 167111051Sandreas.hansson@arm.com } else { 167211483Snikos.nikoleris@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 167311483Snikos.nikoleris@arm.com "(%s): %s\n", repl_addr, blk->isSecure() ? "s" : "ns", 167411051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 167511051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 167611051Sandreas.hansson@arm.com 167711436SRekai.GonzalezAlberquilla@arm.com if (blk->wasPrefetched()) { 167811436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches++; 167911436SRekai.GonzalezAlberquilla@arm.com } 168011051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 168111051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 168211199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 168311051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 168411051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 168511051Sandreas.hansson@arm.com } else { 168611051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 168711051Sandreas.hansson@arm.com } 168811051Sandreas.hansson@arm.com } 168911051Sandreas.hansson@arm.com } 169011051Sandreas.hansson@arm.com 169111051Sandreas.hansson@arm.com return blk; 169211051Sandreas.hansson@arm.com} 169311051Sandreas.hansson@arm.com 169411197Sandreas.hansson@arm.comvoid 169511197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 169611197Sandreas.hansson@arm.com{ 169711197Sandreas.hansson@arm.com if (blk != tempBlock) 169811197Sandreas.hansson@arm.com tags->invalidate(blk); 169911197Sandreas.hansson@arm.com blk->invalidate(); 170011197Sandreas.hansson@arm.com} 170111051Sandreas.hansson@arm.com 170211051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 170311051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 170411051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 170511051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 170611051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 170711051Sandreas.hansson@arm.comCacheBlk* 170811197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 170911197Sandreas.hansson@arm.com bool allocate) 171011051Sandreas.hansson@arm.com{ 171111051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 171211051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 171311051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 171411051Sandreas.hansson@arm.com#if TRACING_ON 171511051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 171611051Sandreas.hansson@arm.com#endif 171711051Sandreas.hansson@arm.com 171811375Sandreas.hansson@arm.com // When handling a fill, we should have no writes to this line. 171911375Sandreas.hansson@arm.com assert(addr == blockAlign(addr)); 172011375Sandreas.hansson@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 172111051Sandreas.hansson@arm.com 172211484Snikos.nikoleris@arm.com if (blk == nullptr) { 172311051Sandreas.hansson@arm.com // better have read new data... 172411051Sandreas.hansson@arm.com assert(pkt->hasData()); 172511051Sandreas.hansson@arm.com 172611051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 172711051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 172811051Sandreas.hansson@arm.com // happens in the subsequent satisfyCpuSideRequest. 172911051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 173011051Sandreas.hansson@arm.com 173111197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 173211197Sandreas.hansson@arm.com // with the temporary storage 173311484Snikos.nikoleris@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : nullptr; 173411197Sandreas.hansson@arm.com 173511484Snikos.nikoleris@arm.com if (blk == nullptr) { 173611197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 173711197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 173811197Sandreas.hansson@arm.com // current request and then get rid of it 173911051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 174011051Sandreas.hansson@arm.com blk = tempBlock; 174111051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 174211051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 174311051Sandreas.hansson@arm.com // @todo: set security state as well... 174411051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 174511051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 174611051Sandreas.hansson@arm.com } else { 174711051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 174811051Sandreas.hansson@arm.com } 174911051Sandreas.hansson@arm.com 175011051Sandreas.hansson@arm.com // we should never be overwriting a valid block 175111051Sandreas.hansson@arm.com assert(!blk->isValid()); 175211051Sandreas.hansson@arm.com } else { 175311051Sandreas.hansson@arm.com // existing block... probably an upgrade 175411051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 175511051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 175611051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 175711051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 175811051Sandreas.hansson@arm.com // don't want to lose that 175911051Sandreas.hansson@arm.com } 176011051Sandreas.hansson@arm.com 176111051Sandreas.hansson@arm.com if (is_secure) 176211051Sandreas.hansson@arm.com blk->status |= BlkSecure; 176311051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 176411051Sandreas.hansson@arm.com 176511137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 176611137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 176711137Sandreas.hansson@arm.com // dirty as part of satisfyCpuSideRequest 176811137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 176911284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 177011137Sandreas.hansson@arm.com // at the moment other caches do not respond to the 177111137Sandreas.hansson@arm.com // invalidation requests corresponding to a whole-line write 177211284Sandreas.hansson@arm.com assert(!pkt->cacheResponding()); 177311137Sandreas.hansson@arm.com } 177411137Sandreas.hansson@arm.com 177511284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 177611284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 177711284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 177811284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 177911284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 178011284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 178111284Sandreas.hansson@arm.com // for more details 178211284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 178311284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 178411284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 178511284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 178611051Sandreas.hansson@arm.com blk->status |= BlkWritable; 178711051Sandreas.hansson@arm.com 178811284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 178911284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 179011284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 179111284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 179211284Sandreas.hansson@arm.com // owners copy 179311051Sandreas.hansson@arm.com blk->status |= BlkDirty; 179411051Sandreas.hansson@arm.com 179511051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 179611051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 179711051Sandreas.hansson@arm.com } 179811051Sandreas.hansson@arm.com } 179911051Sandreas.hansson@arm.com 180011051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 180111051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 180211051Sandreas.hansson@arm.com 180311051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 180411051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 180511051Sandreas.hansson@arm.com if (pkt->isRead()) { 180611051Sandreas.hansson@arm.com // sanity checks 180711051Sandreas.hansson@arm.com assert(pkt->hasData()); 180811051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 180911051Sandreas.hansson@arm.com 181011051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 181111051Sandreas.hansson@arm.com } 181211051Sandreas.hansson@arm.com // We pay for fillLatency here. 181311051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 181411051Sandreas.hansson@arm.com pkt->payloadDelay; 181511051Sandreas.hansson@arm.com 181611051Sandreas.hansson@arm.com return blk; 181711051Sandreas.hansson@arm.com} 181811051Sandreas.hansson@arm.com 181911051Sandreas.hansson@arm.com 182011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 182111051Sandreas.hansson@arm.com// 182211051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 182311051Sandreas.hansson@arm.com// 182411051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 182511051Sandreas.hansson@arm.com 182611051Sandreas.hansson@arm.comvoid 182711051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 182811051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 182911051Sandreas.hansson@arm.com{ 183011051Sandreas.hansson@arm.com // sanity check 183111051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 183211051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 183311051Sandreas.hansson@arm.com 183411051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 183511051Sandreas.hansson@arm.com req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize()); 183611051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 183711051Sandreas.hansson@arm.com // already made a copy... 183811051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 183911051Sandreas.hansson@arm.com if (!already_copied) 184011051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 184111051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 184211051Sandreas.hansson@arm.com // responses) 184311051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 184411051Sandreas.hansson@arm.com 184511051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 184611284Sandreas.hansson@arm.com pkt->hasSharers()); 184711051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 184811051Sandreas.hansson@arm.com if (pkt->isRead()) { 184911051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 185011051Sandreas.hansson@arm.com } 185111051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 185211051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 185311051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 185411284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 185511284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 185611284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 185711284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 185811284Sandreas.hansson@arm.com // but must immediately invalidate it. 185911051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 186011051Sandreas.hansson@arm.com } 186111051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 186211051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 186311051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 186411051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 186511051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 186611051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 186711288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, 186811288Ssteve.reinhardt@amd.com "%s created response: %s addr %#llx size %d tick: %lu\n", 186911051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 187011051Sandreas.hansson@arm.com forward_time); 187111051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 187211051Sandreas.hansson@arm.com} 187311051Sandreas.hansson@arm.com 187411127Sandreas.hansson@arm.comuint32_t 187511051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 187611051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 187711051Sandreas.hansson@arm.com{ 187811288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 187911051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 188011051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 188111051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 188211051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 188311051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 188411051Sandreas.hansson@arm.com assert(pkt->isRequest()); 188511051Sandreas.hansson@arm.com 188611051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 188711051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 188811051Sandreas.hansson@arm.com // original packet up front 188911051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 189011284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 189111051Sandreas.hansson@arm.com 189211285Sandreas.hansson@arm.com // at the moment we could get an uncacheable write which does not 189311285Sandreas.hansson@arm.com // have the invalidate flag, and we need a suitable way of dealing 189411285Sandreas.hansson@arm.com // with this case 189511285Sandreas.hansson@arm.com panic_if(invalidate && pkt->req->isUncacheable(), 189611285Sandreas.hansson@arm.com "%s got an invalidating uncacheable snoop request %s to %#llx", 189711285Sandreas.hansson@arm.com name(), pkt->cmdString(), pkt->getAddr()); 189811285Sandreas.hansson@arm.com 189911127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 190011127Sandreas.hansson@arm.com 190111051Sandreas.hansson@arm.com if (forwardSnoops) { 190211051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 190311051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 190411051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 190511284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 190611051Sandreas.hansson@arm.com if (is_timing) { 190711051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 190811051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 190911051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 191011051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 191111051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 191211051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 191311051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 191411051Sandreas.hansson@arm.com // time 191511051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 191611051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 191711127Sandreas.hansson@arm.com 191811127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 191911127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 192011127Sandreas.hansson@arm.com // cache 192111127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 192211127Sandreas.hansson@arm.com 192311284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 192411051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 192511051Sandreas.hansson@arm.com assert(!alreadyResponded); 192611284Sandreas.hansson@arm.com pkt->setCacheResponding(); 192711051Sandreas.hansson@arm.com } 192811284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 192911284Sandreas.hansson@arm.com // MSHR, pass the flag on 193011284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 193111284Sandreas.hansson@arm.com pkt->setHasSharers(); 193211051Sandreas.hansson@arm.com } 193311051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 193411051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 193511051Sandreas.hansson@arm.com // presence to the requester. 193611051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 193711051Sandreas.hansson@arm.com pkt->setBlockCached(); 193811051Sandreas.hansson@arm.com } 193911051Sandreas.hansson@arm.com } else { 194011051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 194111284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 194211051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 194311051Sandreas.hansson@arm.com // forward response to original requester 194411051Sandreas.hansson@arm.com assert(pkt->isResponse()); 194511051Sandreas.hansson@arm.com } 194611051Sandreas.hansson@arm.com } 194711051Sandreas.hansson@arm.com } 194811051Sandreas.hansson@arm.com 194911051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 195011493Sandreas.hansson@arm.com if (is_deferred) { 195111493Sandreas.hansson@arm.com // we no longer have the block, and will not respond, but a 195211493Sandreas.hansson@arm.com // packet was allocated in MSHR::handleSnoop and we have 195311493Sandreas.hansson@arm.com // to delete it 195411493Sandreas.hansson@arm.com assert(pkt->needsResponse()); 195511493Sandreas.hansson@arm.com 195611493Sandreas.hansson@arm.com // we have passed the block to a cache upstream, that 195711493Sandreas.hansson@arm.com // cache should be responding 195811493Sandreas.hansson@arm.com assert(pkt->cacheResponding()); 195911493Sandreas.hansson@arm.com 196011493Sandreas.hansson@arm.com delete pkt; 196111493Sandreas.hansson@arm.com } 196211493Sandreas.hansson@arm.com 196311288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s snoop miss for %s addr %#llx size %d\n", 196411051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 196511127Sandreas.hansson@arm.com return snoop_delay; 196611051Sandreas.hansson@arm.com } else { 196711288Ssteve.reinhardt@amd.com DPRINTF(Cache, "%s snoop hit for %s addr %#llx size %d, " 196811288Ssteve.reinhardt@amd.com "old state is %s\n", __func__, pkt->cmdString(), 196911288Ssteve.reinhardt@amd.com pkt->getAddr(), pkt->getSize(), blk->print()); 197011051Sandreas.hansson@arm.com } 197111051Sandreas.hansson@arm.com 197211051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 197311051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 197411051Sandreas.hansson@arm.com name()); 197511051Sandreas.hansson@arm.com 197611051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 197711051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 197811051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 197911051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 198011051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 198111051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 198211051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 198311284Sandreas.hansson@arm.com bool have_writable = blk->isWritable(); 198411051Sandreas.hansson@arm.com 198511051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 198611051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 198711051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 198811051Sandreas.hansson@arm.com // downstream caches observe. 198911051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 199011483Snikos.nikoleris@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s " 199111483Snikos.nikoleris@arm.com "from lower cache\n", pkt->getAddr(), pkt->cmdString()); 199211051Sandreas.hansson@arm.com pkt->setBlockCached(); 199311127Sandreas.hansson@arm.com return snoop_delay; 199411051Sandreas.hansson@arm.com } 199511051Sandreas.hansson@arm.com 199611285Sandreas.hansson@arm.com if (pkt->isRead() && !invalidate) { 199711285Sandreas.hansson@arm.com // reading without requiring the line in a writable state 199811284Sandreas.hansson@arm.com assert(!needs_writable); 199911284Sandreas.hansson@arm.com pkt->setHasSharers(); 200011285Sandreas.hansson@arm.com 200111285Sandreas.hansson@arm.com // if the requesting packet is uncacheable, retain the line in 200211285Sandreas.hansson@arm.com // the current state, otherwhise unset the writable flag, 200311285Sandreas.hansson@arm.com // which means we go from Modified to Owned (and will respond 200411285Sandreas.hansson@arm.com // below), remain in Owned (and will respond below), from 200511285Sandreas.hansson@arm.com // Exclusive to Shared, or remain in Shared 200611285Sandreas.hansson@arm.com if (!pkt->req->isUncacheable()) 200711285Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 200811051Sandreas.hansson@arm.com } 200911051Sandreas.hansson@arm.com 201011051Sandreas.hansson@arm.com if (respond) { 201111051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 201211051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 201311284Sandreas.hansson@arm.com // request 201411284Sandreas.hansson@arm.com pkt->setCacheResponding(); 201511284Sandreas.hansson@arm.com if (have_writable) { 201611284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 201711284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 201811284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 201911284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 202011284Sandreas.hansson@arm.com 202111081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 202211284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 202311284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 202411284Sandreas.hansson@arm.com } else { 202511284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 202611284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 202711284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 202811284Sandreas.hansson@arm.com // we already called setHasSharers above 202911051Sandreas.hansson@arm.com } 203011284Sandreas.hansson@arm.com 203111285Sandreas.hansson@arm.com // if we are returning a writable and dirty (Modified) line, 203211285Sandreas.hansson@arm.com // we should be invalidating the line 203311285Sandreas.hansson@arm.com panic_if(!invalidate && !pkt->hasSharers(), 203411285Sandreas.hansson@arm.com "%s is passing a Modified line through %s to %#llx, " 203511285Sandreas.hansson@arm.com "but keeping the block", 203611285Sandreas.hansson@arm.com name(), pkt->cmdString(), pkt->getAddr()); 203711285Sandreas.hansson@arm.com 203811051Sandreas.hansson@arm.com if (is_timing) { 203911051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 204011051Sandreas.hansson@arm.com } else { 204111051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 204211286Sandreas.hansson@arm.com // packets such as upgrades do not actually have any data 204311286Sandreas.hansson@arm.com // payload 204411286Sandreas.hansson@arm.com if (pkt->hasData()) 204511286Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 204611051Sandreas.hansson@arm.com } 204711051Sandreas.hansson@arm.com } 204811051Sandreas.hansson@arm.com 204911051Sandreas.hansson@arm.com if (!respond && is_timing && is_deferred) { 205011271Sandreas.hansson@arm.com // if it's a deferred timing snoop to which we are not 205111271Sandreas.hansson@arm.com // responding, then we've made a copy of both the request and 205211271Sandreas.hansson@arm.com // the packet, delete them here 205311051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 205411493Sandreas.hansson@arm.com assert(!pkt->cacheResponding()); 205511051Sandreas.hansson@arm.com delete pkt->req; 205611051Sandreas.hansson@arm.com delete pkt; 205711051Sandreas.hansson@arm.com } 205811051Sandreas.hansson@arm.com 205911051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 206011051Sandreas.hansson@arm.com // like that 206111051Sandreas.hansson@arm.com if (invalidate) { 206211197Sandreas.hansson@arm.com invalidateBlock(blk); 206311051Sandreas.hansson@arm.com } 206411051Sandreas.hansson@arm.com 206511051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 206611127Sandreas.hansson@arm.com 206711127Sandreas.hansson@arm.com return snoop_delay; 206811051Sandreas.hansson@arm.com} 206911051Sandreas.hansson@arm.com 207011051Sandreas.hansson@arm.com 207111051Sandreas.hansson@arm.comvoid 207211051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 207311051Sandreas.hansson@arm.com{ 207411288Ssteve.reinhardt@amd.com DPRINTF(CacheVerbose, "%s for %s addr %#llx size %d\n", __func__, 207511051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 207611051Sandreas.hansson@arm.com 207711051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 207811051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 207911051Sandreas.hansson@arm.com 208011130Sali.jafri@arm.com // no need to snoop requests that are not in range 208111051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 208211051Sandreas.hansson@arm.com return; 208311051Sandreas.hansson@arm.com } 208411051Sandreas.hansson@arm.com 208511051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 208611051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 208711051Sandreas.hansson@arm.com 208811051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 208911051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 209011051Sandreas.hansson@arm.com 209111127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 209211127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 209311127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 209411127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 209511127Sandreas.hansson@arm.com // happens below. 209611127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 209711127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 209811127Sandreas.hansson@arm.com 209911051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 210011051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 210111051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 210211051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from" 210311051Sandreas.hansson@arm.com "lower cache on mshr hit %#x\n", 210411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 210511051Sandreas.hansson@arm.com pkt->setBlockCached(); 210611051Sandreas.hansson@arm.com return; 210711051Sandreas.hansson@arm.com } 210811051Sandreas.hansson@arm.com 210911051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 211011051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 211111051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 211211051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 211311051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 211411051Sandreas.hansson@arm.com mshr->print()); 211511051Sandreas.hansson@arm.com 211611051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 211711051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 211811051Sandreas.hansson@arm.com return; 211911051Sandreas.hansson@arm.com } 212011051Sandreas.hansson@arm.com 212111051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 212211375Sandreas.hansson@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(blk_addr, is_secure); 212311375Sandreas.hansson@arm.com if (wb_entry) { 212411051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 212511051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 212611051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 212711051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 212811051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 212911051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 213011051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 213111051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 213211051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 213311199Sandreas.hansson@arm.com assert(wb_pkt->isEviction()); 213411051Sandreas.hansson@arm.com 213511199Sandreas.hansson@arm.com if (pkt->isEviction()) { 213611051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 213711051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 213811051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 213911051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 214011051Sandreas.hansson@arm.com pkt->setBlockCached(); 214111051Sandreas.hansson@arm.com DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit" 214211051Sandreas.hansson@arm.com " %#x\n", pkt->cmdString(), pkt->getAddr()); 214311051Sandreas.hansson@arm.com return; 214411051Sandreas.hansson@arm.com } 214511051Sandreas.hansson@arm.com 214611332Sandreas.hansson@arm.com // conceptually writebacks are no different to other blocks in 214711332Sandreas.hansson@arm.com // this cache, so the behaviour is modelled after handleSnoop, 214811332Sandreas.hansson@arm.com // the difference being that instead of querying the block 214911332Sandreas.hansson@arm.com // state to determine if it is dirty and writable, we use the 215011332Sandreas.hansson@arm.com // command and fields of the writeback packet 215111332Sandreas.hansson@arm.com bool respond = wb_pkt->cmd == MemCmd::WritebackDirty && 215211332Sandreas.hansson@arm.com pkt->needsResponse() && pkt->cmd != MemCmd::InvalidateReq; 215311332Sandreas.hansson@arm.com bool have_writable = !wb_pkt->hasSharers(); 215411332Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 215511332Sandreas.hansson@arm.com 215611332Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 215711332Sandreas.hansson@arm.com assert(!pkt->needsWritable()); 215811332Sandreas.hansson@arm.com pkt->setHasSharers(); 215911332Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 216011332Sandreas.hansson@arm.com } 216111332Sandreas.hansson@arm.com 216211332Sandreas.hansson@arm.com if (respond) { 216311284Sandreas.hansson@arm.com pkt->setCacheResponding(); 216411332Sandreas.hansson@arm.com 216511332Sandreas.hansson@arm.com if (have_writable) { 216611332Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 216711051Sandreas.hansson@arm.com } 216811332Sandreas.hansson@arm.com 216911051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 217011051Sandreas.hansson@arm.com false, false); 217111051Sandreas.hansson@arm.com } 217211051Sandreas.hansson@arm.com 217311332Sandreas.hansson@arm.com if (invalidate) { 217411051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 217511051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 217611375Sandreas.hansson@arm.com markInService(wb_entry); 217711051Sandreas.hansson@arm.com delete wb_pkt; 217811051Sandreas.hansson@arm.com } 217911051Sandreas.hansson@arm.com } 218011051Sandreas.hansson@arm.com 218111051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 218211051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 218311051Sandreas.hansson@arm.com // We could be more selective and return here if the 218411051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 218511051Sandreas.hansson@arm.com // exclusive. 218611127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 218711127Sandreas.hansson@arm.com 218811127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 218911127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 219011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 219111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 219211051Sandreas.hansson@arm.com} 219311051Sandreas.hansson@arm.com 219411051Sandreas.hansson@arm.combool 219511051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 219611051Sandreas.hansson@arm.com{ 219711051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 219811051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 219911051Sandreas.hansson@arm.com return true; 220011051Sandreas.hansson@arm.com} 220111051Sandreas.hansson@arm.com 220211051Sandreas.hansson@arm.comTick 220311051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 220411051Sandreas.hansson@arm.com{ 220511051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 220611051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 220711051Sandreas.hansson@arm.com 220811130Sali.jafri@arm.com // no need to snoop requests that are not in range. 220911130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 221011051Sandreas.hansson@arm.com return 0; 221111051Sandreas.hansson@arm.com } 221211051Sandreas.hansson@arm.com 221311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 221411127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 221511127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 221611051Sandreas.hansson@arm.com} 221711051Sandreas.hansson@arm.com 221811051Sandreas.hansson@arm.com 221911375Sandreas.hansson@arm.comQueueEntry* 222011375Sandreas.hansson@arm.comCache::getNextQueueEntry() 222111051Sandreas.hansson@arm.com{ 222211051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 222311051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 222411051Sandreas.hansson@arm.com // simply be that it is not ready 222511375Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 222611375Sandreas.hansson@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 222711051Sandreas.hansson@arm.com 222811051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 222911453Sandreas.hansson@arm.com // full write buffer, otherwise we favour the miss requests 223011453Sandreas.hansson@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 223111051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 223211051Sandreas.hansson@arm.com MSHR *conflict_mshr = 223311375Sandreas.hansson@arm.com mshrQueue.findPending(wq_entry->blkAddr, 223411375Sandreas.hansson@arm.com wq_entry->isSecure); 223511375Sandreas.hansson@arm.com 223611375Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 223711051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 223811051Sandreas.hansson@arm.com return conflict_mshr; 223911051Sandreas.hansson@arm.com 224011051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 224111051Sandreas.hansson@arm.com } 224211051Sandreas.hansson@arm.com 224311051Sandreas.hansson@arm.com // No conflicts; issue write 224411375Sandreas.hansson@arm.com return wq_entry; 224511051Sandreas.hansson@arm.com } else if (miss_mshr) { 224611051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 224711375Sandreas.hansson@arm.com WriteQueueEntry *conflict_mshr = 224811051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 224911051Sandreas.hansson@arm.com miss_mshr->isSecure); 225011051Sandreas.hansson@arm.com if (conflict_mshr) { 225111051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 225211051Sandreas.hansson@arm.com // original code but commented out. 225311051Sandreas.hansson@arm.com 225411051Sandreas.hansson@arm.com // The only way this happens is if we are 225511051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 225611051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 225711051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 225811051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 225911051Sandreas.hansson@arm.com 226011375Sandreas.hansson@arm.com // should we return wq_entry here instead? I.e. do we 226111051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 226211051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 226311051Sandreas.hansson@arm.com return conflict_mshr; 226411051Sandreas.hansson@arm.com 226511051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 226611051Sandreas.hansson@arm.com } 226711051Sandreas.hansson@arm.com 226811051Sandreas.hansson@arm.com // No conflicts; issue read 226911051Sandreas.hansson@arm.com return miss_mshr; 227011051Sandreas.hansson@arm.com } 227111051Sandreas.hansson@arm.com 227211051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 227311375Sandreas.hansson@arm.com assert(!miss_mshr && !wq_entry); 227411051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 227511051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 227611051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 227711051Sandreas.hansson@arm.com if (pkt) { 227811051Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 227911051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 228011051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 228111051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 228211051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 228311051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 228411051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 228511051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 228611051Sandreas.hansson@arm.com 228711051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 228811051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 228911051Sandreas.hansson@arm.com // schedule the send 229011051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 229111051Sandreas.hansson@arm.com } else { 229211051Sandreas.hansson@arm.com // free the request and packet 229311051Sandreas.hansson@arm.com delete pkt->req; 229411051Sandreas.hansson@arm.com delete pkt; 229511051Sandreas.hansson@arm.com } 229611051Sandreas.hansson@arm.com } 229711051Sandreas.hansson@arm.com } 229811051Sandreas.hansson@arm.com 229911375Sandreas.hansson@arm.com return nullptr; 230011051Sandreas.hansson@arm.com} 230111051Sandreas.hansson@arm.com 230211051Sandreas.hansson@arm.combool 230311130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 230411051Sandreas.hansson@arm.com{ 230511051Sandreas.hansson@arm.com if (!forwardSnoops) 230611051Sandreas.hansson@arm.com return false; 230711051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 230811051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 230911051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 231011051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 231111051Sandreas.hansson@arm.com // of the block. 231211130Sali.jafri@arm.com if (is_timing) { 231311130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 231411130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 231511130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 231611130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 231711130Sali.jafri@arm.com // generate a snoop response. 231811199Sandreas.hansson@arm.com assert(pkt->isEviction()); 231911484Snikos.nikoleris@arm.com snoop_pkt.senderState = nullptr; 232011130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 232111130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 232211284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 232311130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 232411130Sali.jafri@arm.com } else { 232511130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 232611130Sali.jafri@arm.com return pkt->isBlockCached(); 232711130Sali.jafri@arm.com } 232811051Sandreas.hansson@arm.com} 232911051Sandreas.hansson@arm.com 233011375Sandreas.hansson@arm.comTick 233111375Sandreas.hansson@arm.comCache::nextQueueReadyTime() const 233211051Sandreas.hansson@arm.com{ 233311375Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 233411375Sandreas.hansson@arm.com writeBuffer.nextReadyTime()); 233511375Sandreas.hansson@arm.com 233611375Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 233711375Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 233811375Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 233911375Sandreas.hansson@arm.com nextReady = std::min(nextReady, 234011375Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 234111051Sandreas.hansson@arm.com } 234211051Sandreas.hansson@arm.com 234311375Sandreas.hansson@arm.com return nextReady; 234411375Sandreas.hansson@arm.com} 234511375Sandreas.hansson@arm.com 234611375Sandreas.hansson@arm.combool 234711375Sandreas.hansson@arm.comCache::sendMSHRQueuePacket(MSHR* mshr) 234811375Sandreas.hansson@arm.com{ 234911375Sandreas.hansson@arm.com assert(mshr); 235011375Sandreas.hansson@arm.com 235111051Sandreas.hansson@arm.com // use request from 1st target 235211051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 235311375Sandreas.hansson@arm.com 235411375Sandreas.hansson@arm.com DPRINTF(Cache, "%s MSHR %s for addr %#llx size %d\n", __func__, 235511375Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), 235611375Sandreas.hansson@arm.com tgt_pkt->getSize()); 235711051Sandreas.hansson@arm.com 235811051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 235911051Sandreas.hansson@arm.com 236011051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 236111375Sandreas.hansson@arm.com // we should never have hardware prefetches to allocated 236211375Sandreas.hansson@arm.com // blocks 236311484Snikos.nikoleris@arm.com assert(blk == nullptr); 236411375Sandreas.hansson@arm.com 236511051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 236611051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 236711051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 236811051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 236911051Sandreas.hansson@arm.com // dirty one. 237011051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 237111051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 237211275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 237311275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 237411275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 237511275Sandreas.hansson@arm.com // state 237611051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 237711051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 237811051Sandreas.hansson@arm.com 237911051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 238011051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 238111051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 238211051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 238311051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 238411051Sandreas.hansson@arm.com 238511284Sandreas.hansson@arm.com // It is important to check cacheResponding before 238611284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 238711284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 238811284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 238911284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 239011284Sandreas.hansson@arm.com // prematurely deallocated. 239111284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 239211276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 239311276Sandreas.hansson@arm.com assert(r.second); 239411284Sandreas.hansson@arm.com 239511284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 239611284Sandreas.hansson@arm.com // will be allocated as Modified 239711284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 239811284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 239911284Sandreas.hansson@arm.com 240011051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 240111051Sandreas.hansson@arm.com " %#x (%s) hit\n", 240211051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 240311375Sandreas.hansson@arm.com return false; 240411051Sandreas.hansson@arm.com } 240511051Sandreas.hansson@arm.com 240611375Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached()) { 240711051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 240811051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 240911051Sandreas.hansson@arm.com mshr->blkAddr); 241011375Sandreas.hansson@arm.com 241111051Sandreas.hansson@arm.com // Deallocate the mshr target 241211375Sandreas.hansson@arm.com if (mshrQueue.forceDeallocateTarget(mshr)) { 241311277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 241411277Sandreas.hansson@arm.com // mshr when all had previously been utilized 241511375Sandreas.hansson@arm.com clearBlocked(Blocked_NoMSHRs); 241611051Sandreas.hansson@arm.com } 241711375Sandreas.hansson@arm.com return false; 241811051Sandreas.hansson@arm.com } 241911051Sandreas.hansson@arm.com } 242011051Sandreas.hansson@arm.com 242111375Sandreas.hansson@arm.com // either a prefetch that is not present upstream, or a normal 242211375Sandreas.hansson@arm.com // MSHR request, proceed to get the packet to send downstream 242311452Sandreas.hansson@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 242411375Sandreas.hansson@arm.com 242511484Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 242611375Sandreas.hansson@arm.com 242711375Sandreas.hansson@arm.com if (mshr->isForward) { 242811375Sandreas.hansson@arm.com // not a cache block request, but a response is expected 242911375Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 243011375Sandreas.hansson@arm.com // copy for response handling 243111375Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 243211375Sandreas.hansson@arm.com assert(!pkt->isWrite()); 243311375Sandreas.hansson@arm.com } 243411375Sandreas.hansson@arm.com 243511375Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, 243611375Sandreas.hansson@arm.com // as forwarded packets may already have existing state 243711375Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 243811375Sandreas.hansson@arm.com 243911375Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(pkt)) { 244011375Sandreas.hansson@arm.com // we are awaiting a retry, but we 244111375Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 244211375Sandreas.hansson@arm.com // when we get the opportunity 244311375Sandreas.hansson@arm.com delete pkt; 244411375Sandreas.hansson@arm.com 244511375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 244611375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 244711375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 244811375Sandreas.hansson@arm.com // care about this packet and might override it before 244911375Sandreas.hansson@arm.com // it gets retried 245011375Sandreas.hansson@arm.com return true; 245111375Sandreas.hansson@arm.com } else { 245211375Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 245311375Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 245411375Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 245511375Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 245611375Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 245711375Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 245811375Sandreas.hansson@arm.com // point 245911375Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 246011375Sandreas.hansson@arm.com pkt->cacheResponding(); 246111375Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 246211375Sandreas.hansson@arm.com return false; 246311375Sandreas.hansson@arm.com } 246411375Sandreas.hansson@arm.com} 246511375Sandreas.hansson@arm.com 246611375Sandreas.hansson@arm.combool 246711375Sandreas.hansson@arm.comCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 246811375Sandreas.hansson@arm.com{ 246911375Sandreas.hansson@arm.com assert(wq_entry); 247011375Sandreas.hansson@arm.com 247111375Sandreas.hansson@arm.com // always a single target for write queue entries 247211375Sandreas.hansson@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 247311375Sandreas.hansson@arm.com 247411375Sandreas.hansson@arm.com DPRINTF(Cache, "%s write %s for addr %#llx size %d\n", __func__, 247511375Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), 247611375Sandreas.hansson@arm.com tgt_pkt->getSize()); 247711375Sandreas.hansson@arm.com 247811453Sandreas.hansson@arm.com // forward as is, both for evictions and uncacheable writes 247911453Sandreas.hansson@arm.com if (!memSidePort->sendTimingReq(tgt_pkt)) { 248011375Sandreas.hansson@arm.com // note that we have now masked any requestBus and 248111375Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 248211375Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 248311375Sandreas.hansson@arm.com // care about this packet and might override it before 248411375Sandreas.hansson@arm.com // it gets retried 248511375Sandreas.hansson@arm.com return true; 248611375Sandreas.hansson@arm.com } else { 248711375Sandreas.hansson@arm.com markInService(wq_entry); 248811375Sandreas.hansson@arm.com return false; 248911051Sandreas.hansson@arm.com } 249011051Sandreas.hansson@arm.com} 249111051Sandreas.hansson@arm.com 249211051Sandreas.hansson@arm.comvoid 249311051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 249411051Sandreas.hansson@arm.com{ 249511051Sandreas.hansson@arm.com bool dirty(isDirty()); 249611051Sandreas.hansson@arm.com 249711051Sandreas.hansson@arm.com if (dirty) { 249811051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 249911051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 250011483Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly and dirty data " 250111483Snikos.nikoleris@arm.com " in the cache will be lost!\n"); 250211051Sandreas.hansson@arm.com } 250311051Sandreas.hansson@arm.com 250411051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 250511051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 250611051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 250711051Sandreas.hansson@arm.com // cache contains dirty data. 250811051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 250911051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 251011051Sandreas.hansson@arm.com} 251111051Sandreas.hansson@arm.com 251211051Sandreas.hansson@arm.comvoid 251311051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 251411051Sandreas.hansson@arm.com{ 251511051Sandreas.hansson@arm.com bool bad_checkpoint; 251611051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 251711051Sandreas.hansson@arm.com if (bad_checkpoint) { 251811051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 251911051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 252011051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 252111051Sandreas.hansson@arm.com } 252211051Sandreas.hansson@arm.com} 252311051Sandreas.hansson@arm.com 252411051Sandreas.hansson@arm.com/////////////// 252511051Sandreas.hansson@arm.com// 252611051Sandreas.hansson@arm.com// CpuSidePort 252711051Sandreas.hansson@arm.com// 252811051Sandreas.hansson@arm.com/////////////// 252911051Sandreas.hansson@arm.com 253011051Sandreas.hansson@arm.comAddrRangeList 253111051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 253211051Sandreas.hansson@arm.com{ 253311051Sandreas.hansson@arm.com return cache->getAddrRanges(); 253411051Sandreas.hansson@arm.com} 253511051Sandreas.hansson@arm.com 253611051Sandreas.hansson@arm.combool 253711051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 253811051Sandreas.hansson@arm.com{ 253911051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 254011051Sandreas.hansson@arm.com 254111051Sandreas.hansson@arm.com bool success = false; 254211051Sandreas.hansson@arm.com 254311334Sandreas.hansson@arm.com // always let express snoop packets through if even if blocked 254411334Sandreas.hansson@arm.com if (pkt->isExpressSnoop()) { 254511051Sandreas.hansson@arm.com // do not change the current retry state 254611051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 254711051Sandreas.hansson@arm.com assert(bypass_success); 254811051Sandreas.hansson@arm.com return true; 254911051Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 255011051Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 255111051Sandreas.hansson@arm.com success = false; 255211051Sandreas.hansson@arm.com } else { 255311051Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 255411051Sandreas.hansson@arm.com // have to retry or not 255511051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 255611051Sandreas.hansson@arm.com } 255711051Sandreas.hansson@arm.com 255811051Sandreas.hansson@arm.com // remember if we have to retry 255911051Sandreas.hansson@arm.com mustSendRetry = !success; 256011051Sandreas.hansson@arm.com return success; 256111051Sandreas.hansson@arm.com} 256211051Sandreas.hansson@arm.com 256311051Sandreas.hansson@arm.comTick 256411051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 256511051Sandreas.hansson@arm.com{ 256611051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 256711051Sandreas.hansson@arm.com} 256811051Sandreas.hansson@arm.com 256911051Sandreas.hansson@arm.comvoid 257011051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 257111051Sandreas.hansson@arm.com{ 257211051Sandreas.hansson@arm.com // functional request 257311051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 257411051Sandreas.hansson@arm.com} 257511051Sandreas.hansson@arm.com 257611051Sandreas.hansson@arm.comCache:: 257711051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 257811051Sandreas.hansson@arm.com const std::string &_label) 257911051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 258011051Sandreas.hansson@arm.com{ 258111051Sandreas.hansson@arm.com} 258211051Sandreas.hansson@arm.com 258311053Sandreas.hansson@arm.comCache* 258411053Sandreas.hansson@arm.comCacheParams::create() 258511053Sandreas.hansson@arm.com{ 258611053Sandreas.hansson@arm.com assert(tags); 258711053Sandreas.hansson@arm.com 258811053Sandreas.hansson@arm.com return new Cache(this); 258911053Sandreas.hansson@arm.com} 259011051Sandreas.hansson@arm.com/////////////// 259111051Sandreas.hansson@arm.com// 259211051Sandreas.hansson@arm.com// MemSidePort 259311051Sandreas.hansson@arm.com// 259411051Sandreas.hansson@arm.com/////////////// 259511051Sandreas.hansson@arm.com 259611051Sandreas.hansson@arm.combool 259711051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 259811051Sandreas.hansson@arm.com{ 259911051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 260011051Sandreas.hansson@arm.com return true; 260111051Sandreas.hansson@arm.com} 260211051Sandreas.hansson@arm.com 260311051Sandreas.hansson@arm.com// Express snooping requests to memside port 260411051Sandreas.hansson@arm.comvoid 260511051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 260611051Sandreas.hansson@arm.com{ 260711051Sandreas.hansson@arm.com // handle snooping requests 260811051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 260911051Sandreas.hansson@arm.com} 261011051Sandreas.hansson@arm.com 261111051Sandreas.hansson@arm.comTick 261211051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 261311051Sandreas.hansson@arm.com{ 261411051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 261511051Sandreas.hansson@arm.com} 261611051Sandreas.hansson@arm.com 261711051Sandreas.hansson@arm.comvoid 261811051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 261911051Sandreas.hansson@arm.com{ 262011051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 262111051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 262211051Sandreas.hansson@arm.com // behaviour regardless) 262311051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 262411051Sandreas.hansson@arm.com} 262511051Sandreas.hansson@arm.com 262611051Sandreas.hansson@arm.comvoid 262711051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 262811051Sandreas.hansson@arm.com{ 262911051Sandreas.hansson@arm.com // sanity check 263011051Sandreas.hansson@arm.com assert(!waitingOnRetry); 263111051Sandreas.hansson@arm.com 263211051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 263311051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 263411051Sandreas.hansson@arm.com // from the MSHR queue or write queue 263511051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 263611051Sandreas.hansson@arm.com 263711051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 263811375Sandreas.hansson@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 263911375Sandreas.hansson@arm.com 264011375Sandreas.hansson@arm.com if (!entry) { 264111051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 264211051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 264311051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 264411051Sandreas.hansson@arm.com } else { 264511051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 264611375Sandreas.hansson@arm.com // the same addresses 264711375Sandreas.hansson@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 264811051Sandreas.hansson@arm.com return; 264911051Sandreas.hansson@arm.com } 265011375Sandreas.hansson@arm.com waitingOnRetry = entry->sendPacket(cache); 265111051Sandreas.hansson@arm.com } 265211051Sandreas.hansson@arm.com 265311051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 265411375Sandreas.hansson@arm.com // next send considering when the next queue is ready, note that 265511051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 265611051Sandreas.hansson@arm.com // their own events 265711051Sandreas.hansson@arm.com if (!waitingOnRetry) { 265811375Sandreas.hansson@arm.com schedSendEvent(cache.nextQueueReadyTime()); 265911051Sandreas.hansson@arm.com } 266011051Sandreas.hansson@arm.com} 266111051Sandreas.hansson@arm.com 266211051Sandreas.hansson@arm.comCache:: 266311051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 266411051Sandreas.hansson@arm.com const std::string &_label) 266511051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 266611051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 266711051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 266811051Sandreas.hansson@arm.com{ 266911051Sandreas.hansson@arm.com} 2670