cache.cc revision 11284
12810Srdreslin@umich.edu/* 211051Sandreas.hansson@arm.com * Copyright (c) 2010-2015 ARM Limited 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 611051Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 711051Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 811051Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 911051Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 1011051Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 1111051Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 1211051Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 1311051Sandreas.hansson@arm.com * 1411051Sandreas.hansson@arm.com * Copyright (c) 2002-2005 The Regents of The University of Michigan 1511051Sandreas.hansson@arm.com * Copyright (c) 2010,2015 Advanced Micro Devices, Inc. 162810Srdreslin@umich.edu * All rights reserved. 172810Srdreslin@umich.edu * 182810Srdreslin@umich.edu * Redistribution and use in source and binary forms, with or without 192810Srdreslin@umich.edu * modification, are permitted provided that the following conditions are 202810Srdreslin@umich.edu * met: redistributions of source code must retain the above copyright 212810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer; 222810Srdreslin@umich.edu * redistributions in binary form must reproduce the above copyright 232810Srdreslin@umich.edu * notice, this list of conditions and the following disclaimer in the 242810Srdreslin@umich.edu * documentation and/or other materials provided with the distribution; 252810Srdreslin@umich.edu * neither the name of the copyright holders nor the names of its 262810Srdreslin@umich.edu * contributors may be used to endorse or promote products derived from 272810Srdreslin@umich.edu * this software without specific prior written permission. 282810Srdreslin@umich.edu * 292810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402810Srdreslin@umich.edu * 412810Srdreslin@umich.edu * Authors: Erik Hallnor 4211051Sandreas.hansson@arm.com * Dave Greene 4311051Sandreas.hansson@arm.com * Nathan Binkert 442810Srdreslin@umich.edu * Steve Reinhardt 4511051Sandreas.hansson@arm.com * Ron Dreslinski 4611051Sandreas.hansson@arm.com * Andreas Sandberg 472810Srdreslin@umich.edu */ 482810Srdreslin@umich.edu 492810Srdreslin@umich.edu/** 502810Srdreslin@umich.edu * @file 5111051Sandreas.hansson@arm.com * Cache definitions. 522810Srdreslin@umich.edu */ 532810Srdreslin@umich.edu 5411051Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 552810Srdreslin@umich.edu 5611051Sandreas.hansson@arm.com#include "base/misc.hh" 5711051Sandreas.hansson@arm.com#include "base/types.hh" 5811051Sandreas.hansson@arm.com#include "debug/Cache.hh" 5911051Sandreas.hansson@arm.com#include "debug/CachePort.hh" 6011051Sandreas.hansson@arm.com#include "debug/CacheTags.hh" 6111051Sandreas.hansson@arm.com#include "mem/cache/blk.hh" 6211051Sandreas.hansson@arm.com#include "mem/cache/mshr.hh" 6311051Sandreas.hansson@arm.com#include "mem/cache/prefetch/base.hh" 6411051Sandreas.hansson@arm.com#include "sim/sim_exit.hh" 6511051Sandreas.hansson@arm.com 6611053Sandreas.hansson@arm.comCache::Cache(const CacheParams *p) 6711053Sandreas.hansson@arm.com : BaseCache(p, p->system->cacheLineSize()), 6811051Sandreas.hansson@arm.com tags(p->tags), 6911051Sandreas.hansson@arm.com prefetcher(p->prefetcher), 7011051Sandreas.hansson@arm.com doFastWrites(true), 7111197Sandreas.hansson@arm.com prefetchOnAccess(p->prefetch_on_access), 7211197Sandreas.hansson@arm.com clusivity(p->clusivity), 7311199Sandreas.hansson@arm.com writebackClean(p->writeback_clean), 7411197Sandreas.hansson@arm.com tempBlockWriteback(nullptr), 7511197Sandreas.hansson@arm.com writebackTempBlockAtomicEvent(this, false, 7611197Sandreas.hansson@arm.com EventBase::Delayed_Writeback_Pri) 7711051Sandreas.hansson@arm.com{ 7811051Sandreas.hansson@arm.com tempBlock = new CacheBlk(); 7911051Sandreas.hansson@arm.com tempBlock->data = new uint8_t[blkSize]; 8011051Sandreas.hansson@arm.com 8111051Sandreas.hansson@arm.com cpuSidePort = new CpuSidePort(p->name + ".cpu_side", this, 8211051Sandreas.hansson@arm.com "CpuSidePort"); 8311051Sandreas.hansson@arm.com memSidePort = new MemSidePort(p->name + ".mem_side", this, 8411051Sandreas.hansson@arm.com "MemSidePort"); 8511051Sandreas.hansson@arm.com 8611051Sandreas.hansson@arm.com tags->setCache(this); 8711051Sandreas.hansson@arm.com if (prefetcher) 8811051Sandreas.hansson@arm.com prefetcher->setCache(this); 8911051Sandreas.hansson@arm.com} 9011051Sandreas.hansson@arm.com 9111051Sandreas.hansson@arm.comCache::~Cache() 9211051Sandreas.hansson@arm.com{ 9311051Sandreas.hansson@arm.com delete [] tempBlock->data; 9411051Sandreas.hansson@arm.com delete tempBlock; 9511051Sandreas.hansson@arm.com 9611051Sandreas.hansson@arm.com delete cpuSidePort; 9711051Sandreas.hansson@arm.com delete memSidePort; 9811051Sandreas.hansson@arm.com} 9911051Sandreas.hansson@arm.com 10011051Sandreas.hansson@arm.comvoid 10111051Sandreas.hansson@arm.comCache::regStats() 10211051Sandreas.hansson@arm.com{ 10311051Sandreas.hansson@arm.com BaseCache::regStats(); 10411051Sandreas.hansson@arm.com} 10511051Sandreas.hansson@arm.com 10611051Sandreas.hansson@arm.comvoid 10711051Sandreas.hansson@arm.comCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 10811051Sandreas.hansson@arm.com{ 10911051Sandreas.hansson@arm.com assert(pkt->isRequest()); 11011051Sandreas.hansson@arm.com 11111051Sandreas.hansson@arm.com uint64_t overwrite_val; 11211051Sandreas.hansson@arm.com bool overwrite_mem; 11311051Sandreas.hansson@arm.com uint64_t condition_val64; 11411051Sandreas.hansson@arm.com uint32_t condition_val32; 11511051Sandreas.hansson@arm.com 11611051Sandreas.hansson@arm.com int offset = tags->extractBlkOffset(pkt->getAddr()); 11711051Sandreas.hansson@arm.com uint8_t *blk_data = blk->data + offset; 11811051Sandreas.hansson@arm.com 11911051Sandreas.hansson@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 12011051Sandreas.hansson@arm.com 12111051Sandreas.hansson@arm.com overwrite_mem = true; 12211051Sandreas.hansson@arm.com // keep a copy of our possible write value, and copy what is at the 12311051Sandreas.hansson@arm.com // memory address into the packet 12411051Sandreas.hansson@arm.com pkt->writeData((uint8_t *)&overwrite_val); 12511051Sandreas.hansson@arm.com pkt->setData(blk_data); 12611051Sandreas.hansson@arm.com 12711051Sandreas.hansson@arm.com if (pkt->req->isCondSwap()) { 12811051Sandreas.hansson@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 12911051Sandreas.hansson@arm.com condition_val64 = pkt->req->getExtraData(); 13011051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 13111051Sandreas.hansson@arm.com sizeof(uint64_t)); 13211051Sandreas.hansson@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 13311051Sandreas.hansson@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 13411051Sandreas.hansson@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 13511051Sandreas.hansson@arm.com sizeof(uint32_t)); 13611051Sandreas.hansson@arm.com } else 13711051Sandreas.hansson@arm.com panic("Invalid size for conditional read/write\n"); 13811051Sandreas.hansson@arm.com } 13911051Sandreas.hansson@arm.com 14011051Sandreas.hansson@arm.com if (overwrite_mem) { 14111051Sandreas.hansson@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 14211051Sandreas.hansson@arm.com blk->status |= BlkDirty; 14311051Sandreas.hansson@arm.com } 14411051Sandreas.hansson@arm.com} 14511051Sandreas.hansson@arm.com 14611051Sandreas.hansson@arm.com 14711051Sandreas.hansson@arm.comvoid 14811051Sandreas.hansson@arm.comCache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk, 14911051Sandreas.hansson@arm.com bool deferred_response, bool pending_downgrade) 15011051Sandreas.hansson@arm.com{ 15111051Sandreas.hansson@arm.com assert(pkt->isRequest()); 15211051Sandreas.hansson@arm.com 15311051Sandreas.hansson@arm.com assert(blk && blk->isValid()); 15411051Sandreas.hansson@arm.com // Occasionally this is not true... if we are a lower-level cache 15511051Sandreas.hansson@arm.com // satisfying a string of Read and ReadEx requests from 15611051Sandreas.hansson@arm.com // upper-level caches, a Read will mark the block as shared but we 15711051Sandreas.hansson@arm.com // can satisfy a following ReadEx anyway since we can rely on the 15811051Sandreas.hansson@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 15911051Sandreas.hansson@arm.com // invalidate their blocks after receiving them. 16011284Sandreas.hansson@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 16111051Sandreas.hansson@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 16211051Sandreas.hansson@arm.com 16311051Sandreas.hansson@arm.com // Check RMW operations first since both isRead() and 16411051Sandreas.hansson@arm.com // isWrite() will be true for them 16511051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::SwapReq) { 16611051Sandreas.hansson@arm.com cmpAndSwap(blk, pkt); 16711051Sandreas.hansson@arm.com } else if (pkt->isWrite()) { 16811284Sandreas.hansson@arm.com // we have the block in a writable state and can go ahead, 16911284Sandreas.hansson@arm.com // note that the line may be also be considered writable in 17011284Sandreas.hansson@arm.com // downstream caches along the path to memory, but always 17111284Sandreas.hansson@arm.com // Exclusive, and never Modified 17211051Sandreas.hansson@arm.com assert(blk->isWritable()); 17311284Sandreas.hansson@arm.com // Write or WriteLine at the first cache with block in writable state 17411051Sandreas.hansson@arm.com if (blk->checkWrite(pkt)) { 17511051Sandreas.hansson@arm.com pkt->writeDataToBlock(blk->data, blkSize); 17611051Sandreas.hansson@arm.com } 17711284Sandreas.hansson@arm.com // Always mark the line as dirty (and thus transition to the 17811284Sandreas.hansson@arm.com // Modified state) even if we are a failed StoreCond so we 17911284Sandreas.hansson@arm.com // supply data to any snoops that have appended themselves to 18011284Sandreas.hansson@arm.com // this cache before knowing the store will fail. 18111051Sandreas.hansson@arm.com blk->status |= BlkDirty; 18211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (write)\n", __func__, 18311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 18411051Sandreas.hansson@arm.com } else if (pkt->isRead()) { 18511051Sandreas.hansson@arm.com if (pkt->isLLSC()) { 18611051Sandreas.hansson@arm.com blk->trackLoadLocked(pkt); 18711051Sandreas.hansson@arm.com } 18811051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 18911051Sandreas.hansson@arm.com // determine if this read is from a (coherent) cache, or not 19011051Sandreas.hansson@arm.com // by looking at the command type; we could potentially add a 19111051Sandreas.hansson@arm.com // packet attribute such as 'FromCache' to make this check a 19211051Sandreas.hansson@arm.com // bit cleaner 19311051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadExReq || 19411051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadSharedReq || 19511051Sandreas.hansson@arm.com pkt->cmd == MemCmd::ReadCleanReq || 19611051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq) { 19711051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 19811051Sandreas.hansson@arm.com // special handling for coherent block requests from 19911051Sandreas.hansson@arm.com // upper-level caches 20011284Sandreas.hansson@arm.com if (pkt->needsWritable()) { 20111051Sandreas.hansson@arm.com // sanity check 20211051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::ReadExReq || 20311051Sandreas.hansson@arm.com pkt->cmd == MemCmd::SCUpgradeFailReq); 20411051Sandreas.hansson@arm.com 20511051Sandreas.hansson@arm.com // if we have a dirty copy, make sure the recipient 20611284Sandreas.hansson@arm.com // keeps it marked dirty (in the modified state) 20711051Sandreas.hansson@arm.com if (blk->isDirty()) { 20811284Sandreas.hansson@arm.com pkt->setCacheResponding(); 20911051Sandreas.hansson@arm.com } 21011197Sandreas.hansson@arm.com // on ReadExReq we give up our copy unconditionally, 21111197Sandreas.hansson@arm.com // even if this cache is mostly inclusive, we may want 21211197Sandreas.hansson@arm.com // to revisit this 21311197Sandreas.hansson@arm.com invalidateBlock(blk); 21411051Sandreas.hansson@arm.com } else if (blk->isWritable() && !pending_downgrade && 21511284Sandreas.hansson@arm.com !pkt->hasSharers() && 21611051Sandreas.hansson@arm.com pkt->cmd != MemCmd::ReadCleanReq) { 21711284Sandreas.hansson@arm.com // we can give the requester a writable copy on a read 21811284Sandreas.hansson@arm.com // request if: 21911284Sandreas.hansson@arm.com // - we have a writable copy at this level (& below) 22011051Sandreas.hansson@arm.com // - we don't have a pending snoop from below 22111051Sandreas.hansson@arm.com // signaling another read request 22211051Sandreas.hansson@arm.com // - no other cache above has a copy (otherwise it 22311284Sandreas.hansson@arm.com // would have set hasSharers flag when 22411284Sandreas.hansson@arm.com // snooping the packet) 22511284Sandreas.hansson@arm.com // - the read has explicitly asked for a clean 22611284Sandreas.hansson@arm.com // copy of the line 22711051Sandreas.hansson@arm.com if (blk->isDirty()) { 22811051Sandreas.hansson@arm.com // special considerations if we're owner: 22911051Sandreas.hansson@arm.com if (!deferred_response) { 23011284Sandreas.hansson@arm.com // respond with the line in Modified state 23111284Sandreas.hansson@arm.com // (cacheResponding set, hasSharers not set) 23211284Sandreas.hansson@arm.com pkt->setCacheResponding(); 23311197Sandreas.hansson@arm.com 23411284Sandreas.hansson@arm.com if (clusivity == Enums::mostly_excl) { 23511284Sandreas.hansson@arm.com // if this cache is mostly exclusive with 23611284Sandreas.hansson@arm.com // respect to the cache above, drop the 23711284Sandreas.hansson@arm.com // block, no need to first unset the dirty 23811284Sandreas.hansson@arm.com // bit 23911284Sandreas.hansson@arm.com invalidateBlock(blk); 24011284Sandreas.hansson@arm.com } else { 24111284Sandreas.hansson@arm.com // if this cache is mostly inclusive, we 24211284Sandreas.hansson@arm.com // keep the block in the Exclusive state, 24311284Sandreas.hansson@arm.com // and pass it upwards as Modified 24411284Sandreas.hansson@arm.com // (writable and dirty), hence we have 24511284Sandreas.hansson@arm.com // multiple caches, all on the same path 24611284Sandreas.hansson@arm.com // towards memory, all considering the 24711284Sandreas.hansson@arm.com // same block writable, but only one 24811284Sandreas.hansson@arm.com // considering it Modified 24911197Sandreas.hansson@arm.com 25011284Sandreas.hansson@arm.com // we get away with multiple caches (on 25111284Sandreas.hansson@arm.com // the same path to memory) considering 25211284Sandreas.hansson@arm.com // the block writeable as we always enter 25311284Sandreas.hansson@arm.com // the cache hierarchy through a cache, 25411284Sandreas.hansson@arm.com // and first snoop upwards in all other 25511284Sandreas.hansson@arm.com // branches 25611284Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 25711197Sandreas.hansson@arm.com } 25811051Sandreas.hansson@arm.com } else { 25911051Sandreas.hansson@arm.com // if we're responding after our own miss, 26011051Sandreas.hansson@arm.com // there's a window where the recipient didn't 26111051Sandreas.hansson@arm.com // know it was getting ownership and may not 26211051Sandreas.hansson@arm.com // have responded to snoops correctly, so we 26311284Sandreas.hansson@arm.com // have to respond with a shared line 26411284Sandreas.hansson@arm.com pkt->setHasSharers(); 26511051Sandreas.hansson@arm.com } 26611051Sandreas.hansson@arm.com } 26711051Sandreas.hansson@arm.com } else { 26811051Sandreas.hansson@arm.com // otherwise only respond with a shared copy 26911284Sandreas.hansson@arm.com pkt->setHasSharers(); 27011051Sandreas.hansson@arm.com } 27111051Sandreas.hansson@arm.com } 27211051Sandreas.hansson@arm.com } else { 27311284Sandreas.hansson@arm.com // Upgrade or Invalidate 27411051Sandreas.hansson@arm.com assert(pkt->isUpgrade() || pkt->isInvalidate()); 27511197Sandreas.hansson@arm.com 27611197Sandreas.hansson@arm.com // for invalidations we could be looking at the temp block 27711197Sandreas.hansson@arm.com // (for upgrades we always allocate) 27811197Sandreas.hansson@arm.com invalidateBlock(blk); 27911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d (invalidation)\n", 28011051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 28111051Sandreas.hansson@arm.com } 28211051Sandreas.hansson@arm.com} 28311051Sandreas.hansson@arm.com 28411051Sandreas.hansson@arm.com 28511051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 28611051Sandreas.hansson@arm.com// 28711051Sandreas.hansson@arm.com// MSHR helper functions 28811051Sandreas.hansson@arm.com// 28911051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29011051Sandreas.hansson@arm.com 29111051Sandreas.hansson@arm.com 29211051Sandreas.hansson@arm.comvoid 29311284Sandreas.hansson@arm.comCache::markInService(MSHR *mshr, bool pending_modified_resp) 29411051Sandreas.hansson@arm.com{ 29511284Sandreas.hansson@arm.com markInServiceInternal(mshr, pending_modified_resp); 29611051Sandreas.hansson@arm.com} 29711051Sandreas.hansson@arm.com 29811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 29911051Sandreas.hansson@arm.com// 30011051Sandreas.hansson@arm.com// Access path: requests coming in from the CPU side 30111051Sandreas.hansson@arm.com// 30211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 30311051Sandreas.hansson@arm.com 30411051Sandreas.hansson@arm.combool 30511051Sandreas.hansson@arm.comCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 30611051Sandreas.hansson@arm.com PacketList &writebacks) 30711051Sandreas.hansson@arm.com{ 30811051Sandreas.hansson@arm.com // sanity check 30911051Sandreas.hansson@arm.com assert(pkt->isRequest()); 31011051Sandreas.hansson@arm.com 31111051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 31211051Sandreas.hansson@arm.com "Should never see a write in a read-only cache %s\n", 31311051Sandreas.hansson@arm.com name()); 31411051Sandreas.hansson@arm.com 31511051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 31611051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 31711051Sandreas.hansson@arm.com 31811051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 31911051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx uncacheable\n", pkt->cmdString(), 32011051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 32111051Sandreas.hansson@arm.com pkt->getAddr()); 32211051Sandreas.hansson@arm.com 32311051Sandreas.hansson@arm.com // flush and invalidate any existing block 32411051Sandreas.hansson@arm.com CacheBlk *old_blk(tags->findBlock(pkt->getAddr(), pkt->isSecure())); 32511051Sandreas.hansson@arm.com if (old_blk && old_blk->isValid()) { 32611199Sandreas.hansson@arm.com if (old_blk->isDirty() || writebackClean) 32711051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(old_blk)); 32811051Sandreas.hansson@arm.com else 32911051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(old_blk)); 33011051Sandreas.hansson@arm.com tags->invalidate(old_blk); 33111051Sandreas.hansson@arm.com old_blk->invalidate(); 33211051Sandreas.hansson@arm.com } 33311051Sandreas.hansson@arm.com 33411051Sandreas.hansson@arm.com blk = NULL; 33511051Sandreas.hansson@arm.com // lookupLatency is the latency in case the request is uncacheable. 33611051Sandreas.hansson@arm.com lat = lookupLatency; 33711051Sandreas.hansson@arm.com return false; 33811051Sandreas.hansson@arm.com } 33911051Sandreas.hansson@arm.com 34011051Sandreas.hansson@arm.com ContextID id = pkt->req->hasContextId() ? 34111051Sandreas.hansson@arm.com pkt->req->contextId() : InvalidContextID; 34211051Sandreas.hansson@arm.com // Here lat is the value passed as parameter to accessBlock() function 34311051Sandreas.hansson@arm.com // that can modify its value. 34411051Sandreas.hansson@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); 34511051Sandreas.hansson@arm.com 34611051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s addr %#llx size %d (%s) %s\n", pkt->cmdString(), 34711051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 34811051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), pkt->isSecure() ? "s" : "ns", 34911051Sandreas.hansson@arm.com blk ? "hit " + blk->print() : "miss"); 35011051Sandreas.hansson@arm.com 35111051Sandreas.hansson@arm.com 35211199Sandreas.hansson@arm.com if (pkt->isEviction()) { 35311051Sandreas.hansson@arm.com // We check for presence of block in above caches before issuing 35411051Sandreas.hansson@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 35511051Sandreas.hansson@arm.com // possible cases can be of a CleanEvict packet coming from above 35611051Sandreas.hansson@arm.com // encountering a Writeback generated in this cache peer cache and 35711051Sandreas.hansson@arm.com // waiting in the write buffer. Cases of upper level peer caches 35811051Sandreas.hansson@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 35911051Sandreas.hansson@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 36011051Sandreas.hansson@arm.com // by crossbar. 36111051Sandreas.hansson@arm.com std::vector<MSHR *> outgoing; 36211051Sandreas.hansson@arm.com if (writeBuffer.findMatches(pkt->getAddr(), pkt->isSecure(), 36311051Sandreas.hansson@arm.com outgoing)) { 36411051Sandreas.hansson@arm.com assert(outgoing.size() == 1); 36511199Sandreas.hansson@arm.com MSHR *wb_entry = outgoing[0]; 36611199Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 36711199Sandreas.hansson@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 36811199Sandreas.hansson@arm.com assert(wbPkt->isWriteback()); 36911199Sandreas.hansson@arm.com 37011199Sandreas.hansson@arm.com if (pkt->isCleanEviction()) { 37111199Sandreas.hansson@arm.com // The CleanEvict and WritebackClean snoops into other 37211199Sandreas.hansson@arm.com // peer caches of the same level while traversing the 37311199Sandreas.hansson@arm.com // crossbar. If a copy of the block is found, the 37411199Sandreas.hansson@arm.com // packet is deleted in the crossbar. Hence, none of 37511199Sandreas.hansson@arm.com // the other upper level caches connected to this 37611199Sandreas.hansson@arm.com // cache have the block, so we can clear the 37711199Sandreas.hansson@arm.com // BLOCK_CACHED flag in the Writeback if set and 37811199Sandreas.hansson@arm.com // discard the CleanEvict by returning true. 37911199Sandreas.hansson@arm.com wbPkt->clearBlockCached(); 38011199Sandreas.hansson@arm.com return true; 38111199Sandreas.hansson@arm.com } else { 38211199Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 38311199Sandreas.hansson@arm.com // Dirty writeback from above trumps our clean 38411199Sandreas.hansson@arm.com // writeback... discard here 38511199Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 38611199Sandreas.hansson@arm.com markInService(wb_entry, false); 38711199Sandreas.hansson@arm.com delete wbPkt; 38811199Sandreas.hansson@arm.com } 38911051Sandreas.hansson@arm.com } 39011051Sandreas.hansson@arm.com } 39111051Sandreas.hansson@arm.com 39211051Sandreas.hansson@arm.com // Writeback handling is special case. We can write the block into 39311051Sandreas.hansson@arm.com // the cache without having a writeable copy (or any copy at all). 39411199Sandreas.hansson@arm.com if (pkt->isWriteback()) { 39511051Sandreas.hansson@arm.com assert(blkSize == pkt->getSize()); 39611199Sandreas.hansson@arm.com 39711199Sandreas.hansson@arm.com // we could get a clean writeback while we are having 39811199Sandreas.hansson@arm.com // outstanding accesses to a block, do the simple thing for 39911199Sandreas.hansson@arm.com // now and drop the clean writeback so that we do not upset 40011199Sandreas.hansson@arm.com // any ordering/decisions about ownership already taken 40111199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackClean && 40211199Sandreas.hansson@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 40311199Sandreas.hansson@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 40411199Sandreas.hansson@arm.com "dropping\n", pkt->getAddr()); 40511199Sandreas.hansson@arm.com return true; 40611199Sandreas.hansson@arm.com } 40711199Sandreas.hansson@arm.com 40811051Sandreas.hansson@arm.com if (blk == NULL) { 40911051Sandreas.hansson@arm.com // need to do a replacement 41011051Sandreas.hansson@arm.com blk = allocateBlock(pkt->getAddr(), pkt->isSecure(), writebacks); 41111051Sandreas.hansson@arm.com if (blk == NULL) { 41211051Sandreas.hansson@arm.com // no replaceable block available: give up, fwd to next level. 41311051Sandreas.hansson@arm.com incMissCount(pkt); 41411051Sandreas.hansson@arm.com return false; 41511051Sandreas.hansson@arm.com } 41611051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 41711051Sandreas.hansson@arm.com 41811051Sandreas.hansson@arm.com blk->status = (BlkValid | BlkReadable); 41911051Sandreas.hansson@arm.com if (pkt->isSecure()) { 42011051Sandreas.hansson@arm.com blk->status |= BlkSecure; 42111051Sandreas.hansson@arm.com } 42211051Sandreas.hansson@arm.com } 42311199Sandreas.hansson@arm.com // only mark the block dirty if we got a writeback command, 42411199Sandreas.hansson@arm.com // and leave it as is for a clean writeback 42511199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 42611199Sandreas.hansson@arm.com blk->status |= BlkDirty; 42711199Sandreas.hansson@arm.com } 42811284Sandreas.hansson@arm.com // if the packet does not have sharers, it is passing 42911284Sandreas.hansson@arm.com // writable, and we got the writeback in Modified or Exclusive 43011284Sandreas.hansson@arm.com // state, if not we are in the Owned or Shared state 43111284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 43211051Sandreas.hansson@arm.com blk->status |= BlkWritable; 43311051Sandreas.hansson@arm.com } 43411051Sandreas.hansson@arm.com // nothing else to do; writeback doesn't expect response 43511051Sandreas.hansson@arm.com assert(!pkt->needsResponse()); 43611051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 43711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 43811051Sandreas.hansson@arm.com incHitCount(pkt); 43911051Sandreas.hansson@arm.com return true; 44011051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 44111051Sandreas.hansson@arm.com if (blk != NULL) { 44211051Sandreas.hansson@arm.com // Found the block in the tags, need to stop CleanEvict from 44311051Sandreas.hansson@arm.com // propagating further down the hierarchy. Returning true will 44411051Sandreas.hansson@arm.com // treat the CleanEvict like a satisfied write request and delete 44511051Sandreas.hansson@arm.com // it. 44611051Sandreas.hansson@arm.com return true; 44711051Sandreas.hansson@arm.com } 44811051Sandreas.hansson@arm.com // We didn't find the block here, propagate the CleanEvict further 44911051Sandreas.hansson@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 45011051Sandreas.hansson@arm.com // like a Writeback which could not find a replaceable block so has to 45111051Sandreas.hansson@arm.com // go to next level. 45211051Sandreas.hansson@arm.com return false; 45311051Sandreas.hansson@arm.com } else if ((blk != NULL) && 45411284Sandreas.hansson@arm.com (pkt->needsWritable() ? blk->isWritable() : blk->isReadable())) { 45511051Sandreas.hansson@arm.com // OK to satisfy access 45611051Sandreas.hansson@arm.com incHitCount(pkt); 45711051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 45811051Sandreas.hansson@arm.com return true; 45911051Sandreas.hansson@arm.com } 46011051Sandreas.hansson@arm.com 46111051Sandreas.hansson@arm.com // Can't satisfy access normally... either no block (blk == NULL) 46211284Sandreas.hansson@arm.com // or have block but need writable 46311051Sandreas.hansson@arm.com 46411051Sandreas.hansson@arm.com incMissCount(pkt); 46511051Sandreas.hansson@arm.com 46611051Sandreas.hansson@arm.com if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { 46711051Sandreas.hansson@arm.com // complete miss on store conditional... just give up now 46811051Sandreas.hansson@arm.com pkt->req->setExtraData(0); 46911051Sandreas.hansson@arm.com return true; 47011051Sandreas.hansson@arm.com } 47111051Sandreas.hansson@arm.com 47211051Sandreas.hansson@arm.com return false; 47311051Sandreas.hansson@arm.com} 47411051Sandreas.hansson@arm.com 47511051Sandreas.hansson@arm.comvoid 47611051Sandreas.hansson@arm.comCache::doWritebacks(PacketList& writebacks, Tick forward_time) 47711051Sandreas.hansson@arm.com{ 47811051Sandreas.hansson@arm.com while (!writebacks.empty()) { 47911051Sandreas.hansson@arm.com PacketPtr wbPkt = writebacks.front(); 48011051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying writebacks to 48111051Sandreas.hansson@arm.com // write buffer. Call isCachedAbove for both Writebacks and 48211051Sandreas.hansson@arm.com // CleanEvicts. If isCachedAbove returns true we set BLOCK_CACHED flag 48311051Sandreas.hansson@arm.com // in Writebacks and discard CleanEvicts. 48411051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) { 48511051Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::CleanEvict) { 48611051Sandreas.hansson@arm.com // Delete CleanEvict because cached copies exist above. The 48711051Sandreas.hansson@arm.com // packet destructor will delete the request object because 48811051Sandreas.hansson@arm.com // this is a non-snoop request packet which does not require a 48911051Sandreas.hansson@arm.com // response. 49011051Sandreas.hansson@arm.com delete wbPkt; 49111199Sandreas.hansson@arm.com } else if (wbPkt->cmd == MemCmd::WritebackClean) { 49211199Sandreas.hansson@arm.com // clean writeback, do not send since the block is 49311199Sandreas.hansson@arm.com // still cached above 49411199Sandreas.hansson@arm.com assert(writebackClean); 49511199Sandreas.hansson@arm.com delete wbPkt; 49611051Sandreas.hansson@arm.com } else { 49711199Sandreas.hansson@arm.com assert(wbPkt->cmd == MemCmd::WritebackDirty); 49811051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag in Writeback and send below, so that 49911051Sandreas.hansson@arm.com // the Writeback does not reset the bit corresponding to this 50011051Sandreas.hansson@arm.com // address in the snoop filter below. 50111051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 50211051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 50311051Sandreas.hansson@arm.com } 50411051Sandreas.hansson@arm.com } else { 50511051Sandreas.hansson@arm.com // If the block is not cached above, send packet below. Both 50611051Sandreas.hansson@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 50711051Sandreas.hansson@arm.com // reset the bit corresponding to this address in the snoop filter 50811051Sandreas.hansson@arm.com // below. 50911051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 51011051Sandreas.hansson@arm.com } 51111051Sandreas.hansson@arm.com writebacks.pop_front(); 51211051Sandreas.hansson@arm.com } 51311051Sandreas.hansson@arm.com} 51411051Sandreas.hansson@arm.com 51511130Sali.jafri@arm.comvoid 51611130Sali.jafri@arm.comCache::doWritebacksAtomic(PacketList& writebacks) 51711130Sali.jafri@arm.com{ 51811130Sali.jafri@arm.com while (!writebacks.empty()) { 51911130Sali.jafri@arm.com PacketPtr wbPkt = writebacks.front(); 52011130Sali.jafri@arm.com // Call isCachedAbove for both Writebacks and CleanEvicts. If 52111130Sali.jafri@arm.com // isCachedAbove returns true we set BLOCK_CACHED flag in Writebacks 52211130Sali.jafri@arm.com // and discard CleanEvicts. 52311130Sali.jafri@arm.com if (isCachedAbove(wbPkt, false)) { 52411199Sandreas.hansson@arm.com if (wbPkt->cmd == MemCmd::WritebackDirty) { 52511130Sali.jafri@arm.com // Set BLOCK_CACHED flag in Writeback and send below, 52611130Sali.jafri@arm.com // so that the Writeback does not reset the bit 52711130Sali.jafri@arm.com // corresponding to this address in the snoop filter 52811130Sali.jafri@arm.com // below. We can discard CleanEvicts because cached 52911130Sali.jafri@arm.com // copies exist above. Atomic mode isCachedAbove 53011130Sali.jafri@arm.com // modifies packet to set BLOCK_CACHED flag 53111130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 53211130Sali.jafri@arm.com } 53311130Sali.jafri@arm.com } else { 53411130Sali.jafri@arm.com // If the block is not cached above, send packet below. Both 53511130Sali.jafri@arm.com // CleanEvict and Writeback with BLOCK_CACHED flag cleared will 53611130Sali.jafri@arm.com // reset the bit corresponding to this address in the snoop filter 53711130Sali.jafri@arm.com // below. 53811130Sali.jafri@arm.com memSidePort->sendAtomic(wbPkt); 53911130Sali.jafri@arm.com } 54011130Sali.jafri@arm.com writebacks.pop_front(); 54111130Sali.jafri@arm.com // In case of CleanEvicts, the packet destructor will delete the 54211130Sali.jafri@arm.com // request object because this is a non-snoop request packet which 54311130Sali.jafri@arm.com // does not require a response. 54411130Sali.jafri@arm.com delete wbPkt; 54511130Sali.jafri@arm.com } 54611130Sali.jafri@arm.com} 54711130Sali.jafri@arm.com 54811051Sandreas.hansson@arm.com 54911051Sandreas.hansson@arm.comvoid 55011051Sandreas.hansson@arm.comCache::recvTimingSnoopResp(PacketPtr pkt) 55111051Sandreas.hansson@arm.com{ 55211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 55311051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 55411051Sandreas.hansson@arm.com 55511051Sandreas.hansson@arm.com assert(pkt->isResponse()); 55611051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 55711051Sandreas.hansson@arm.com 55811276Sandreas.hansson@arm.com // determine if the response is from a snoop request we created 55911276Sandreas.hansson@arm.com // (in which case it should be in the outstandingSnoop), or if we 56011276Sandreas.hansson@arm.com // merely forwarded someone else's snoop request 56111276Sandreas.hansson@arm.com const bool forwardAsSnoop = outstandingSnoop.find(pkt->req) == 56211276Sandreas.hansson@arm.com outstandingSnoop.end(); 56311276Sandreas.hansson@arm.com 56411276Sandreas.hansson@arm.com if (!forwardAsSnoop) { 56511276Sandreas.hansson@arm.com // the packet came from this cache, so sink it here and do not 56611276Sandreas.hansson@arm.com // forward it 56711051Sandreas.hansson@arm.com assert(pkt->cmd == MemCmd::HardPFResp); 56811276Sandreas.hansson@arm.com 56911276Sandreas.hansson@arm.com outstandingSnoop.erase(pkt->req); 57011276Sandreas.hansson@arm.com 57111276Sandreas.hansson@arm.com DPRINTF(Cache, "Got prefetch response from above for addr " 57211276Sandreas.hansson@arm.com "%#llx (%s)\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 57311051Sandreas.hansson@arm.com recvTimingResp(pkt); 57411051Sandreas.hansson@arm.com return; 57511051Sandreas.hansson@arm.com } 57611051Sandreas.hansson@arm.com 57711051Sandreas.hansson@arm.com // forwardLatency is set here because there is a response from an 57811051Sandreas.hansson@arm.com // upper level cache. 57911051Sandreas.hansson@arm.com // To pay the delay that occurs if the packet comes from the bus, 58011051Sandreas.hansson@arm.com // we charge also headerDelay. 58111051Sandreas.hansson@arm.com Tick snoop_resp_time = clockEdge(forwardLatency) + pkt->headerDelay; 58211051Sandreas.hansson@arm.com // Reset the timing of the packet. 58311051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 58411051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, snoop_resp_time); 58511051Sandreas.hansson@arm.com} 58611051Sandreas.hansson@arm.com 58711051Sandreas.hansson@arm.comvoid 58811051Sandreas.hansson@arm.comCache::promoteWholeLineWrites(PacketPtr pkt) 58911051Sandreas.hansson@arm.com{ 59011051Sandreas.hansson@arm.com // Cache line clearing instructions 59111051Sandreas.hansson@arm.com if (doFastWrites && (pkt->cmd == MemCmd::WriteReq) && 59211051Sandreas.hansson@arm.com (pkt->getSize() == blkSize) && (pkt->getOffset(blkSize) == 0)) { 59311051Sandreas.hansson@arm.com pkt->cmd = MemCmd::WriteLineReq; 59411051Sandreas.hansson@arm.com DPRINTF(Cache, "packet promoted from Write to WriteLineReq\n"); 59511051Sandreas.hansson@arm.com } 59611051Sandreas.hansson@arm.com} 59711051Sandreas.hansson@arm.com 59811051Sandreas.hansson@arm.combool 59911051Sandreas.hansson@arm.comCache::recvTimingReq(PacketPtr pkt) 60011051Sandreas.hansson@arm.com{ 60111051Sandreas.hansson@arm.com DPRINTF(CacheTags, "%s tags: %s\n", __func__, tags->print()); 60211051Sandreas.hansson@arm.com 60311051Sandreas.hansson@arm.com assert(pkt->isRequest()); 60411051Sandreas.hansson@arm.com 60511051Sandreas.hansson@arm.com // Just forward the packet if caches are disabled. 60611051Sandreas.hansson@arm.com if (system->bypassCaches()) { 60711051Sandreas.hansson@arm.com // @todo This should really enqueue the packet rather 60811051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(pkt); 60911051Sandreas.hansson@arm.com assert(success); 61011051Sandreas.hansson@arm.com return true; 61111051Sandreas.hansson@arm.com } 61211051Sandreas.hansson@arm.com 61311051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 61411051Sandreas.hansson@arm.com 61511284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 61611051Sandreas.hansson@arm.com // a cache above us (but not where the packet came from) is 61711284Sandreas.hansson@arm.com // responding to the request, in other words it has the line 61811284Sandreas.hansson@arm.com // in Modified or Owned state 61911284Sandreas.hansson@arm.com DPRINTF(Cache, "Cache above responding to %#llx (%s): " 62011284Sandreas.hansson@arm.com "not responding\n", 62111051Sandreas.hansson@arm.com pkt->getAddr(), pkt->isSecure() ? "s" : "ns"); 62211051Sandreas.hansson@arm.com 62311284Sandreas.hansson@arm.com // if the packet needs the block to be writable, and the cache 62411284Sandreas.hansson@arm.com // that has promised to respond (setting the cache responding 62511284Sandreas.hansson@arm.com // flag) is not providing writable (it is in Owned rather than 62611284Sandreas.hansson@arm.com // the Modified state), we know that there may be other Shared 62711284Sandreas.hansson@arm.com // copies in the system; go out and invalidate them all 62811284Sandreas.hansson@arm.com if (pkt->needsWritable() && !pkt->responderHadWritable()) { 62911284Sandreas.hansson@arm.com // an upstream cache that had the line in Owned state 63011284Sandreas.hansson@arm.com // (dirty, but not writable), is responding and thus 63111284Sandreas.hansson@arm.com // transferring the dirty line from one branch of the 63211284Sandreas.hansson@arm.com // cache hierarchy to another 63311284Sandreas.hansson@arm.com 63411284Sandreas.hansson@arm.com // send out an express snoop and invalidate all other 63511284Sandreas.hansson@arm.com // copies (snooping a packet that needs writable is the 63611284Sandreas.hansson@arm.com // same as an invalidation), thus turning the Owned line 63711284Sandreas.hansson@arm.com // into a Modified line, note that we don't invalidate the 63811284Sandreas.hansson@arm.com // block in the current cache or any other cache on the 63911284Sandreas.hansson@arm.com // path to memory 64011284Sandreas.hansson@arm.com 64111051Sandreas.hansson@arm.com // create a downstream express snoop with cleared packet 64211051Sandreas.hansson@arm.com // flags, there is no need to allocate any data as the 64311051Sandreas.hansson@arm.com // packet is merely used to co-ordinate state transitions 64411051Sandreas.hansson@arm.com Packet *snoop_pkt = new Packet(pkt, true, false); 64511051Sandreas.hansson@arm.com 64611051Sandreas.hansson@arm.com // also reset the bus time that the original packet has 64711051Sandreas.hansson@arm.com // not yet paid for 64811051Sandreas.hansson@arm.com snoop_pkt->headerDelay = snoop_pkt->payloadDelay = 0; 64911051Sandreas.hansson@arm.com 65011051Sandreas.hansson@arm.com // make this an instantaneous express snoop, and let the 65111284Sandreas.hansson@arm.com // other caches in the system know that the another cache 65211284Sandreas.hansson@arm.com // is responding, because we have found the authorative 65311284Sandreas.hansson@arm.com // copy (Modified or Owned) that will supply the right 65411284Sandreas.hansson@arm.com // data 65511051Sandreas.hansson@arm.com snoop_pkt->setExpressSnoop(); 65611284Sandreas.hansson@arm.com snoop_pkt->setCacheResponding(); 65711051Sandreas.hansson@arm.com 65811051Sandreas.hansson@arm.com // this express snoop travels towards the memory, and at 65911051Sandreas.hansson@arm.com // every crossbar it is snooped upwards thus reaching 66011051Sandreas.hansson@arm.com // every cache in the system 66111051Sandreas.hansson@arm.com bool M5_VAR_USED success = memSidePort->sendTimingReq(snoop_pkt); 66211051Sandreas.hansson@arm.com // express snoops always succeed 66311051Sandreas.hansson@arm.com assert(success); 66411051Sandreas.hansson@arm.com 66511284Sandreas.hansson@arm.com // main memory will delete the snoop packet 66611051Sandreas.hansson@arm.com } 66711051Sandreas.hansson@arm.com 66811284Sandreas.hansson@arm.com // queue for deletion, as opposed to immediate deletion, as 66911284Sandreas.hansson@arm.com // the sending cache is still relying on the packet 67011190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 67111051Sandreas.hansson@arm.com 67211284Sandreas.hansson@arm.com // no need to take any action in this particular cache as an 67311284Sandreas.hansson@arm.com // upstream cache has already committed to responding, and 67411284Sandreas.hansson@arm.com // either the packet does not need writable (and we can let 67511284Sandreas.hansson@arm.com // the cache that set the cache responding flag pass on the 67611284Sandreas.hansson@arm.com // line without any need for intervention), or if the packet 67711284Sandreas.hansson@arm.com // needs writable it is provided, or we have already sent out 67811284Sandreas.hansson@arm.com // any express snoops in the section above 67911051Sandreas.hansson@arm.com return true; 68011051Sandreas.hansson@arm.com } 68111051Sandreas.hansson@arm.com 68211051Sandreas.hansson@arm.com // anything that is merely forwarded pays for the forward latency and 68311051Sandreas.hansson@arm.com // the delay provided by the crossbar 68411051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 68511051Sandreas.hansson@arm.com 68611051Sandreas.hansson@arm.com // We use lookupLatency here because it is used to specify the latency 68711051Sandreas.hansson@arm.com // to access. 68811051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 68911051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 69011051Sandreas.hansson@arm.com bool satisfied = false; 69111051Sandreas.hansson@arm.com { 69211051Sandreas.hansson@arm.com PacketList writebacks; 69311051Sandreas.hansson@arm.com // Note that lat is passed by reference here. The function 69411051Sandreas.hansson@arm.com // access() calls accessBlock() which can modify lat value. 69511051Sandreas.hansson@arm.com satisfied = access(pkt, blk, lat, writebacks); 69611051Sandreas.hansson@arm.com 69711051Sandreas.hansson@arm.com // copy writebacks to write buffer here to ensure they logically 69811051Sandreas.hansson@arm.com // proceed anything happening below 69911051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 70011051Sandreas.hansson@arm.com } 70111051Sandreas.hansson@arm.com 70211051Sandreas.hansson@arm.com // Here we charge the headerDelay that takes into account the latencies 70311051Sandreas.hansson@arm.com // of the bus, if the packet comes from it. 70411051Sandreas.hansson@arm.com // The latency charged it is just lat that is the value of lookupLatency 70511051Sandreas.hansson@arm.com // modified by access() function, or if not just lookupLatency. 70611051Sandreas.hansson@arm.com // In case of a hit we are neglecting response latency. 70711051Sandreas.hansson@arm.com // In case of a miss we are neglecting forward latency. 70811051Sandreas.hansson@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 70911051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 71011051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 71111051Sandreas.hansson@arm.com 71211051Sandreas.hansson@arm.com // track time of availability of next prefetch, if any 71311051Sandreas.hansson@arm.com Tick next_pf_time = MaxTick; 71411051Sandreas.hansson@arm.com 71511051Sandreas.hansson@arm.com bool needsResponse = pkt->needsResponse(); 71611051Sandreas.hansson@arm.com 71711051Sandreas.hansson@arm.com if (satisfied) { 71811051Sandreas.hansson@arm.com // should never be satisfying an uncacheable access as we 71911051Sandreas.hansson@arm.com // flush and invalidate any existing block as part of the 72011051Sandreas.hansson@arm.com // lookup 72111051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 72211051Sandreas.hansson@arm.com 72311051Sandreas.hansson@arm.com // hit (for all other request types) 72411051Sandreas.hansson@arm.com 72511051Sandreas.hansson@arm.com if (prefetcher && (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 72611051Sandreas.hansson@arm.com if (blk) 72711051Sandreas.hansson@arm.com blk->status &= ~BlkHWPrefetched; 72811051Sandreas.hansson@arm.com 72911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 73011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 73111051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 73211051Sandreas.hansson@arm.com } 73311051Sandreas.hansson@arm.com 73411051Sandreas.hansson@arm.com if (needsResponse) { 73511051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 73611051Sandreas.hansson@arm.com // @todo: Make someone pay for this 73711051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 73811051Sandreas.hansson@arm.com 73911051Sandreas.hansson@arm.com // In this case we are considering request_time that takes 74011051Sandreas.hansson@arm.com // into account the delay of the xbar, if any, and just 74111051Sandreas.hansson@arm.com // lat, neglecting responseLatency, modelling hit latency 74211051Sandreas.hansson@arm.com // just as lookupLatency or or the value of lat overriden 74311051Sandreas.hansson@arm.com // by access(), that calls accessBlock() function. 74411194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 74511051Sandreas.hansson@arm.com } else { 74611199Sandreas.hansson@arm.com DPRINTF(Cache, "%s satisfied %s addr %#llx, no response needed\n", 74711199Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 74811199Sandreas.hansson@arm.com pkt->getSize()); 74911199Sandreas.hansson@arm.com 75011190Sandreas.hansson@arm.com // queue the packet for deletion, as the sending cache is 75111190Sandreas.hansson@arm.com // still relying on it; if the block is found in access(), 75211190Sandreas.hansson@arm.com // CleanEvict and Writeback messages will be deleted 75311190Sandreas.hansson@arm.com // here as well 75411190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 75511051Sandreas.hansson@arm.com } 75611051Sandreas.hansson@arm.com } else { 75711051Sandreas.hansson@arm.com // miss 75811051Sandreas.hansson@arm.com 75911051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 76011051Sandreas.hansson@arm.com 76111051Sandreas.hansson@arm.com // ignore any existing MSHR if we are dealing with an 76211051Sandreas.hansson@arm.com // uncacheable request 76311051Sandreas.hansson@arm.com MSHR *mshr = pkt->req->isUncacheable() ? nullptr : 76411051Sandreas.hansson@arm.com mshrQueue.findMatch(blk_addr, pkt->isSecure()); 76511051Sandreas.hansson@arm.com 76611051Sandreas.hansson@arm.com // Software prefetch handling: 76711051Sandreas.hansson@arm.com // To keep the core from waiting on data it won't look at 76811051Sandreas.hansson@arm.com // anyway, send back a response with dummy data. Miss handling 76911051Sandreas.hansson@arm.com // will continue asynchronously. Unfortunately, the core will 77011051Sandreas.hansson@arm.com // insist upon freeing original Packet/Request, so we have to 77111051Sandreas.hansson@arm.com // create a new pair with a different lifecycle. Note that this 77211051Sandreas.hansson@arm.com // processing happens before any MSHR munging on the behalf of 77311051Sandreas.hansson@arm.com // this request because this new Request will be the one stored 77411051Sandreas.hansson@arm.com // into the MSHRs, not the original. 77511051Sandreas.hansson@arm.com if (pkt->cmd.isSWPrefetch()) { 77611051Sandreas.hansson@arm.com assert(needsResponse); 77711051Sandreas.hansson@arm.com assert(pkt->req->hasPaddr()); 77811051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 77911051Sandreas.hansson@arm.com 78011051Sandreas.hansson@arm.com // There's no reason to add a prefetch as an additional target 78111051Sandreas.hansson@arm.com // to an existing MSHR. If an outstanding request is already 78211051Sandreas.hansson@arm.com // in progress, there is nothing for the prefetch to do. 78311051Sandreas.hansson@arm.com // If this is the case, we don't even create a request at all. 78411051Sandreas.hansson@arm.com PacketPtr pf = nullptr; 78511051Sandreas.hansson@arm.com 78611051Sandreas.hansson@arm.com if (!mshr) { 78711051Sandreas.hansson@arm.com // copy the request and create a new SoftPFReq packet 78811051Sandreas.hansson@arm.com RequestPtr req = new Request(pkt->req->getPaddr(), 78911051Sandreas.hansson@arm.com pkt->req->getSize(), 79011051Sandreas.hansson@arm.com pkt->req->getFlags(), 79111051Sandreas.hansson@arm.com pkt->req->masterId()); 79211051Sandreas.hansson@arm.com pf = new Packet(req, pkt->cmd); 79311051Sandreas.hansson@arm.com pf->allocate(); 79411051Sandreas.hansson@arm.com assert(pf->getAddr() == pkt->getAddr()); 79511051Sandreas.hansson@arm.com assert(pf->getSize() == pkt->getSize()); 79611051Sandreas.hansson@arm.com } 79711051Sandreas.hansson@arm.com 79811051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 79911051Sandreas.hansson@arm.com // for debugging, set all the bits in the response data 80011051Sandreas.hansson@arm.com // (also keeps valgrind from complaining when debugging settings 80111051Sandreas.hansson@arm.com // print out instruction results) 80211051Sandreas.hansson@arm.com std::memset(pkt->getPtr<uint8_t>(), 0xFF, pkt->getSize()); 80311051Sandreas.hansson@arm.com // request_time is used here, taking into account lat and the delay 80411051Sandreas.hansson@arm.com // charged if the packet comes from the xbar. 80511194Sali.jafri@arm.com cpuSidePort->schedTimingResp(pkt, request_time, true); 80611051Sandreas.hansson@arm.com 80711051Sandreas.hansson@arm.com // If an outstanding request is in progress (we found an 80811051Sandreas.hansson@arm.com // MSHR) this is set to null 80911051Sandreas.hansson@arm.com pkt = pf; 81011051Sandreas.hansson@arm.com } 81111051Sandreas.hansson@arm.com 81211051Sandreas.hansson@arm.com if (mshr) { 81311051Sandreas.hansson@arm.com /// MSHR hit 81411051Sandreas.hansson@arm.com /// @note writebacks will be checked in getNextMSHR() 81511051Sandreas.hansson@arm.com /// for any conflicting requests to the same block 81611051Sandreas.hansson@arm.com 81711051Sandreas.hansson@arm.com //@todo remove hw_pf here 81811051Sandreas.hansson@arm.com 81911051Sandreas.hansson@arm.com // Coalesce unless it was a software prefetch (see above). 82011051Sandreas.hansson@arm.com if (pkt) { 82111199Sandreas.hansson@arm.com assert(!pkt->isWriteback()); 82211199Sandreas.hansson@arm.com // CleanEvicts corresponding to blocks which have 82311199Sandreas.hansson@arm.com // outstanding requests in MSHRs are simply sunk here 82411051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 82511190Sandreas.hansson@arm.com pendingDelete.reset(pkt); 82611051Sandreas.hansson@arm.com } else { 82711051Sandreas.hansson@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s addr %#llx size %d\n", 82811051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), 82911051Sandreas.hansson@arm.com pkt->getSize()); 83011051Sandreas.hansson@arm.com 83111051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 83211051Sandreas.hansson@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 83311051Sandreas.hansson@arm.com // We use forward_time here because it is the same 83411051Sandreas.hansson@arm.com // considering new targets. We have multiple 83511051Sandreas.hansson@arm.com // requests for the same address here. It 83611051Sandreas.hansson@arm.com // specifies the latency to allocate an internal 83711051Sandreas.hansson@arm.com // buffer and to schedule an event to the queued 83811051Sandreas.hansson@arm.com // port and also takes into account the additional 83911051Sandreas.hansson@arm.com // delay of the xbar. 84011197Sandreas.hansson@arm.com mshr->allocateTarget(pkt, forward_time, order++, 84111197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 84211051Sandreas.hansson@arm.com if (mshr->getNumTargets() == numTarget) { 84311051Sandreas.hansson@arm.com noTargetMSHR = mshr; 84411051Sandreas.hansson@arm.com setBlocked(Blocked_NoTargets); 84511051Sandreas.hansson@arm.com // need to be careful with this... if this mshr isn't 84611051Sandreas.hansson@arm.com // ready yet (i.e. time > curTick()), we don't want to 84711051Sandreas.hansson@arm.com // move it ahead of mshrs that are ready 84811051Sandreas.hansson@arm.com // mshrQueue.moveToFront(mshr); 84911051Sandreas.hansson@arm.com } 85011051Sandreas.hansson@arm.com } 85111051Sandreas.hansson@arm.com // We should call the prefetcher reguardless if the request is 85211051Sandreas.hansson@arm.com // satisfied or not, reguardless if the request is in the MSHR or 85311051Sandreas.hansson@arm.com // not. The request could be a ReadReq hit, but still not 85411051Sandreas.hansson@arm.com // satisfied (potentially because of a prior write to the same 85511051Sandreas.hansson@arm.com // cache line. So, even when not satisfied, tehre is an MSHR 85611051Sandreas.hansson@arm.com // already allocated for this, we need to let the prefetcher know 85711051Sandreas.hansson@arm.com // about the request 85811051Sandreas.hansson@arm.com if (prefetcher) { 85911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 86011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 86111051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 86211051Sandreas.hansson@arm.com } 86311051Sandreas.hansson@arm.com } 86411051Sandreas.hansson@arm.com } else { 86511051Sandreas.hansson@arm.com // no MSHR 86611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 86711051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 86811051Sandreas.hansson@arm.com mshr_uncacheable[pkt->cmdToIndex()][pkt->req->masterId()]++; 86911051Sandreas.hansson@arm.com } else { 87011051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 87111051Sandreas.hansson@arm.com } 87211051Sandreas.hansson@arm.com 87311199Sandreas.hansson@arm.com if (pkt->isEviction() || 87411051Sandreas.hansson@arm.com (pkt->req->isUncacheable() && pkt->isWrite())) { 87511051Sandreas.hansson@arm.com // We use forward_time here because there is an 87611051Sandreas.hansson@arm.com // uncached memory write, forwarded to WriteBuffer. 87711051Sandreas.hansson@arm.com allocateWriteBuffer(pkt, forward_time); 87811051Sandreas.hansson@arm.com } else { 87911051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 88011051Sandreas.hansson@arm.com // should have flushed and have no valid block 88111051Sandreas.hansson@arm.com assert(!pkt->req->isUncacheable()); 88211051Sandreas.hansson@arm.com 88311051Sandreas.hansson@arm.com // If we have a write miss to a valid block, we 88411051Sandreas.hansson@arm.com // need to mark the block non-readable. Otherwise 88511051Sandreas.hansson@arm.com // if we allow reads while there's an outstanding 88611051Sandreas.hansson@arm.com // write miss, the read could return stale data 88711051Sandreas.hansson@arm.com // out of the cache block... a more aggressive 88811051Sandreas.hansson@arm.com // system could detect the overlap (if any) and 88911051Sandreas.hansson@arm.com // forward data out of the MSHRs, but we don't do 89011051Sandreas.hansson@arm.com // that yet. Note that we do need to leave the 89111051Sandreas.hansson@arm.com // block valid so that it stays in the cache, in 89211051Sandreas.hansson@arm.com // case we get an upgrade response (and hence no 89311051Sandreas.hansson@arm.com // new data) when the write miss completes. 89411051Sandreas.hansson@arm.com // As long as CPUs do proper store/load forwarding 89511051Sandreas.hansson@arm.com // internally, and have a sufficiently weak memory 89611051Sandreas.hansson@arm.com // model, this is probably unnecessary, but at some 89711051Sandreas.hansson@arm.com // point it must have seemed like we needed it... 89811284Sandreas.hansson@arm.com assert(pkt->needsWritable()); 89911051Sandreas.hansson@arm.com assert(!blk->isWritable()); 90011051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 90111051Sandreas.hansson@arm.com } 90211051Sandreas.hansson@arm.com // Here we are using forward_time, modelling the latency of 90311051Sandreas.hansson@arm.com // a miss (outbound) just as forwardLatency, neglecting the 90411051Sandreas.hansson@arm.com // lookupLatency component. 90511051Sandreas.hansson@arm.com allocateMissBuffer(pkt, forward_time); 90611051Sandreas.hansson@arm.com } 90711051Sandreas.hansson@arm.com 90811051Sandreas.hansson@arm.com if (prefetcher) { 90911051Sandreas.hansson@arm.com // Don't notify on SWPrefetch 91011051Sandreas.hansson@arm.com if (!pkt->cmd.isSWPrefetch()) 91111051Sandreas.hansson@arm.com next_pf_time = prefetcher->notify(pkt); 91211051Sandreas.hansson@arm.com } 91311051Sandreas.hansson@arm.com } 91411051Sandreas.hansson@arm.com } 91511051Sandreas.hansson@arm.com 91611051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 91711051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 91811051Sandreas.hansson@arm.com 91911051Sandreas.hansson@arm.com return true; 92011051Sandreas.hansson@arm.com} 92111051Sandreas.hansson@arm.com 92211051Sandreas.hansson@arm.com 92311051Sandreas.hansson@arm.com// See comment in cache.hh. 92411051Sandreas.hansson@arm.comPacketPtr 92511051Sandreas.hansson@arm.comCache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk, 92611284Sandreas.hansson@arm.com bool needsWritable) const 92711051Sandreas.hansson@arm.com{ 92811051Sandreas.hansson@arm.com bool blkValid = blk && blk->isValid(); 92911051Sandreas.hansson@arm.com 93011051Sandreas.hansson@arm.com if (cpu_pkt->req->isUncacheable()) { 93111051Sandreas.hansson@arm.com // note that at the point we see the uncacheable request we 93211051Sandreas.hansson@arm.com // flush any block, but there could be an outstanding MSHR, 93311051Sandreas.hansson@arm.com // and the cache could have filled again before we actually 93411051Sandreas.hansson@arm.com // send out the forwarded uncacheable request (blk could thus 93511051Sandreas.hansson@arm.com // be non-null) 93611051Sandreas.hansson@arm.com return NULL; 93711051Sandreas.hansson@arm.com } 93811051Sandreas.hansson@arm.com 93911051Sandreas.hansson@arm.com if (!blkValid && 94011051Sandreas.hansson@arm.com (cpu_pkt->isUpgrade() || 94111199Sandreas.hansson@arm.com cpu_pkt->isEviction())) { 94211051Sandreas.hansson@arm.com // Writebacks that weren't allocated in access() and upgrades 94311051Sandreas.hansson@arm.com // from upper-level caches that missed completely just go 94411051Sandreas.hansson@arm.com // through. 94511051Sandreas.hansson@arm.com return NULL; 94611051Sandreas.hansson@arm.com } 94711051Sandreas.hansson@arm.com 94811051Sandreas.hansson@arm.com assert(cpu_pkt->needsResponse()); 94911051Sandreas.hansson@arm.com 95011051Sandreas.hansson@arm.com MemCmd cmd; 95111051Sandreas.hansson@arm.com // @TODO make useUpgrades a parameter. 95211051Sandreas.hansson@arm.com // Note that ownership protocols require upgrade, otherwise a 95311051Sandreas.hansson@arm.com // write miss on a shared owned block will generate a ReadExcl, 95411051Sandreas.hansson@arm.com // which will clobber the owned copy. 95511051Sandreas.hansson@arm.com const bool useUpgrades = true; 95611051Sandreas.hansson@arm.com if (blkValid && useUpgrades) { 95711284Sandreas.hansson@arm.com // only reason to be here is that blk is read only and we need 95811284Sandreas.hansson@arm.com // it to be writable 95911284Sandreas.hansson@arm.com assert(needsWritable); 96011051Sandreas.hansson@arm.com assert(!blk->isWritable()); 96111051Sandreas.hansson@arm.com cmd = cpu_pkt->isLLSC() ? MemCmd::SCUpgradeReq : MemCmd::UpgradeReq; 96211051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::SCUpgradeFailReq || 96311051Sandreas.hansson@arm.com cpu_pkt->cmd == MemCmd::StoreCondFailReq) { 96411051Sandreas.hansson@arm.com // Even though this SC will fail, we still need to send out the 96511051Sandreas.hansson@arm.com // request and get the data to supply it to other snoopers in the case 96611051Sandreas.hansson@arm.com // where the determination the StoreCond fails is delayed due to 96711051Sandreas.hansson@arm.com // all caches not being on the same local bus. 96811051Sandreas.hansson@arm.com cmd = MemCmd::SCUpgradeFailReq; 96911051Sandreas.hansson@arm.com } else if (cpu_pkt->cmd == MemCmd::WriteLineReq) { 97011051Sandreas.hansson@arm.com // forward as invalidate to all other caches, this gives us 97111284Sandreas.hansson@arm.com // the line in Exclusive state, and invalidates all other 97211051Sandreas.hansson@arm.com // copies 97311051Sandreas.hansson@arm.com cmd = MemCmd::InvalidateReq; 97411051Sandreas.hansson@arm.com } else { 97511051Sandreas.hansson@arm.com // block is invalid 97611284Sandreas.hansson@arm.com cmd = needsWritable ? MemCmd::ReadExReq : 97711051Sandreas.hansson@arm.com (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq); 97811051Sandreas.hansson@arm.com } 97911051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize); 98011051Sandreas.hansson@arm.com 98111284Sandreas.hansson@arm.com // if there are upstream caches that have already marked the 98211284Sandreas.hansson@arm.com // packet as having sharers (not passing writable), pass that info 98311284Sandreas.hansson@arm.com // downstream 98411284Sandreas.hansson@arm.com if (cpu_pkt->hasSharers()) { 98511051Sandreas.hansson@arm.com // note that cpu_pkt may have spent a considerable time in the 98611051Sandreas.hansson@arm.com // MSHR queue and that the information could possibly be out 98711051Sandreas.hansson@arm.com // of date, however, there is no harm in conservatively 98811284Sandreas.hansson@arm.com // assuming the block has sharers 98911284Sandreas.hansson@arm.com pkt->setHasSharers(); 99011284Sandreas.hansson@arm.com DPRINTF(Cache, "%s passing hasSharers from %s to %s addr %#llx " 99111284Sandreas.hansson@arm.com "size %d\n", 99211051Sandreas.hansson@arm.com __func__, cpu_pkt->cmdString(), pkt->cmdString(), 99311051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize()); 99411051Sandreas.hansson@arm.com } 99511051Sandreas.hansson@arm.com 99611051Sandreas.hansson@arm.com // the packet should be block aligned 99711051Sandreas.hansson@arm.com assert(pkt->getAddr() == blockAlign(pkt->getAddr())); 99811051Sandreas.hansson@arm.com 99911051Sandreas.hansson@arm.com pkt->allocate(); 100011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created %s from %s for addr %#llx size %d\n", 100111051Sandreas.hansson@arm.com __func__, pkt->cmdString(), cpu_pkt->cmdString(), pkt->getAddr(), 100211051Sandreas.hansson@arm.com pkt->getSize()); 100311051Sandreas.hansson@arm.com return pkt; 100411051Sandreas.hansson@arm.com} 100511051Sandreas.hansson@arm.com 100611051Sandreas.hansson@arm.com 100711051Sandreas.hansson@arm.comTick 100811051Sandreas.hansson@arm.comCache::recvAtomic(PacketPtr pkt) 100911051Sandreas.hansson@arm.com{ 101011051Sandreas.hansson@arm.com // We are in atomic mode so we pay just for lookupLatency here. 101111051Sandreas.hansson@arm.com Cycles lat = lookupLatency; 101211051Sandreas.hansson@arm.com // @TODO: make this a parameter 101311051Sandreas.hansson@arm.com bool last_level_cache = false; 101411051Sandreas.hansson@arm.com 101511051Sandreas.hansson@arm.com // Forward the request if the system is in cache bypass mode. 101611051Sandreas.hansson@arm.com if (system->bypassCaches()) 101711051Sandreas.hansson@arm.com return ticksToCycles(memSidePort->sendAtomic(pkt)); 101811051Sandreas.hansson@arm.com 101911051Sandreas.hansson@arm.com promoteWholeLineWrites(pkt); 102011051Sandreas.hansson@arm.com 102111284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 102211051Sandreas.hansson@arm.com // have to invalidate ourselves and any lower caches even if 102311051Sandreas.hansson@arm.com // upper cache will be responding 102411051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 102511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 102611051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 102711051Sandreas.hansson@arm.com tags->invalidate(blk); 102811051Sandreas.hansson@arm.com blk->invalidate(); 102911284Sandreas.hansson@arm.com DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):" 103011051Sandreas.hansson@arm.com " invalidating\n", 103111051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 103211051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 103311051Sandreas.hansson@arm.com } 103411051Sandreas.hansson@arm.com if (!last_level_cache) { 103511284Sandreas.hansson@arm.com DPRINTF(Cache, "Other cache responding to %s on %#llx (%s):" 103611284Sandreas.hansson@arm.com " forwarding\n", 103711051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), 103811051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 103911051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(pkt)); 104011051Sandreas.hansson@arm.com } 104111051Sandreas.hansson@arm.com } else { 104211284Sandreas.hansson@arm.com DPRINTF(Cache, "Other cache responding to %s on %#llx: " 104311284Sandreas.hansson@arm.com "not responding\n", 104411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 104511051Sandreas.hansson@arm.com } 104611051Sandreas.hansson@arm.com 104711051Sandreas.hansson@arm.com return lat * clockPeriod(); 104811051Sandreas.hansson@arm.com } 104911051Sandreas.hansson@arm.com 105011051Sandreas.hansson@arm.com // should assert here that there are no outstanding MSHRs or 105111051Sandreas.hansson@arm.com // writebacks... that would mean that someone used an atomic 105211051Sandreas.hansson@arm.com // access in timing mode 105311051Sandreas.hansson@arm.com 105411051Sandreas.hansson@arm.com CacheBlk *blk = NULL; 105511051Sandreas.hansson@arm.com PacketList writebacks; 105611051Sandreas.hansson@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 105711051Sandreas.hansson@arm.com 105811051Sandreas.hansson@arm.com // handle writebacks resulting from the access here to ensure they 105911051Sandreas.hansson@arm.com // logically proceed anything happening below 106011130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 106111051Sandreas.hansson@arm.com 106211051Sandreas.hansson@arm.com if (!satisfied) { 106311051Sandreas.hansson@arm.com // MISS 106411051Sandreas.hansson@arm.com 106511284Sandreas.hansson@arm.com PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsWritable()); 106611051Sandreas.hansson@arm.com 106711051Sandreas.hansson@arm.com bool is_forward = (bus_pkt == NULL); 106811051Sandreas.hansson@arm.com 106911051Sandreas.hansson@arm.com if (is_forward) { 107011051Sandreas.hansson@arm.com // just forwarding the same request to the next level 107111051Sandreas.hansson@arm.com // no local cache operation involved 107211051Sandreas.hansson@arm.com bus_pkt = pkt; 107311051Sandreas.hansson@arm.com } 107411051Sandreas.hansson@arm.com 107511051Sandreas.hansson@arm.com DPRINTF(Cache, "Sending an atomic %s for %#llx (%s)\n", 107611051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 107711051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns"); 107811051Sandreas.hansson@arm.com 107911051Sandreas.hansson@arm.com#if TRACING_ON 108011051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 108111051Sandreas.hansson@arm.com#endif 108211051Sandreas.hansson@arm.com 108311051Sandreas.hansson@arm.com lat += ticksToCycles(memSidePort->sendAtomic(bus_pkt)); 108411051Sandreas.hansson@arm.com 108511051Sandreas.hansson@arm.com // We are now dealing with the response handling 108611051Sandreas.hansson@arm.com DPRINTF(Cache, "Receive response: %s for addr %#llx (%s) in state %i\n", 108711051Sandreas.hansson@arm.com bus_pkt->cmdString(), bus_pkt->getAddr(), 108811051Sandreas.hansson@arm.com bus_pkt->isSecure() ? "s" : "ns", 108911051Sandreas.hansson@arm.com old_state); 109011051Sandreas.hansson@arm.com 109111051Sandreas.hansson@arm.com // If packet was a forward, the response (if any) is already 109211051Sandreas.hansson@arm.com // in place in the bus_pkt == pkt structure, so we don't need 109311051Sandreas.hansson@arm.com // to do anything. Otherwise, use the separate bus_pkt to 109411051Sandreas.hansson@arm.com // generate response to pkt and then delete it. 109511051Sandreas.hansson@arm.com if (!is_forward) { 109611051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 109711051Sandreas.hansson@arm.com assert(bus_pkt->isResponse()); 109811051Sandreas.hansson@arm.com if (bus_pkt->isError()) { 109911051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 110011051Sandreas.hansson@arm.com pkt->copyError(bus_pkt); 110111051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::InvalidateReq) { 110211051Sandreas.hansson@arm.com if (blk) { 110311051Sandreas.hansson@arm.com // invalidate response to a cache that received 110411051Sandreas.hansson@arm.com // an invalidate request 110511051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 110611051Sandreas.hansson@arm.com } 110711051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::WriteLineReq) { 110811051Sandreas.hansson@arm.com // note the use of pkt, not bus_pkt here. 110911051Sandreas.hansson@arm.com 111011051Sandreas.hansson@arm.com // write-line request to the cache that promoted 111111051Sandreas.hansson@arm.com // the write to a whole line 111211197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, 111311197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 111411051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 111511051Sandreas.hansson@arm.com } else if (bus_pkt->isRead() || 111611051Sandreas.hansson@arm.com bus_pkt->cmd == MemCmd::UpgradeResp) { 111711051Sandreas.hansson@arm.com // we're updating cache state to allow us to 111811051Sandreas.hansson@arm.com // satisfy the upstream request from the cache 111911197Sandreas.hansson@arm.com blk = handleFill(bus_pkt, blk, writebacks, 112011197Sandreas.hansson@arm.com allocOnFill(pkt->cmd)); 112111051Sandreas.hansson@arm.com satisfyCpuSideRequest(pkt, blk); 112211051Sandreas.hansson@arm.com } else { 112311051Sandreas.hansson@arm.com // we're satisfying the upstream request without 112411051Sandreas.hansson@arm.com // modifying cache state, e.g., a write-through 112511051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 112611051Sandreas.hansson@arm.com } 112711051Sandreas.hansson@arm.com } 112811051Sandreas.hansson@arm.com delete bus_pkt; 112911051Sandreas.hansson@arm.com } 113011051Sandreas.hansson@arm.com } 113111051Sandreas.hansson@arm.com 113211051Sandreas.hansson@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 113311051Sandreas.hansson@arm.com // It's not clear how to do it properly, particularly for 113411051Sandreas.hansson@arm.com // prefetchers that aggressively generate prefetch candidates and 113511051Sandreas.hansson@arm.com // rely on bandwidth contention to throttle them; these will tend 113611051Sandreas.hansson@arm.com // to pollute the cache in atomic mode since there is no bandwidth 113711051Sandreas.hansson@arm.com // contention. If we ever do want to enable prefetching in atomic 113811051Sandreas.hansson@arm.com // mode, though, this is the place to do it... see timingAccess() 113911051Sandreas.hansson@arm.com // for an example (though we'd want to issue the prefetch(es) 114011051Sandreas.hansson@arm.com // immediately rather than calling requestMemSideBus() as we do 114111051Sandreas.hansson@arm.com // there). 114211051Sandreas.hansson@arm.com 114311197Sandreas.hansson@arm.com // do any writebacks resulting from the response handling 114411130Sali.jafri@arm.com doWritebacksAtomic(writebacks); 114511051Sandreas.hansson@arm.com 114611197Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and if so 114711197Sandreas.hansson@arm.com // clear it out, but only do so after the call to recvAtomic is 114811197Sandreas.hansson@arm.com // finished so that any downstream observers (such as a snoop 114911197Sandreas.hansson@arm.com // filter), first see the fill, and only then see the eviction 115011197Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 115111197Sandreas.hansson@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 115211197Sandreas.hansson@arm.com // sequentuially, and we may already have a tempBlock 115311197Sandreas.hansson@arm.com // writeback from the fetch that we have not yet sent 115411197Sandreas.hansson@arm.com if (tempBlockWriteback) { 115511197Sandreas.hansson@arm.com // if that is the case, write the prevoius one back, and 115611197Sandreas.hansson@arm.com // do not schedule any new event 115711197Sandreas.hansson@arm.com writebackTempBlockAtomic(); 115811197Sandreas.hansson@arm.com } else { 115911197Sandreas.hansson@arm.com // the writeback/clean eviction happens after the call to 116011197Sandreas.hansson@arm.com // recvAtomic has finished (but before any successive 116111197Sandreas.hansson@arm.com // calls), so that the response handling from the fill is 116211197Sandreas.hansson@arm.com // allowed to happen first 116311197Sandreas.hansson@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 116411197Sandreas.hansson@arm.com } 116511197Sandreas.hansson@arm.com 116611199Sandreas.hansson@arm.com tempBlockWriteback = (blk->isDirty() || writebackClean) ? 116711199Sandreas.hansson@arm.com writebackBlk(blk) : cleanEvictBlk(blk); 116811197Sandreas.hansson@arm.com blk->invalidate(); 116911197Sandreas.hansson@arm.com } 117011197Sandreas.hansson@arm.com 117111051Sandreas.hansson@arm.com if (pkt->needsResponse()) { 117211051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 117311051Sandreas.hansson@arm.com } 117411051Sandreas.hansson@arm.com 117511051Sandreas.hansson@arm.com return lat * clockPeriod(); 117611051Sandreas.hansson@arm.com} 117711051Sandreas.hansson@arm.com 117811051Sandreas.hansson@arm.com 117911051Sandreas.hansson@arm.comvoid 118011051Sandreas.hansson@arm.comCache::functionalAccess(PacketPtr pkt, bool fromCpuSide) 118111051Sandreas.hansson@arm.com{ 118211051Sandreas.hansson@arm.com if (system->bypassCaches()) { 118311051Sandreas.hansson@arm.com // Packets from the memory side are snoop request and 118411051Sandreas.hansson@arm.com // shouldn't happen in bypass mode. 118511051Sandreas.hansson@arm.com assert(fromCpuSide); 118611051Sandreas.hansson@arm.com 118711051Sandreas.hansson@arm.com // The cache should be flushed if we are in cache bypass mode, 118811051Sandreas.hansson@arm.com // so we don't need to check if we need to update anything. 118911051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 119011051Sandreas.hansson@arm.com return; 119111051Sandreas.hansson@arm.com } 119211051Sandreas.hansson@arm.com 119311051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 119411051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 119511051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 119611051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 119711051Sandreas.hansson@arm.com 119811051Sandreas.hansson@arm.com pkt->pushLabel(name()); 119911051Sandreas.hansson@arm.com 120011051Sandreas.hansson@arm.com CacheBlkPrintWrapper cbpw(blk); 120111051Sandreas.hansson@arm.com 120211051Sandreas.hansson@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 120311051Sandreas.hansson@arm.com // L1 doesn't have a more up-to-date modified copy that still 120411051Sandreas.hansson@arm.com // needs to be found. As a result we always update the request if 120511051Sandreas.hansson@arm.com // we have it, but only declare it satisfied if we are the owner. 120611051Sandreas.hansson@arm.com 120711051Sandreas.hansson@arm.com // see if we have data at all (owned or otherwise) 120811051Sandreas.hansson@arm.com bool have_data = blk && blk->isValid() 120911051Sandreas.hansson@arm.com && pkt->checkFunctional(&cbpw, blk_addr, is_secure, blkSize, 121011051Sandreas.hansson@arm.com blk->data); 121111051Sandreas.hansson@arm.com 121211284Sandreas.hansson@arm.com // data we have is dirty if marked as such or if we have an 121311284Sandreas.hansson@arm.com // in-service MSHR that is pending a modified line 121411051Sandreas.hansson@arm.com bool have_dirty = 121511051Sandreas.hansson@arm.com have_data && (blk->isDirty() || 121611284Sandreas.hansson@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 121711051Sandreas.hansson@arm.com 121811051Sandreas.hansson@arm.com bool done = have_dirty 121911051Sandreas.hansson@arm.com || cpuSidePort->checkFunctional(pkt) 122011051Sandreas.hansson@arm.com || mshrQueue.checkFunctional(pkt, blk_addr) 122111051Sandreas.hansson@arm.com || writeBuffer.checkFunctional(pkt, blk_addr) 122211051Sandreas.hansson@arm.com || memSidePort->checkFunctional(pkt); 122311051Sandreas.hansson@arm.com 122411051Sandreas.hansson@arm.com DPRINTF(Cache, "functional %s %#llx (%s) %s%s%s\n", 122511051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), is_secure ? "s" : "ns", 122611051Sandreas.hansson@arm.com (blk && blk->isValid()) ? "valid " : "", 122711051Sandreas.hansson@arm.com have_data ? "data " : "", done ? "done " : ""); 122811051Sandreas.hansson@arm.com 122911051Sandreas.hansson@arm.com // We're leaving the cache, so pop cache->name() label 123011051Sandreas.hansson@arm.com pkt->popLabel(); 123111051Sandreas.hansson@arm.com 123211051Sandreas.hansson@arm.com if (done) { 123311051Sandreas.hansson@arm.com pkt->makeResponse(); 123411051Sandreas.hansson@arm.com } else { 123511051Sandreas.hansson@arm.com // if it came as a request from the CPU side then make sure it 123611051Sandreas.hansson@arm.com // continues towards the memory side 123711051Sandreas.hansson@arm.com if (fromCpuSide) { 123811051Sandreas.hansson@arm.com memSidePort->sendFunctional(pkt); 123911051Sandreas.hansson@arm.com } else if (forwardSnoops && cpuSidePort->isSnooping()) { 124011051Sandreas.hansson@arm.com // if it came from the memory side, it must be a snoop request 124111051Sandreas.hansson@arm.com // and we should only forward it if we are forwarding snoops 124211051Sandreas.hansson@arm.com cpuSidePort->sendFunctionalSnoop(pkt); 124311051Sandreas.hansson@arm.com } 124411051Sandreas.hansson@arm.com } 124511051Sandreas.hansson@arm.com} 124611051Sandreas.hansson@arm.com 124711051Sandreas.hansson@arm.com 124811051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 124911051Sandreas.hansson@arm.com// 125011051Sandreas.hansson@arm.com// Response handling: responses from the memory side 125111051Sandreas.hansson@arm.com// 125211051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 125311051Sandreas.hansson@arm.com 125411051Sandreas.hansson@arm.com 125511051Sandreas.hansson@arm.comvoid 125611051Sandreas.hansson@arm.comCache::recvTimingResp(PacketPtr pkt) 125711051Sandreas.hansson@arm.com{ 125811051Sandreas.hansson@arm.com assert(pkt->isResponse()); 125911051Sandreas.hansson@arm.com 126011051Sandreas.hansson@arm.com // all header delay should be paid for by the crossbar, unless 126111051Sandreas.hansson@arm.com // this is a prefetch response from above 126211051Sandreas.hansson@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 126311051Sandreas.hansson@arm.com "%s saw a non-zero packet delay\n", name()); 126411051Sandreas.hansson@arm.com 126511051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 126611051Sandreas.hansson@arm.com bool is_error = pkt->isError(); 126711051Sandreas.hansson@arm.com 126811051Sandreas.hansson@arm.com assert(mshr); 126911051Sandreas.hansson@arm.com 127011051Sandreas.hansson@arm.com if (is_error) { 127111051Sandreas.hansson@arm.com DPRINTF(Cache, "Cache received packet with error for addr %#llx (%s), " 127211051Sandreas.hansson@arm.com "cmd: %s\n", pkt->getAddr(), pkt->isSecure() ? "s" : "ns", 127311051Sandreas.hansson@arm.com pkt->cmdString()); 127411051Sandreas.hansson@arm.com } 127511051Sandreas.hansson@arm.com 127611051Sandreas.hansson@arm.com DPRINTF(Cache, "Handling response %s for addr %#llx size %d (%s)\n", 127711051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 127811051Sandreas.hansson@arm.com pkt->isSecure() ? "s" : "ns"); 127911051Sandreas.hansson@arm.com 128011051Sandreas.hansson@arm.com MSHRQueue *mq = mshr->queue; 128111051Sandreas.hansson@arm.com bool wasFull = mq->isFull(); 128211051Sandreas.hansson@arm.com 128311051Sandreas.hansson@arm.com if (mshr == noTargetMSHR) { 128411051Sandreas.hansson@arm.com // we always clear at least one target 128511051Sandreas.hansson@arm.com clearBlocked(Blocked_NoTargets); 128611051Sandreas.hansson@arm.com noTargetMSHR = NULL; 128711051Sandreas.hansson@arm.com } 128811051Sandreas.hansson@arm.com 128911051Sandreas.hansson@arm.com // Initial target is used just for stats 129011051Sandreas.hansson@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 129111051Sandreas.hansson@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 129211051Sandreas.hansson@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 129311051Sandreas.hansson@arm.com PacketList writebacks; 129411051Sandreas.hansson@arm.com // We need forward_time here because we have a call of 129511051Sandreas.hansson@arm.com // allocateWriteBuffer() that need this parameter to specify the 129611051Sandreas.hansson@arm.com // time to request the bus. In this case we use forward latency 129711051Sandreas.hansson@arm.com // because there is a writeback. We pay also here for headerDelay 129811051Sandreas.hansson@arm.com // that is charged of bus latencies if the packet comes from the 129911051Sandreas.hansson@arm.com // bus. 130011051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 130111051Sandreas.hansson@arm.com 130211051Sandreas.hansson@arm.com if (pkt->req->isUncacheable()) { 130311051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 130411051Sandreas.hansson@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 130511051Sandreas.hansson@arm.com miss_latency; 130611051Sandreas.hansson@arm.com } else { 130711051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 130811051Sandreas.hansson@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 130911051Sandreas.hansson@arm.com miss_latency; 131011051Sandreas.hansson@arm.com } 131111051Sandreas.hansson@arm.com 131211284Sandreas.hansson@arm.com // upgrade deferred targets if the response has no sharers, and is 131311284Sandreas.hansson@arm.com // thus passing writable 131411284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 131511284Sandreas.hansson@arm.com mshr->promoteWritable(); 131611177Sandreas.hansson@arm.com } 131711177Sandreas.hansson@arm.com 131811051Sandreas.hansson@arm.com bool is_fill = !mshr->isForward && 131911051Sandreas.hansson@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 132011051Sandreas.hansson@arm.com 132111177Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 132211177Sandreas.hansson@arm.com 132311051Sandreas.hansson@arm.com if (is_fill && !is_error) { 132411051Sandreas.hansson@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 132511051Sandreas.hansson@arm.com pkt->getAddr()); 132611051Sandreas.hansson@arm.com 132711197Sandreas.hansson@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill); 132811051Sandreas.hansson@arm.com assert(blk != NULL); 132911051Sandreas.hansson@arm.com } 133011051Sandreas.hansson@arm.com 133111051Sandreas.hansson@arm.com // allow invalidation responses originating from write-line 133211051Sandreas.hansson@arm.com // requests to be discarded 133311136Sandreas.hansson@arm.com bool is_invalidate = pkt->isInvalidate(); 133411051Sandreas.hansson@arm.com 133511051Sandreas.hansson@arm.com // First offset for critical word first calculations 133611051Sandreas.hansson@arm.com int initial_offset = initial_tgt->pkt->getOffset(blkSize); 133711051Sandreas.hansson@arm.com 133811051Sandreas.hansson@arm.com while (mshr->hasTargets()) { 133911051Sandreas.hansson@arm.com MSHR::Target *target = mshr->getTarget(); 134011051Sandreas.hansson@arm.com Packet *tgt_pkt = target->pkt; 134111051Sandreas.hansson@arm.com 134211051Sandreas.hansson@arm.com switch (target->source) { 134311051Sandreas.hansson@arm.com case MSHR::Target::FromCPU: 134411051Sandreas.hansson@arm.com Tick completion_time; 134511051Sandreas.hansson@arm.com // Here we charge on completion_time the delay of the xbar if the 134611051Sandreas.hansson@arm.com // packet comes from it, charged on headerDelay. 134711051Sandreas.hansson@arm.com completion_time = pkt->headerDelay; 134811051Sandreas.hansson@arm.com 134911051Sandreas.hansson@arm.com // Software prefetch handling for cache closest to core 135011051Sandreas.hansson@arm.com if (tgt_pkt->cmd.isSWPrefetch()) { 135111051Sandreas.hansson@arm.com // a software prefetch would have already been ack'd immediately 135211051Sandreas.hansson@arm.com // with dummy data so the core would be able to retire it. 135311051Sandreas.hansson@arm.com // this request completes right here, so we deallocate it. 135411051Sandreas.hansson@arm.com delete tgt_pkt->req; 135511051Sandreas.hansson@arm.com delete tgt_pkt; 135611051Sandreas.hansson@arm.com break; // skip response 135711051Sandreas.hansson@arm.com } 135811051Sandreas.hansson@arm.com 135911051Sandreas.hansson@arm.com // unlike the other packet flows, where data is found in other 136011051Sandreas.hansson@arm.com // caches or memory and brought back, write-line requests always 136111051Sandreas.hansson@arm.com // have the data right away, so the above check for "is fill?" 136211051Sandreas.hansson@arm.com // cannot actually be determined until examining the stored MSHR 136311051Sandreas.hansson@arm.com // state. We "catch up" with that logic here, which is duplicated 136411051Sandreas.hansson@arm.com // from above. 136511051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::WriteLineReq) { 136611051Sandreas.hansson@arm.com assert(!is_error); 136711284Sandreas.hansson@arm.com // we got the block in a writable state, so promote 136811284Sandreas.hansson@arm.com // any deferred targets if possible 136911284Sandreas.hansson@arm.com mshr->promoteWritable(); 137011051Sandreas.hansson@arm.com // NB: we use the original packet here and not the response! 137111197Sandreas.hansson@arm.com blk = handleFill(tgt_pkt, blk, writebacks, mshr->allocOnFill); 137211051Sandreas.hansson@arm.com assert(blk != NULL); 137311051Sandreas.hansson@arm.com 137411051Sandreas.hansson@arm.com // treat as a fill, and discard the invalidation 137511051Sandreas.hansson@arm.com // response 137611051Sandreas.hansson@arm.com is_fill = true; 137711136Sandreas.hansson@arm.com is_invalidate = false; 137811051Sandreas.hansson@arm.com } 137911051Sandreas.hansson@arm.com 138011051Sandreas.hansson@arm.com if (is_fill) { 138111051Sandreas.hansson@arm.com satisfyCpuSideRequest(tgt_pkt, blk, 138211051Sandreas.hansson@arm.com true, mshr->hasPostDowngrade()); 138311051Sandreas.hansson@arm.com 138411051Sandreas.hansson@arm.com // How many bytes past the first request is this one 138511051Sandreas.hansson@arm.com int transfer_offset = 138611051Sandreas.hansson@arm.com tgt_pkt->getOffset(blkSize) - initial_offset; 138711051Sandreas.hansson@arm.com if (transfer_offset < 0) { 138811051Sandreas.hansson@arm.com transfer_offset += blkSize; 138911051Sandreas.hansson@arm.com } 139011051Sandreas.hansson@arm.com 139111051Sandreas.hansson@arm.com // If not critical word (offset) return payloadDelay. 139211051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 139311051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 139411051Sandreas.hansson@arm.com // the core. 139511051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 139611051Sandreas.hansson@arm.com (transfer_offset ? pkt->payloadDelay : 0); 139711051Sandreas.hansson@arm.com 139811051Sandreas.hansson@arm.com assert(!tgt_pkt->req->isUncacheable()); 139911051Sandreas.hansson@arm.com 140011051Sandreas.hansson@arm.com assert(tgt_pkt->req->masterId() < system->maxMasters()); 140111051Sandreas.hansson@arm.com missLatency[tgt_pkt->cmdToIndex()][tgt_pkt->req->masterId()] += 140211051Sandreas.hansson@arm.com completion_time - target->recvTime; 140311051Sandreas.hansson@arm.com } else if (pkt->cmd == MemCmd::UpgradeFailResp) { 140411051Sandreas.hansson@arm.com // failed StoreCond upgrade 140511051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::StoreCondReq || 140611051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::StoreCondFailReq || 140711051Sandreas.hansson@arm.com tgt_pkt->cmd == MemCmd::SCUpgradeFailReq); 140811051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 140911051Sandreas.hansson@arm.com // from lower level caches/memory to an upper level cache or 141011051Sandreas.hansson@arm.com // the core. 141111051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 141211051Sandreas.hansson@arm.com pkt->payloadDelay; 141311051Sandreas.hansson@arm.com tgt_pkt->req->setExtraData(0); 141411051Sandreas.hansson@arm.com } else { 141511051Sandreas.hansson@arm.com // not a cache fill, just forwarding response 141611051Sandreas.hansson@arm.com // responseLatency is the latency of the return path 141711051Sandreas.hansson@arm.com // from lower level cahces/memory to the core. 141811051Sandreas.hansson@arm.com completion_time += clockEdge(responseLatency) + 141911051Sandreas.hansson@arm.com pkt->payloadDelay; 142011051Sandreas.hansson@arm.com if (pkt->isRead() && !is_error) { 142111051Sandreas.hansson@arm.com // sanity check 142211051Sandreas.hansson@arm.com assert(pkt->getAddr() == tgt_pkt->getAddr()); 142311051Sandreas.hansson@arm.com assert(pkt->getSize() >= tgt_pkt->getSize()); 142411051Sandreas.hansson@arm.com 142511051Sandreas.hansson@arm.com tgt_pkt->setData(pkt->getConstPtr<uint8_t>()); 142611051Sandreas.hansson@arm.com } 142711051Sandreas.hansson@arm.com } 142811051Sandreas.hansson@arm.com tgt_pkt->makeTimingResponse(); 142911051Sandreas.hansson@arm.com // if this packet is an error copy that to the new packet 143011051Sandreas.hansson@arm.com if (is_error) 143111051Sandreas.hansson@arm.com tgt_pkt->copyError(pkt); 143211051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::ReadResp && 143311136Sandreas.hansson@arm.com (is_invalidate || mshr->hasPostInvalidate())) { 143411051Sandreas.hansson@arm.com // If intermediate cache got ReadRespWithInvalidate, 143511051Sandreas.hansson@arm.com // propagate that. Response should not have 143611051Sandreas.hansson@arm.com // isInvalidate() set otherwise. 143711051Sandreas.hansson@arm.com tgt_pkt->cmd = MemCmd::ReadRespWithInvalidate; 143811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s updated cmd to %s for addr %#llx\n", 143911051Sandreas.hansson@arm.com __func__, tgt_pkt->cmdString(), tgt_pkt->getAddr()); 144011051Sandreas.hansson@arm.com } 144111051Sandreas.hansson@arm.com // Reset the bus additional time as it is now accounted for 144211051Sandreas.hansson@arm.com tgt_pkt->headerDelay = tgt_pkt->payloadDelay = 0; 144311194Sali.jafri@arm.com cpuSidePort->schedTimingResp(tgt_pkt, completion_time, true); 144411051Sandreas.hansson@arm.com break; 144511051Sandreas.hansson@arm.com 144611051Sandreas.hansson@arm.com case MSHR::Target::FromPrefetcher: 144711051Sandreas.hansson@arm.com assert(tgt_pkt->cmd == MemCmd::HardPFReq); 144811051Sandreas.hansson@arm.com if (blk) 144911051Sandreas.hansson@arm.com blk->status |= BlkHWPrefetched; 145011051Sandreas.hansson@arm.com delete tgt_pkt->req; 145111051Sandreas.hansson@arm.com delete tgt_pkt; 145211051Sandreas.hansson@arm.com break; 145311051Sandreas.hansson@arm.com 145411051Sandreas.hansson@arm.com case MSHR::Target::FromSnoop: 145511051Sandreas.hansson@arm.com // I don't believe that a snoop can be in an error state 145611051Sandreas.hansson@arm.com assert(!is_error); 145711051Sandreas.hansson@arm.com // response to snoop request 145811051Sandreas.hansson@arm.com DPRINTF(Cache, "processing deferred snoop...\n"); 145911136Sandreas.hansson@arm.com assert(!(is_invalidate && !mshr->hasPostInvalidate())); 146011051Sandreas.hansson@arm.com handleSnoop(tgt_pkt, blk, true, true, mshr->hasPostInvalidate()); 146111051Sandreas.hansson@arm.com break; 146211051Sandreas.hansson@arm.com 146311051Sandreas.hansson@arm.com default: 146411051Sandreas.hansson@arm.com panic("Illegal target->source enum %d\n", target->source); 146511051Sandreas.hansson@arm.com } 146611051Sandreas.hansson@arm.com 146711051Sandreas.hansson@arm.com mshr->popTarget(); 146811051Sandreas.hansson@arm.com } 146911051Sandreas.hansson@arm.com 147011051Sandreas.hansson@arm.com if (blk && blk->isValid()) { 147111051Sandreas.hansson@arm.com // an invalidate response stemming from a write line request 147211051Sandreas.hansson@arm.com // should not invalidate the block, so check if the 147311051Sandreas.hansson@arm.com // invalidation should be discarded 147411136Sandreas.hansson@arm.com if (is_invalidate || mshr->hasPostInvalidate()) { 147511197Sandreas.hansson@arm.com invalidateBlock(blk); 147611051Sandreas.hansson@arm.com } else if (mshr->hasPostDowngrade()) { 147711051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 147811051Sandreas.hansson@arm.com } 147911051Sandreas.hansson@arm.com } 148011051Sandreas.hansson@arm.com 148111051Sandreas.hansson@arm.com if (mshr->promoteDeferredTargets()) { 148211051Sandreas.hansson@arm.com // avoid later read getting stale data while write miss is 148311051Sandreas.hansson@arm.com // outstanding.. see comment in timingAccess() 148411051Sandreas.hansson@arm.com if (blk) { 148511051Sandreas.hansson@arm.com blk->status &= ~BlkReadable; 148611051Sandreas.hansson@arm.com } 148711051Sandreas.hansson@arm.com mq = mshr->queue; 148811051Sandreas.hansson@arm.com mq->markPending(mshr); 148911051Sandreas.hansson@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 149011051Sandreas.hansson@arm.com } else { 149111051Sandreas.hansson@arm.com mq->deallocate(mshr); 149211051Sandreas.hansson@arm.com if (wasFull && !mq->isFull()) { 149311051Sandreas.hansson@arm.com clearBlocked((BlockedCause)mq->index); 149411051Sandreas.hansson@arm.com } 149511051Sandreas.hansson@arm.com 149611051Sandreas.hansson@arm.com // Request the bus for a prefetch if this deallocation freed enough 149711051Sandreas.hansson@arm.com // MSHRs for a prefetch to take place 149811051Sandreas.hansson@arm.com if (prefetcher && mq == &mshrQueue && mshrQueue.canPrefetch()) { 149911051Sandreas.hansson@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 150011051Sandreas.hansson@arm.com clockEdge()); 150111051Sandreas.hansson@arm.com if (next_pf_time != MaxTick) 150211051Sandreas.hansson@arm.com schedMemSideSendEvent(next_pf_time); 150311051Sandreas.hansson@arm.com } 150411051Sandreas.hansson@arm.com } 150511051Sandreas.hansson@arm.com // reset the xbar additional timinig as it is now accounted for 150611051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 150711051Sandreas.hansson@arm.com 150811051Sandreas.hansson@arm.com // copy writebacks to write buffer 150911051Sandreas.hansson@arm.com doWritebacks(writebacks, forward_time); 151011051Sandreas.hansson@arm.com 151111051Sandreas.hansson@arm.com // if we used temp block, check to see if its valid and then clear it out 151211051Sandreas.hansson@arm.com if (blk == tempBlock && tempBlock->isValid()) { 151311051Sandreas.hansson@arm.com // We use forwardLatency here because we are copying 151411051Sandreas.hansson@arm.com // Writebacks/CleanEvicts to write buffer. It specifies the latency to 151511051Sandreas.hansson@arm.com // allocate an internal buffer and to schedule an event to the 151611051Sandreas.hansson@arm.com // queued port. 151711199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 151811051Sandreas.hansson@arm.com PacketPtr wbPkt = writebackBlk(blk); 151911051Sandreas.hansson@arm.com allocateWriteBuffer(wbPkt, forward_time); 152011051Sandreas.hansson@arm.com // Set BLOCK_CACHED flag if cached above. 152111051Sandreas.hansson@arm.com if (isCachedAbove(wbPkt)) 152211051Sandreas.hansson@arm.com wbPkt->setBlockCached(); 152311051Sandreas.hansson@arm.com } else { 152411051Sandreas.hansson@arm.com PacketPtr wcPkt = cleanEvictBlk(blk); 152511051Sandreas.hansson@arm.com // Check to see if block is cached above. If not allocate 152611051Sandreas.hansson@arm.com // write buffer 152711051Sandreas.hansson@arm.com if (isCachedAbove(wcPkt)) 152811051Sandreas.hansson@arm.com delete wcPkt; 152911051Sandreas.hansson@arm.com else 153011051Sandreas.hansson@arm.com allocateWriteBuffer(wcPkt, forward_time); 153111051Sandreas.hansson@arm.com } 153211051Sandreas.hansson@arm.com blk->invalidate(); 153311051Sandreas.hansson@arm.com } 153411051Sandreas.hansson@arm.com 153511051Sandreas.hansson@arm.com DPRINTF(Cache, "Leaving %s with %s for addr %#llx\n", __func__, 153611051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 153711051Sandreas.hansson@arm.com delete pkt; 153811051Sandreas.hansson@arm.com} 153911051Sandreas.hansson@arm.com 154011051Sandreas.hansson@arm.comPacketPtr 154111051Sandreas.hansson@arm.comCache::writebackBlk(CacheBlk *blk) 154211051Sandreas.hansson@arm.com{ 154311199Sandreas.hansson@arm.com chatty_assert(!isReadOnly || writebackClean, 154411199Sandreas.hansson@arm.com "Writeback from read-only cache"); 154511199Sandreas.hansson@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 154611051Sandreas.hansson@arm.com 154711051Sandreas.hansson@arm.com writebacks[Request::wbMasterId]++; 154811051Sandreas.hansson@arm.com 154911199Sandreas.hansson@arm.com Request *req = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), 155011199Sandreas.hansson@arm.com blkSize, 0, Request::wbMasterId); 155111051Sandreas.hansson@arm.com if (blk->isSecure()) 155211199Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 155311051Sandreas.hansson@arm.com 155411199Sandreas.hansson@arm.com req->taskId(blk->task_id); 155511051Sandreas.hansson@arm.com blk->task_id= ContextSwitchTaskId::Unknown; 155611051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 155711051Sandreas.hansson@arm.com 155811199Sandreas.hansson@arm.com PacketPtr pkt = 155911199Sandreas.hansson@arm.com new Packet(req, blk->isDirty() ? 156011199Sandreas.hansson@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 156111199Sandreas.hansson@arm.com 156211199Sandreas.hansson@arm.com DPRINTF(Cache, "Create Writeback %#llx writable: %d, dirty: %d\n", 156311199Sandreas.hansson@arm.com pkt->getAddr(), blk->isWritable(), blk->isDirty()); 156411199Sandreas.hansson@arm.com 156511051Sandreas.hansson@arm.com if (blk->isWritable()) { 156611051Sandreas.hansson@arm.com // not asserting shared means we pass the block in modified 156711051Sandreas.hansson@arm.com // state, mark our own block non-writeable 156811051Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 156911051Sandreas.hansson@arm.com } else { 157011284Sandreas.hansson@arm.com // we are in the Owned state, tell the receiver 157111284Sandreas.hansson@arm.com pkt->setHasSharers(); 157211051Sandreas.hansson@arm.com } 157311051Sandreas.hansson@arm.com 157411199Sandreas.hansson@arm.com // make sure the block is not marked dirty 157511199Sandreas.hansson@arm.com blk->status &= ~BlkDirty; 157611051Sandreas.hansson@arm.com 157711199Sandreas.hansson@arm.com pkt->allocate(); 157811199Sandreas.hansson@arm.com std::memcpy(pkt->getPtr<uint8_t>(), blk->data, blkSize); 157911199Sandreas.hansson@arm.com 158011199Sandreas.hansson@arm.com return pkt; 158111051Sandreas.hansson@arm.com} 158211051Sandreas.hansson@arm.com 158311051Sandreas.hansson@arm.comPacketPtr 158411051Sandreas.hansson@arm.comCache::cleanEvictBlk(CacheBlk *blk) 158511051Sandreas.hansson@arm.com{ 158611199Sandreas.hansson@arm.com assert(!writebackClean); 158711051Sandreas.hansson@arm.com assert(blk && blk->isValid() && !blk->isDirty()); 158811051Sandreas.hansson@arm.com // Creating a zero sized write, a message to the snoop filter 158911051Sandreas.hansson@arm.com Request *req = 159011051Sandreas.hansson@arm.com new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, 159111051Sandreas.hansson@arm.com Request::wbMasterId); 159211051Sandreas.hansson@arm.com if (blk->isSecure()) 159311051Sandreas.hansson@arm.com req->setFlags(Request::SECURE); 159411051Sandreas.hansson@arm.com 159511051Sandreas.hansson@arm.com req->taskId(blk->task_id); 159611051Sandreas.hansson@arm.com blk->task_id = ContextSwitchTaskId::Unknown; 159711051Sandreas.hansson@arm.com blk->tickInserted = curTick(); 159811051Sandreas.hansson@arm.com 159911051Sandreas.hansson@arm.com PacketPtr pkt = new Packet(req, MemCmd::CleanEvict); 160011051Sandreas.hansson@arm.com pkt->allocate(); 160111051Sandreas.hansson@arm.com DPRINTF(Cache, "%s%s %x Create CleanEvict\n", pkt->cmdString(), 160211051Sandreas.hansson@arm.com pkt->req->isInstFetch() ? " (ifetch)" : "", 160311051Sandreas.hansson@arm.com pkt->getAddr()); 160411051Sandreas.hansson@arm.com 160511051Sandreas.hansson@arm.com return pkt; 160611051Sandreas.hansson@arm.com} 160711051Sandreas.hansson@arm.com 160811051Sandreas.hansson@arm.comvoid 160911051Sandreas.hansson@arm.comCache::memWriteback() 161011051Sandreas.hansson@arm.com{ 161111051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::writebackVisitor); 161211051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 161311051Sandreas.hansson@arm.com} 161411051Sandreas.hansson@arm.com 161511051Sandreas.hansson@arm.comvoid 161611051Sandreas.hansson@arm.comCache::memInvalidate() 161711051Sandreas.hansson@arm.com{ 161811051Sandreas.hansson@arm.com CacheBlkVisitorWrapper visitor(*this, &Cache::invalidateVisitor); 161911051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 162011051Sandreas.hansson@arm.com} 162111051Sandreas.hansson@arm.com 162211051Sandreas.hansson@arm.combool 162311051Sandreas.hansson@arm.comCache::isDirty() const 162411051Sandreas.hansson@arm.com{ 162511051Sandreas.hansson@arm.com CacheBlkIsDirtyVisitor visitor; 162611051Sandreas.hansson@arm.com tags->forEachBlk(visitor); 162711051Sandreas.hansson@arm.com 162811051Sandreas.hansson@arm.com return visitor.isDirty(); 162911051Sandreas.hansson@arm.com} 163011051Sandreas.hansson@arm.com 163111051Sandreas.hansson@arm.combool 163211051Sandreas.hansson@arm.comCache::writebackVisitor(CacheBlk &blk) 163311051Sandreas.hansson@arm.com{ 163411051Sandreas.hansson@arm.com if (blk.isDirty()) { 163511051Sandreas.hansson@arm.com assert(blk.isValid()); 163611051Sandreas.hansson@arm.com 163711051Sandreas.hansson@arm.com Request request(tags->regenerateBlkAddr(blk.tag, blk.set), 163811051Sandreas.hansson@arm.com blkSize, 0, Request::funcMasterId); 163911051Sandreas.hansson@arm.com request.taskId(blk.task_id); 164011051Sandreas.hansson@arm.com 164111051Sandreas.hansson@arm.com Packet packet(&request, MemCmd::WriteReq); 164211051Sandreas.hansson@arm.com packet.dataStatic(blk.data); 164311051Sandreas.hansson@arm.com 164411051Sandreas.hansson@arm.com memSidePort->sendFunctional(&packet); 164511051Sandreas.hansson@arm.com 164611051Sandreas.hansson@arm.com blk.status &= ~BlkDirty; 164711051Sandreas.hansson@arm.com } 164811051Sandreas.hansson@arm.com 164911051Sandreas.hansson@arm.com return true; 165011051Sandreas.hansson@arm.com} 165111051Sandreas.hansson@arm.com 165211051Sandreas.hansson@arm.combool 165311051Sandreas.hansson@arm.comCache::invalidateVisitor(CacheBlk &blk) 165411051Sandreas.hansson@arm.com{ 165511051Sandreas.hansson@arm.com 165611051Sandreas.hansson@arm.com if (blk.isDirty()) 165711051Sandreas.hansson@arm.com warn_once("Invalidating dirty cache lines. Expect things to break.\n"); 165811051Sandreas.hansson@arm.com 165911051Sandreas.hansson@arm.com if (blk.isValid()) { 166011051Sandreas.hansson@arm.com assert(!blk.isDirty()); 166111051Sandreas.hansson@arm.com tags->invalidate(&blk); 166211051Sandreas.hansson@arm.com blk.invalidate(); 166311051Sandreas.hansson@arm.com } 166411051Sandreas.hansson@arm.com 166511051Sandreas.hansson@arm.com return true; 166611051Sandreas.hansson@arm.com} 166711051Sandreas.hansson@arm.com 166811051Sandreas.hansson@arm.comCacheBlk* 166911051Sandreas.hansson@arm.comCache::allocateBlock(Addr addr, bool is_secure, PacketList &writebacks) 167011051Sandreas.hansson@arm.com{ 167111051Sandreas.hansson@arm.com CacheBlk *blk = tags->findVictim(addr); 167211051Sandreas.hansson@arm.com 167311051Sandreas.hansson@arm.com // It is valid to return NULL if there is no victim 167411051Sandreas.hansson@arm.com if (!blk) 167511051Sandreas.hansson@arm.com return nullptr; 167611051Sandreas.hansson@arm.com 167711051Sandreas.hansson@arm.com if (blk->isValid()) { 167811051Sandreas.hansson@arm.com Addr repl_addr = tags->regenerateBlkAddr(blk->tag, blk->set); 167911051Sandreas.hansson@arm.com MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 168011051Sandreas.hansson@arm.com if (repl_mshr) { 168111051Sandreas.hansson@arm.com // must be an outstanding upgrade request 168211051Sandreas.hansson@arm.com // on a block we're about to replace... 168311051Sandreas.hansson@arm.com assert(!blk->isWritable() || blk->isDirty()); 168411284Sandreas.hansson@arm.com assert(repl_mshr->needsWritable()); 168511051Sandreas.hansson@arm.com // too hard to replace block with transient state 168611051Sandreas.hansson@arm.com // allocation failed, block not inserted 168711051Sandreas.hansson@arm.com return NULL; 168811051Sandreas.hansson@arm.com } else { 168911051Sandreas.hansson@arm.com DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx (%s): %s\n", 169011051Sandreas.hansson@arm.com repl_addr, blk->isSecure() ? "s" : "ns", 169111051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", 169211051Sandreas.hansson@arm.com blk->isDirty() ? "writeback" : "clean"); 169311051Sandreas.hansson@arm.com 169411051Sandreas.hansson@arm.com // Will send up Writeback/CleanEvict snoops via isCachedAbove 169511051Sandreas.hansson@arm.com // when pushing this writeback list into the write buffer. 169611199Sandreas.hansson@arm.com if (blk->isDirty() || writebackClean) { 169711051Sandreas.hansson@arm.com // Save writeback packet for handling by caller 169811051Sandreas.hansson@arm.com writebacks.push_back(writebackBlk(blk)); 169911051Sandreas.hansson@arm.com } else { 170011051Sandreas.hansson@arm.com writebacks.push_back(cleanEvictBlk(blk)); 170111051Sandreas.hansson@arm.com } 170211051Sandreas.hansson@arm.com } 170311051Sandreas.hansson@arm.com } 170411051Sandreas.hansson@arm.com 170511051Sandreas.hansson@arm.com return blk; 170611051Sandreas.hansson@arm.com} 170711051Sandreas.hansson@arm.com 170811197Sandreas.hansson@arm.comvoid 170911197Sandreas.hansson@arm.comCache::invalidateBlock(CacheBlk *blk) 171011197Sandreas.hansson@arm.com{ 171111197Sandreas.hansson@arm.com if (blk != tempBlock) 171211197Sandreas.hansson@arm.com tags->invalidate(blk); 171311197Sandreas.hansson@arm.com blk->invalidate(); 171411197Sandreas.hansson@arm.com} 171511051Sandreas.hansson@arm.com 171611051Sandreas.hansson@arm.com// Note that the reason we return a list of writebacks rather than 171711051Sandreas.hansson@arm.com// inserting them directly in the write buffer is that this function 171811051Sandreas.hansson@arm.com// is called by both atomic and timing-mode accesses, and in atomic 171911051Sandreas.hansson@arm.com// mode we don't mess with the write buffer (we just perform the 172011051Sandreas.hansson@arm.com// writebacks atomically once the original request is complete). 172111051Sandreas.hansson@arm.comCacheBlk* 172211197Sandreas.hansson@arm.comCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 172311197Sandreas.hansson@arm.com bool allocate) 172411051Sandreas.hansson@arm.com{ 172511051Sandreas.hansson@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 172611051Sandreas.hansson@arm.com Addr addr = pkt->getAddr(); 172711051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 172811051Sandreas.hansson@arm.com#if TRACING_ON 172911051Sandreas.hansson@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 173011051Sandreas.hansson@arm.com#endif 173111051Sandreas.hansson@arm.com 173211051Sandreas.hansson@arm.com // When handling a fill, discard any CleanEvicts for the 173311051Sandreas.hansson@arm.com // same address in write buffer. 173411051Sandreas.hansson@arm.com Addr M5_VAR_USED blk_addr = blockAlign(pkt->getAddr()); 173511051Sandreas.hansson@arm.com std::vector<MSHR *> M5_VAR_USED wbs; 173611051Sandreas.hansson@arm.com assert (!writeBuffer.findMatches(blk_addr, is_secure, wbs)); 173711051Sandreas.hansson@arm.com 173811051Sandreas.hansson@arm.com if (blk == NULL) { 173911051Sandreas.hansson@arm.com // better have read new data... 174011051Sandreas.hansson@arm.com assert(pkt->hasData()); 174111051Sandreas.hansson@arm.com 174211051Sandreas.hansson@arm.com // only read responses and write-line requests have data; 174311051Sandreas.hansson@arm.com // note that we don't write the data here for write-line - that 174411051Sandreas.hansson@arm.com // happens in the subsequent satisfyCpuSideRequest. 174511051Sandreas.hansson@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 174611051Sandreas.hansson@arm.com 174711197Sandreas.hansson@arm.com // need to do a replacement if allocating, otherwise we stick 174811197Sandreas.hansson@arm.com // with the temporary storage 174911197Sandreas.hansson@arm.com blk = allocate ? allocateBlock(addr, is_secure, writebacks) : NULL; 175011197Sandreas.hansson@arm.com 175111051Sandreas.hansson@arm.com if (blk == NULL) { 175211197Sandreas.hansson@arm.com // No replaceable block or a mostly exclusive 175311197Sandreas.hansson@arm.com // cache... just use temporary storage to complete the 175411197Sandreas.hansson@arm.com // current request and then get rid of it 175511051Sandreas.hansson@arm.com assert(!tempBlock->isValid()); 175611051Sandreas.hansson@arm.com blk = tempBlock; 175711051Sandreas.hansson@arm.com tempBlock->set = tags->extractSet(addr); 175811051Sandreas.hansson@arm.com tempBlock->tag = tags->extractTag(addr); 175911051Sandreas.hansson@arm.com // @todo: set security state as well... 176011051Sandreas.hansson@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 176111051Sandreas.hansson@arm.com is_secure ? "s" : "ns"); 176211051Sandreas.hansson@arm.com } else { 176311051Sandreas.hansson@arm.com tags->insertBlock(pkt, blk); 176411051Sandreas.hansson@arm.com } 176511051Sandreas.hansson@arm.com 176611051Sandreas.hansson@arm.com // we should never be overwriting a valid block 176711051Sandreas.hansson@arm.com assert(!blk->isValid()); 176811051Sandreas.hansson@arm.com } else { 176911051Sandreas.hansson@arm.com // existing block... probably an upgrade 177011051Sandreas.hansson@arm.com assert(blk->tag == tags->extractTag(addr)); 177111051Sandreas.hansson@arm.com // either we're getting new data or the block should already be valid 177211051Sandreas.hansson@arm.com assert(pkt->hasData() || blk->isValid()); 177311051Sandreas.hansson@arm.com // don't clear block status... if block is already dirty we 177411051Sandreas.hansson@arm.com // don't want to lose that 177511051Sandreas.hansson@arm.com } 177611051Sandreas.hansson@arm.com 177711051Sandreas.hansson@arm.com if (is_secure) 177811051Sandreas.hansson@arm.com blk->status |= BlkSecure; 177911051Sandreas.hansson@arm.com blk->status |= BlkValid | BlkReadable; 178011051Sandreas.hansson@arm.com 178111137Sandreas.hansson@arm.com // sanity check for whole-line writes, which should always be 178211137Sandreas.hansson@arm.com // marked as writable as part of the fill, and then later marked 178311137Sandreas.hansson@arm.com // dirty as part of satisfyCpuSideRequest 178411137Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 178511284Sandreas.hansson@arm.com assert(!pkt->hasSharers()); 178611137Sandreas.hansson@arm.com // at the moment other caches do not respond to the 178711137Sandreas.hansson@arm.com // invalidation requests corresponding to a whole-line write 178811284Sandreas.hansson@arm.com assert(!pkt->cacheResponding()); 178911137Sandreas.hansson@arm.com } 179011137Sandreas.hansson@arm.com 179111284Sandreas.hansson@arm.com // here we deal with setting the appropriate state of the line, 179211284Sandreas.hansson@arm.com // and we start by looking at the hasSharers flag, and ignore the 179311284Sandreas.hansson@arm.com // cacheResponding flag (normally signalling dirty data) if the 179411284Sandreas.hansson@arm.com // packet has sharers, thus the line is never allocated as Owned 179511284Sandreas.hansson@arm.com // (dirty but not writable), and always ends up being either 179611284Sandreas.hansson@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 179711284Sandreas.hansson@arm.com // for more details 179811284Sandreas.hansson@arm.com if (!pkt->hasSharers()) { 179911284Sandreas.hansson@arm.com // we could get a writable line from memory (rather than a 180011284Sandreas.hansson@arm.com // cache) even in a read-only cache, note that we set this bit 180111284Sandreas.hansson@arm.com // even for a read-only cache, possibly revisit this decision 180211051Sandreas.hansson@arm.com blk->status |= BlkWritable; 180311051Sandreas.hansson@arm.com 180411284Sandreas.hansson@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 180511284Sandreas.hansson@arm.com // cache that had the block in Modified or Owned state) 180611284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 180711284Sandreas.hansson@arm.com // we got the block in Modified state, and invalidated the 180811284Sandreas.hansson@arm.com // owners copy 180911051Sandreas.hansson@arm.com blk->status |= BlkDirty; 181011051Sandreas.hansson@arm.com 181111051Sandreas.hansson@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 181211051Sandreas.hansson@arm.com "in read-only cache %s\n", name()); 181311051Sandreas.hansson@arm.com } 181411051Sandreas.hansson@arm.com } 181511051Sandreas.hansson@arm.com 181611051Sandreas.hansson@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 181711051Sandreas.hansson@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 181811051Sandreas.hansson@arm.com 181911051Sandreas.hansson@arm.com // if we got new data, copy it in (checking for a read response 182011051Sandreas.hansson@arm.com // and a response that has data is the same in the end) 182111051Sandreas.hansson@arm.com if (pkt->isRead()) { 182211051Sandreas.hansson@arm.com // sanity checks 182311051Sandreas.hansson@arm.com assert(pkt->hasData()); 182411051Sandreas.hansson@arm.com assert(pkt->getSize() == blkSize); 182511051Sandreas.hansson@arm.com 182611051Sandreas.hansson@arm.com std::memcpy(blk->data, pkt->getConstPtr<uint8_t>(), blkSize); 182711051Sandreas.hansson@arm.com } 182811051Sandreas.hansson@arm.com // We pay for fillLatency here. 182911051Sandreas.hansson@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 183011051Sandreas.hansson@arm.com pkt->payloadDelay; 183111051Sandreas.hansson@arm.com 183211051Sandreas.hansson@arm.com return blk; 183311051Sandreas.hansson@arm.com} 183411051Sandreas.hansson@arm.com 183511051Sandreas.hansson@arm.com 183611051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 183711051Sandreas.hansson@arm.com// 183811051Sandreas.hansson@arm.com// Snoop path: requests coming in from the memory side 183911051Sandreas.hansson@arm.com// 184011051Sandreas.hansson@arm.com///////////////////////////////////////////////////// 184111051Sandreas.hansson@arm.com 184211051Sandreas.hansson@arm.comvoid 184311051Sandreas.hansson@arm.comCache::doTimingSupplyResponse(PacketPtr req_pkt, const uint8_t *blk_data, 184411051Sandreas.hansson@arm.com bool already_copied, bool pending_inval) 184511051Sandreas.hansson@arm.com{ 184611051Sandreas.hansson@arm.com // sanity check 184711051Sandreas.hansson@arm.com assert(req_pkt->isRequest()); 184811051Sandreas.hansson@arm.com assert(req_pkt->needsResponse()); 184911051Sandreas.hansson@arm.com 185011051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 185111051Sandreas.hansson@arm.com req_pkt->cmdString(), req_pkt->getAddr(), req_pkt->getSize()); 185211051Sandreas.hansson@arm.com // timing-mode snoop responses require a new packet, unless we 185311051Sandreas.hansson@arm.com // already made a copy... 185411051Sandreas.hansson@arm.com PacketPtr pkt = req_pkt; 185511051Sandreas.hansson@arm.com if (!already_copied) 185611051Sandreas.hansson@arm.com // do not clear flags, and allocate space for data if the 185711051Sandreas.hansson@arm.com // packet needs it (the only packets that carry data are read 185811051Sandreas.hansson@arm.com // responses) 185911051Sandreas.hansson@arm.com pkt = new Packet(req_pkt, false, req_pkt->isRead()); 186011051Sandreas.hansson@arm.com 186111051Sandreas.hansson@arm.com assert(req_pkt->req->isUncacheable() || req_pkt->isInvalidate() || 186211284Sandreas.hansson@arm.com pkt->hasSharers()); 186311051Sandreas.hansson@arm.com pkt->makeTimingResponse(); 186411051Sandreas.hansson@arm.com if (pkt->isRead()) { 186511051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk_data, blkSize); 186611051Sandreas.hansson@arm.com } 186711051Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::ReadResp && pending_inval) { 186811051Sandreas.hansson@arm.com // Assume we defer a response to a read from a far-away cache 186911051Sandreas.hansson@arm.com // A, then later defer a ReadExcl from a cache B on the same 187011284Sandreas.hansson@arm.com // bus as us. We'll assert cacheResponding in both cases, but 187111284Sandreas.hansson@arm.com // in the latter case cacheResponding will keep the 187211284Sandreas.hansson@arm.com // invalidation from reaching cache A. This special response 187311284Sandreas.hansson@arm.com // tells cache A that it gets the block to satisfy its read, 187411284Sandreas.hansson@arm.com // but must immediately invalidate it. 187511051Sandreas.hansson@arm.com pkt->cmd = MemCmd::ReadRespWithInvalidate; 187611051Sandreas.hansson@arm.com } 187711051Sandreas.hansson@arm.com // Here we consider forward_time, paying for just forward latency and 187811051Sandreas.hansson@arm.com // also charging the delay provided by the xbar. 187911051Sandreas.hansson@arm.com // forward_time is used as send_time in next allocateWriteBuffer(). 188011051Sandreas.hansson@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 188111051Sandreas.hansson@arm.com // Here we reset the timing of the packet. 188211051Sandreas.hansson@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 188311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s created response: %s addr %#llx size %d tick: %lu\n", 188411051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize(), 188511051Sandreas.hansson@arm.com forward_time); 188611051Sandreas.hansson@arm.com memSidePort->schedTimingSnoopResp(pkt, forward_time, true); 188711051Sandreas.hansson@arm.com} 188811051Sandreas.hansson@arm.com 188911127Sandreas.hansson@arm.comuint32_t 189011051Sandreas.hansson@arm.comCache::handleSnoop(PacketPtr pkt, CacheBlk *blk, bool is_timing, 189111051Sandreas.hansson@arm.com bool is_deferred, bool pending_inval) 189211051Sandreas.hansson@arm.com{ 189311051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 189411051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 189511051Sandreas.hansson@arm.com // deferred snoops can only happen in timing mode 189611051Sandreas.hansson@arm.com assert(!(is_deferred && !is_timing)); 189711051Sandreas.hansson@arm.com // pending_inval only makes sense on deferred snoops 189811051Sandreas.hansson@arm.com assert(!(pending_inval && !is_deferred)); 189911051Sandreas.hansson@arm.com assert(pkt->isRequest()); 190011051Sandreas.hansson@arm.com 190111051Sandreas.hansson@arm.com // the packet may get modified if we or a forwarded snooper 190211051Sandreas.hansson@arm.com // responds in atomic mode, so remember a few things about the 190311051Sandreas.hansson@arm.com // original packet up front 190411051Sandreas.hansson@arm.com bool invalidate = pkt->isInvalidate(); 190511284Sandreas.hansson@arm.com bool M5_VAR_USED needs_writable = pkt->needsWritable(); 190611051Sandreas.hansson@arm.com 190711127Sandreas.hansson@arm.com uint32_t snoop_delay = 0; 190811127Sandreas.hansson@arm.com 190911051Sandreas.hansson@arm.com if (forwardSnoops) { 191011051Sandreas.hansson@arm.com // first propagate snoop upward to see if anyone above us wants to 191111051Sandreas.hansson@arm.com // handle it. save & restore packet src since it will get 191211051Sandreas.hansson@arm.com // rewritten to be relative to cpu-side bus (if any) 191311284Sandreas.hansson@arm.com bool alreadyResponded = pkt->cacheResponding(); 191411051Sandreas.hansson@arm.com if (is_timing) { 191511051Sandreas.hansson@arm.com // copy the packet so that we can clear any flags before 191611051Sandreas.hansson@arm.com // forwarding it upwards, we also allocate data (passing 191711051Sandreas.hansson@arm.com // the pointer along in case of static data), in case 191811051Sandreas.hansson@arm.com // there is a snoop hit in upper levels 191911051Sandreas.hansson@arm.com Packet snoopPkt(pkt, true, true); 192011051Sandreas.hansson@arm.com snoopPkt.setExpressSnoop(); 192111051Sandreas.hansson@arm.com // the snoop packet does not need to wait any additional 192211051Sandreas.hansson@arm.com // time 192311051Sandreas.hansson@arm.com snoopPkt.headerDelay = snoopPkt.payloadDelay = 0; 192411051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoopPkt); 192511127Sandreas.hansson@arm.com 192611127Sandreas.hansson@arm.com // add the header delay (including crossbar and snoop 192711127Sandreas.hansson@arm.com // delays) of the upward snoop to the snoop delay for this 192811127Sandreas.hansson@arm.com // cache 192911127Sandreas.hansson@arm.com snoop_delay += snoopPkt.headerDelay; 193011127Sandreas.hansson@arm.com 193111284Sandreas.hansson@arm.com if (snoopPkt.cacheResponding()) { 193211051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache 193311051Sandreas.hansson@arm.com assert(!alreadyResponded); 193411284Sandreas.hansson@arm.com pkt->setCacheResponding(); 193511051Sandreas.hansson@arm.com } 193611284Sandreas.hansson@arm.com // upstream cache has the block, or has an outstanding 193711284Sandreas.hansson@arm.com // MSHR, pass the flag on 193811284Sandreas.hansson@arm.com if (snoopPkt.hasSharers()) { 193911284Sandreas.hansson@arm.com pkt->setHasSharers(); 194011051Sandreas.hansson@arm.com } 194111051Sandreas.hansson@arm.com // If this request is a prefetch or clean evict and an upper level 194211051Sandreas.hansson@arm.com // signals block present, make sure to propagate the block 194311051Sandreas.hansson@arm.com // presence to the requester. 194411051Sandreas.hansson@arm.com if (snoopPkt.isBlockCached()) { 194511051Sandreas.hansson@arm.com pkt->setBlockCached(); 194611051Sandreas.hansson@arm.com } 194711051Sandreas.hansson@arm.com } else { 194811051Sandreas.hansson@arm.com cpuSidePort->sendAtomicSnoop(pkt); 194911284Sandreas.hansson@arm.com if (!alreadyResponded && pkt->cacheResponding()) { 195011051Sandreas.hansson@arm.com // cache-to-cache response from some upper cache: 195111051Sandreas.hansson@arm.com // forward response to original requester 195211051Sandreas.hansson@arm.com assert(pkt->isResponse()); 195311051Sandreas.hansson@arm.com } 195411051Sandreas.hansson@arm.com } 195511051Sandreas.hansson@arm.com } 195611051Sandreas.hansson@arm.com 195711051Sandreas.hansson@arm.com if (!blk || !blk->isValid()) { 195811051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop miss for %s addr %#llx size %d\n", 195911051Sandreas.hansson@arm.com __func__, pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 196011127Sandreas.hansson@arm.com return snoop_delay; 196111051Sandreas.hansson@arm.com } else { 196211051Sandreas.hansson@arm.com DPRINTF(Cache, "%s snoop hit for %s for addr %#llx size %d, " 196311051Sandreas.hansson@arm.com "old state is %s\n", __func__, pkt->cmdString(), 196411051Sandreas.hansson@arm.com pkt->getAddr(), pkt->getSize(), blk->print()); 196511051Sandreas.hansson@arm.com } 196611051Sandreas.hansson@arm.com 196711051Sandreas.hansson@arm.com chatty_assert(!(isReadOnly && blk->isDirty()), 196811051Sandreas.hansson@arm.com "Should never have a dirty block in a read-only cache %s\n", 196911051Sandreas.hansson@arm.com name()); 197011051Sandreas.hansson@arm.com 197111051Sandreas.hansson@arm.com // We may end up modifying both the block state and the packet (if 197211051Sandreas.hansson@arm.com // we respond in atomic mode), so just figure out what to do now 197311051Sandreas.hansson@arm.com // and then do it later. If we find dirty data while snooping for 197411051Sandreas.hansson@arm.com // an invalidate, we don't need to send a response. The 197511051Sandreas.hansson@arm.com // invalidation itself is taken care of below. 197611051Sandreas.hansson@arm.com bool respond = blk->isDirty() && pkt->needsResponse() && 197711051Sandreas.hansson@arm.com pkt->cmd != MemCmd::InvalidateReq; 197811284Sandreas.hansson@arm.com bool have_writable = blk->isWritable(); 197911051Sandreas.hansson@arm.com 198011051Sandreas.hansson@arm.com // Invalidate any prefetch's from below that would strip write permissions 198111051Sandreas.hansson@arm.com // MemCmd::HardPFReq is only observed by upstream caches. After missing 198211051Sandreas.hansson@arm.com // above and in it's own cache, a new MemCmd::ReadReq is created that 198311051Sandreas.hansson@arm.com // downstream caches observe. 198411051Sandreas.hansson@arm.com if (pkt->mustCheckAbove()) { 198511051Sandreas.hansson@arm.com DPRINTF(Cache, "Found addr %#llx in upper level cache for snoop %s from" 198611051Sandreas.hansson@arm.com " lower cache\n", pkt->getAddr(), pkt->cmdString()); 198711051Sandreas.hansson@arm.com pkt->setBlockCached(); 198811127Sandreas.hansson@arm.com return snoop_delay; 198911051Sandreas.hansson@arm.com } 199011051Sandreas.hansson@arm.com 199111051Sandreas.hansson@arm.com if (!pkt->req->isUncacheable() && pkt->isRead() && !invalidate) { 199211284Sandreas.hansson@arm.com // reading without requiring the line in a writable state, 199311284Sandreas.hansson@arm.com // note that we retain the block as Owned if it is Modified 199411284Sandreas.hansson@arm.com // (dirty data), with the response taken care of below, and 199511284Sandreas.hansson@arm.com // otherwhise simply downgrade from Exclusive to Shared (or 199611284Sandreas.hansson@arm.com // remain in Shared) 199711284Sandreas.hansson@arm.com assert(!needs_writable); 199811284Sandreas.hansson@arm.com pkt->setHasSharers(); 199911081Sandreas.hansson@arm.com blk->status &= ~BlkWritable; 200011051Sandreas.hansson@arm.com } 200111051Sandreas.hansson@arm.com 200211051Sandreas.hansson@arm.com if (respond) { 200311051Sandreas.hansson@arm.com // prevent anyone else from responding, cache as well as 200411051Sandreas.hansson@arm.com // memory, and also prevent any memory from even seeing the 200511284Sandreas.hansson@arm.com // request 200611284Sandreas.hansson@arm.com pkt->setCacheResponding(); 200711284Sandreas.hansson@arm.com if (have_writable) { 200811284Sandreas.hansson@arm.com // inform the cache hierarchy that this cache had the line 200911284Sandreas.hansson@arm.com // in the Modified state so that we avoid unnecessary 201011284Sandreas.hansson@arm.com // invalidations (see Packet::setResponderHadWritable) 201111284Sandreas.hansson@arm.com pkt->setResponderHadWritable(); 201211284Sandreas.hansson@arm.com 201311081Sandreas.hansson@arm.com // in the case of an uncacheable request there is no point 201411284Sandreas.hansson@arm.com // in setting the responderHadWritable flag, but since the 201511284Sandreas.hansson@arm.com // recipient does not care there is no harm in doing so 201611284Sandreas.hansson@arm.com } else { 201711284Sandreas.hansson@arm.com // if the packet has needsWritable set we invalidate our 201811284Sandreas.hansson@arm.com // copy below and all other copies will be invalidates 201911284Sandreas.hansson@arm.com // through express snoops, and if needsWritable is not set 202011284Sandreas.hansson@arm.com // we already called setHasSharers above 202111051Sandreas.hansson@arm.com } 202211284Sandreas.hansson@arm.com 202311051Sandreas.hansson@arm.com if (is_timing) { 202411051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, blk->data, is_deferred, pending_inval); 202511051Sandreas.hansson@arm.com } else { 202611051Sandreas.hansson@arm.com pkt->makeAtomicResponse(); 202711051Sandreas.hansson@arm.com pkt->setDataFromBlock(blk->data, blkSize); 202811051Sandreas.hansson@arm.com } 202911051Sandreas.hansson@arm.com } 203011051Sandreas.hansson@arm.com 203111051Sandreas.hansson@arm.com if (!respond && is_timing && is_deferred) { 203211271Sandreas.hansson@arm.com // if it's a deferred timing snoop to which we are not 203311271Sandreas.hansson@arm.com // responding, then we've made a copy of both the request and 203411271Sandreas.hansson@arm.com // the packet, delete them here 203511051Sandreas.hansson@arm.com assert(pkt->needsResponse()); 203611051Sandreas.hansson@arm.com delete pkt->req; 203711051Sandreas.hansson@arm.com delete pkt; 203811051Sandreas.hansson@arm.com } 203911051Sandreas.hansson@arm.com 204011051Sandreas.hansson@arm.com // Do this last in case it deallocates block data or something 204111051Sandreas.hansson@arm.com // like that 204211051Sandreas.hansson@arm.com if (invalidate) { 204311197Sandreas.hansson@arm.com invalidateBlock(blk); 204411051Sandreas.hansson@arm.com } 204511051Sandreas.hansson@arm.com 204611051Sandreas.hansson@arm.com DPRINTF(Cache, "new state is %s\n", blk->print()); 204711127Sandreas.hansson@arm.com 204811127Sandreas.hansson@arm.com return snoop_delay; 204911051Sandreas.hansson@arm.com} 205011051Sandreas.hansson@arm.com 205111051Sandreas.hansson@arm.com 205211051Sandreas.hansson@arm.comvoid 205311051Sandreas.hansson@arm.comCache::recvTimingSnoopReq(PacketPtr pkt) 205411051Sandreas.hansson@arm.com{ 205511051Sandreas.hansson@arm.com DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__, 205611051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr(), pkt->getSize()); 205711051Sandreas.hansson@arm.com 205811051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 205911051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 206011051Sandreas.hansson@arm.com 206111130Sali.jafri@arm.com // no need to snoop requests that are not in range 206211051Sandreas.hansson@arm.com if (!inRange(pkt->getAddr())) { 206311051Sandreas.hansson@arm.com return; 206411051Sandreas.hansson@arm.com } 206511051Sandreas.hansson@arm.com 206611051Sandreas.hansson@arm.com bool is_secure = pkt->isSecure(); 206711051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 206811051Sandreas.hansson@arm.com 206911051Sandreas.hansson@arm.com Addr blk_addr = blockAlign(pkt->getAddr()); 207011051Sandreas.hansson@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 207111051Sandreas.hansson@arm.com 207211127Sandreas.hansson@arm.com // Update the latency cost of the snoop so that the crossbar can 207311127Sandreas.hansson@arm.com // account for it. Do not overwrite what other neighbouring caches 207411127Sandreas.hansson@arm.com // have already done, rather take the maximum. The update is 207511127Sandreas.hansson@arm.com // tentative, for cases where we return before an upward snoop 207611127Sandreas.hansson@arm.com // happens below. 207711127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, 207811127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 207911127Sandreas.hansson@arm.com 208011051Sandreas.hansson@arm.com // Inform request(Prefetch, CleanEvict or Writeback) from below of 208111051Sandreas.hansson@arm.com // MSHR hit, set setBlockCached. 208211051Sandreas.hansson@arm.com if (mshr && pkt->mustCheckAbove()) { 208311051Sandreas.hansson@arm.com DPRINTF(Cache, "Setting block cached for %s from" 208411051Sandreas.hansson@arm.com "lower cache on mshr hit %#x\n", 208511051Sandreas.hansson@arm.com pkt->cmdString(), pkt->getAddr()); 208611051Sandreas.hansson@arm.com pkt->setBlockCached(); 208711051Sandreas.hansson@arm.com return; 208811051Sandreas.hansson@arm.com } 208911051Sandreas.hansson@arm.com 209011051Sandreas.hansson@arm.com // Let the MSHR itself track the snoop and decide whether we want 209111051Sandreas.hansson@arm.com // to go ahead and do the regular cache snoop 209211051Sandreas.hansson@arm.com if (mshr && mshr->handleSnoop(pkt, order++)) { 209311051Sandreas.hansson@arm.com DPRINTF(Cache, "Deferring snoop on in-service MSHR to blk %#llx (%s)." 209411051Sandreas.hansson@arm.com "mshrs: %s\n", blk_addr, is_secure ? "s" : "ns", 209511051Sandreas.hansson@arm.com mshr->print()); 209611051Sandreas.hansson@arm.com 209711051Sandreas.hansson@arm.com if (mshr->getNumTargets() > numTarget) 209811051Sandreas.hansson@arm.com warn("allocating bonus target for snoop"); //handle later 209911051Sandreas.hansson@arm.com return; 210011051Sandreas.hansson@arm.com } 210111051Sandreas.hansson@arm.com 210211051Sandreas.hansson@arm.com //We also need to check the writeback buffers and handle those 210311051Sandreas.hansson@arm.com std::vector<MSHR *> writebacks; 210411051Sandreas.hansson@arm.com if (writeBuffer.findMatches(blk_addr, is_secure, writebacks)) { 210511051Sandreas.hansson@arm.com DPRINTF(Cache, "Snoop hit in writeback to addr %#llx (%s)\n", 210611051Sandreas.hansson@arm.com pkt->getAddr(), is_secure ? "s" : "ns"); 210711051Sandreas.hansson@arm.com 210811051Sandreas.hansson@arm.com // Look through writebacks for any cachable writes. 210911051Sandreas.hansson@arm.com // We should only ever find a single match 211011051Sandreas.hansson@arm.com assert(writebacks.size() == 1); 211111051Sandreas.hansson@arm.com MSHR *wb_entry = writebacks[0]; 211211051Sandreas.hansson@arm.com // Expect to see only Writebacks and/or CleanEvicts here, both of 211311051Sandreas.hansson@arm.com // which should not be generated for uncacheable data. 211411051Sandreas.hansson@arm.com assert(!wb_entry->isUncacheable()); 211511051Sandreas.hansson@arm.com // There should only be a single request responsible for generating 211611051Sandreas.hansson@arm.com // Writebacks/CleanEvicts. 211711051Sandreas.hansson@arm.com assert(wb_entry->getNumTargets() == 1); 211811051Sandreas.hansson@arm.com PacketPtr wb_pkt = wb_entry->getTarget()->pkt; 211911199Sandreas.hansson@arm.com assert(wb_pkt->isEviction()); 212011051Sandreas.hansson@arm.com 212111199Sandreas.hansson@arm.com if (pkt->isEviction()) { 212211051Sandreas.hansson@arm.com // if the block is found in the write queue, set the BLOCK_CACHED 212311051Sandreas.hansson@arm.com // flag for Writeback/CleanEvict snoop. On return the snoop will 212411051Sandreas.hansson@arm.com // propagate the BLOCK_CACHED flag in Writeback packets and prevent 212511051Sandreas.hansson@arm.com // any CleanEvicts from travelling down the memory hierarchy. 212611051Sandreas.hansson@arm.com pkt->setBlockCached(); 212711051Sandreas.hansson@arm.com DPRINTF(Cache, "Squashing %s from lower cache on writequeue hit" 212811051Sandreas.hansson@arm.com " %#x\n", pkt->cmdString(), pkt->getAddr()); 212911051Sandreas.hansson@arm.com return; 213011051Sandreas.hansson@arm.com } 213111051Sandreas.hansson@arm.com 213211199Sandreas.hansson@arm.com if (wb_pkt->cmd == MemCmd::WritebackDirty) { 213311284Sandreas.hansson@arm.com // we have dirty data, and so will proceed to respond 213411284Sandreas.hansson@arm.com pkt->setCacheResponding(); 213511284Sandreas.hansson@arm.com if (!pkt->needsWritable()) { 213611284Sandreas.hansson@arm.com // the packet should end up in the Shared state (non 213711284Sandreas.hansson@arm.com // writable) on the completion of the fill 213811284Sandreas.hansson@arm.com pkt->setHasSharers(); 213911284Sandreas.hansson@arm.com // similarly, the writeback is no longer passing 214011284Sandreas.hansson@arm.com // writeable (the receiving cache should consider the 214111284Sandreas.hansson@arm.com // block Owned rather than Modified) 214211284Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 214311051Sandreas.hansson@arm.com } else { 214411284Sandreas.hansson@arm.com // we need to invalidate our copy. we do that 214511284Sandreas.hansson@arm.com // below. 214611051Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 214711051Sandreas.hansson@arm.com } 214811051Sandreas.hansson@arm.com doTimingSupplyResponse(pkt, wb_pkt->getConstPtr<uint8_t>(), 214911051Sandreas.hansson@arm.com false, false); 215011051Sandreas.hansson@arm.com } else { 215111199Sandreas.hansson@arm.com // on hitting a clean writeback we play it safe and do not 215211199Sandreas.hansson@arm.com // provide a response, the block may be dirty somewhere 215311199Sandreas.hansson@arm.com // else 215411199Sandreas.hansson@arm.com assert(wb_pkt->isCleanEviction()); 215511051Sandreas.hansson@arm.com // The cache technically holds the block until the 215611199Sandreas.hansson@arm.com // corresponding message reaches the crossbar 215711051Sandreas.hansson@arm.com // below. Therefore when a snoop encounters a CleanEvict 215811284Sandreas.hansson@arm.com // or WritebackClean message we must call 215911284Sandreas.hansson@arm.com // setHasSharers (just like when it encounters a 216011284Sandreas.hansson@arm.com // Writeback) to avoid the snoop filter prematurely 216111284Sandreas.hansson@arm.com // clearing the holder bit in the crossbar below 216211284Sandreas.hansson@arm.com if (!pkt->needsWritable()) { 216311284Sandreas.hansson@arm.com pkt->setHasSharers(); 216411284Sandreas.hansson@arm.com // the writeback is no longer passing writeable (the 216511284Sandreas.hansson@arm.com // receiving cache should consider the block Owned 216611284Sandreas.hansson@arm.com // rather than Modified) 216711284Sandreas.hansson@arm.com wb_pkt->setHasSharers(); 216811199Sandreas.hansson@arm.com } else { 216911051Sandreas.hansson@arm.com assert(pkt->isInvalidate()); 217011199Sandreas.hansson@arm.com } 217111051Sandreas.hansson@arm.com } 217211051Sandreas.hansson@arm.com 217311051Sandreas.hansson@arm.com if (pkt->isInvalidate()) { 217411051Sandreas.hansson@arm.com // Invalidation trumps our writeback... discard here 217511051Sandreas.hansson@arm.com // Note: markInService will remove entry from writeback buffer. 217611051Sandreas.hansson@arm.com markInService(wb_entry, false); 217711051Sandreas.hansson@arm.com delete wb_pkt; 217811051Sandreas.hansson@arm.com } 217911051Sandreas.hansson@arm.com } 218011051Sandreas.hansson@arm.com 218111051Sandreas.hansson@arm.com // If this was a shared writeback, there may still be 218211051Sandreas.hansson@arm.com // other shared copies above that require invalidation. 218311051Sandreas.hansson@arm.com // We could be more selective and return here if the 218411051Sandreas.hansson@arm.com // request is non-exclusive or if the writeback is 218511051Sandreas.hansson@arm.com // exclusive. 218611127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, true, false, false); 218711127Sandreas.hansson@arm.com 218811127Sandreas.hansson@arm.com // Override what we did when we first saw the snoop, as we now 218911127Sandreas.hansson@arm.com // also have the cost of the upwards snoops to account for 219011127Sandreas.hansson@arm.com pkt->snoopDelay = std::max<uint32_t>(pkt->snoopDelay, snoop_delay + 219111127Sandreas.hansson@arm.com lookupLatency * clockPeriod()); 219211051Sandreas.hansson@arm.com} 219311051Sandreas.hansson@arm.com 219411051Sandreas.hansson@arm.combool 219511051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 219611051Sandreas.hansson@arm.com{ 219711051Sandreas.hansson@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 219811051Sandreas.hansson@arm.com cache->recvTimingSnoopResp(pkt); 219911051Sandreas.hansson@arm.com return true; 220011051Sandreas.hansson@arm.com} 220111051Sandreas.hansson@arm.com 220211051Sandreas.hansson@arm.comTick 220311051Sandreas.hansson@arm.comCache::recvAtomicSnoop(PacketPtr pkt) 220411051Sandreas.hansson@arm.com{ 220511051Sandreas.hansson@arm.com // Snoops shouldn't happen when bypassing caches 220611051Sandreas.hansson@arm.com assert(!system->bypassCaches()); 220711051Sandreas.hansson@arm.com 220811130Sali.jafri@arm.com // no need to snoop requests that are not in range. 220911130Sali.jafri@arm.com if (!inRange(pkt->getAddr())) { 221011051Sandreas.hansson@arm.com return 0; 221111051Sandreas.hansson@arm.com } 221211051Sandreas.hansson@arm.com 221311051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 221411127Sandreas.hansson@arm.com uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false); 221511127Sandreas.hansson@arm.com return snoop_delay + lookupLatency * clockPeriod(); 221611051Sandreas.hansson@arm.com} 221711051Sandreas.hansson@arm.com 221811051Sandreas.hansson@arm.com 221911051Sandreas.hansson@arm.comMSHR * 222011051Sandreas.hansson@arm.comCache::getNextMSHR() 222111051Sandreas.hansson@arm.com{ 222211051Sandreas.hansson@arm.com // Check both MSHR queue and write buffer for potential requests, 222311051Sandreas.hansson@arm.com // note that null does not mean there is no request, it could 222411051Sandreas.hansson@arm.com // simply be that it is not ready 222511051Sandreas.hansson@arm.com MSHR *miss_mshr = mshrQueue.getNextMSHR(); 222611051Sandreas.hansson@arm.com MSHR *write_mshr = writeBuffer.getNextMSHR(); 222711051Sandreas.hansson@arm.com 222811051Sandreas.hansson@arm.com // If we got a write buffer request ready, first priority is a 222911051Sandreas.hansson@arm.com // full write buffer, otherwhise we favour the miss requests 223011051Sandreas.hansson@arm.com if (write_mshr && 223111051Sandreas.hansson@arm.com ((writeBuffer.isFull() && writeBuffer.inServiceEntries == 0) || 223211051Sandreas.hansson@arm.com !miss_mshr)) { 223311051Sandreas.hansson@arm.com // need to search MSHR queue for conflicting earlier miss. 223411051Sandreas.hansson@arm.com MSHR *conflict_mshr = 223511051Sandreas.hansson@arm.com mshrQueue.findPending(write_mshr->blkAddr, 223611051Sandreas.hansson@arm.com write_mshr->isSecure); 223711051Sandreas.hansson@arm.com 223811051Sandreas.hansson@arm.com if (conflict_mshr && conflict_mshr->order < write_mshr->order) { 223911051Sandreas.hansson@arm.com // Service misses in order until conflict is cleared. 224011051Sandreas.hansson@arm.com return conflict_mshr; 224111051Sandreas.hansson@arm.com 224211051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 224311051Sandreas.hansson@arm.com } 224411051Sandreas.hansson@arm.com 224511051Sandreas.hansson@arm.com // No conflicts; issue write 224611051Sandreas.hansson@arm.com return write_mshr; 224711051Sandreas.hansson@arm.com } else if (miss_mshr) { 224811051Sandreas.hansson@arm.com // need to check for conflicting earlier writeback 224911051Sandreas.hansson@arm.com MSHR *conflict_mshr = 225011051Sandreas.hansson@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 225111051Sandreas.hansson@arm.com miss_mshr->isSecure); 225211051Sandreas.hansson@arm.com if (conflict_mshr) { 225311051Sandreas.hansson@arm.com // not sure why we don't check order here... it was in the 225411051Sandreas.hansson@arm.com // original code but commented out. 225511051Sandreas.hansson@arm.com 225611051Sandreas.hansson@arm.com // The only way this happens is if we are 225711051Sandreas.hansson@arm.com // doing a write and we didn't have permissions 225811051Sandreas.hansson@arm.com // then subsequently saw a writeback (owned got evicted) 225911051Sandreas.hansson@arm.com // We need to make sure to perform the writeback first 226011051Sandreas.hansson@arm.com // To preserve the dirty data, then we can issue the write 226111051Sandreas.hansson@arm.com 226211051Sandreas.hansson@arm.com // should we return write_mshr here instead? I.e. do we 226311051Sandreas.hansson@arm.com // have to flush writes in order? I don't think so... not 226411051Sandreas.hansson@arm.com // for Alpha anyway. Maybe for x86? 226511051Sandreas.hansson@arm.com return conflict_mshr; 226611051Sandreas.hansson@arm.com 226711051Sandreas.hansson@arm.com // @todo Note that we ignore the ready time of the conflict here 226811051Sandreas.hansson@arm.com } 226911051Sandreas.hansson@arm.com 227011051Sandreas.hansson@arm.com // No conflicts; issue read 227111051Sandreas.hansson@arm.com return miss_mshr; 227211051Sandreas.hansson@arm.com } 227311051Sandreas.hansson@arm.com 227411051Sandreas.hansson@arm.com // fall through... no pending requests. Try a prefetch. 227511051Sandreas.hansson@arm.com assert(!miss_mshr && !write_mshr); 227611051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 227711051Sandreas.hansson@arm.com // If we have a miss queue slot, we can try a prefetch 227811051Sandreas.hansson@arm.com PacketPtr pkt = prefetcher->getPacket(); 227911051Sandreas.hansson@arm.com if (pkt) { 228011051Sandreas.hansson@arm.com Addr pf_addr = blockAlign(pkt->getAddr()); 228111051Sandreas.hansson@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 228211051Sandreas.hansson@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 228311051Sandreas.hansson@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 228411051Sandreas.hansson@arm.com // Update statistic on number of prefetches issued 228511051Sandreas.hansson@arm.com // (hwpf_mshr_misses) 228611051Sandreas.hansson@arm.com assert(pkt->req->masterId() < system->maxMasters()); 228711051Sandreas.hansson@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 228811051Sandreas.hansson@arm.com 228911051Sandreas.hansson@arm.com // allocate an MSHR and return it, note 229011051Sandreas.hansson@arm.com // that we send the packet straight away, so do not 229111051Sandreas.hansson@arm.com // schedule the send 229211051Sandreas.hansson@arm.com return allocateMissBuffer(pkt, curTick(), false); 229311051Sandreas.hansson@arm.com } else { 229411051Sandreas.hansson@arm.com // free the request and packet 229511051Sandreas.hansson@arm.com delete pkt->req; 229611051Sandreas.hansson@arm.com delete pkt; 229711051Sandreas.hansson@arm.com } 229811051Sandreas.hansson@arm.com } 229911051Sandreas.hansson@arm.com } 230011051Sandreas.hansson@arm.com 230111051Sandreas.hansson@arm.com return NULL; 230211051Sandreas.hansson@arm.com} 230311051Sandreas.hansson@arm.com 230411051Sandreas.hansson@arm.combool 230511130Sali.jafri@arm.comCache::isCachedAbove(PacketPtr pkt, bool is_timing) const 230611051Sandreas.hansson@arm.com{ 230711051Sandreas.hansson@arm.com if (!forwardSnoops) 230811051Sandreas.hansson@arm.com return false; 230911051Sandreas.hansson@arm.com // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and 231011051Sandreas.hansson@arm.com // Writeback snoops into upper level caches to check for copies of the 231111051Sandreas.hansson@arm.com // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict 231211051Sandreas.hansson@arm.com // packet, the cache can inform the crossbar below of presence or absence 231311051Sandreas.hansson@arm.com // of the block. 231411130Sali.jafri@arm.com if (is_timing) { 231511130Sali.jafri@arm.com Packet snoop_pkt(pkt, true, false); 231611130Sali.jafri@arm.com snoop_pkt.setExpressSnoop(); 231711130Sali.jafri@arm.com // Assert that packet is either Writeback or CleanEvict and not a 231811130Sali.jafri@arm.com // prefetch request because prefetch requests need an MSHR and may 231911130Sali.jafri@arm.com // generate a snoop response. 232011199Sandreas.hansson@arm.com assert(pkt->isEviction()); 232111130Sali.jafri@arm.com snoop_pkt.senderState = NULL; 232211130Sali.jafri@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 232311130Sali.jafri@arm.com // Writeback/CleanEvict snoops do not generate a snoop response. 232411284Sandreas.hansson@arm.com assert(!(snoop_pkt.cacheResponding())); 232511130Sali.jafri@arm.com return snoop_pkt.isBlockCached(); 232611130Sali.jafri@arm.com } else { 232711130Sali.jafri@arm.com cpuSidePort->sendAtomicSnoop(pkt); 232811130Sali.jafri@arm.com return pkt->isBlockCached(); 232911130Sali.jafri@arm.com } 233011051Sandreas.hansson@arm.com} 233111051Sandreas.hansson@arm.com 233211051Sandreas.hansson@arm.comPacketPtr 233311051Sandreas.hansson@arm.comCache::getTimingPacket() 233411051Sandreas.hansson@arm.com{ 233511051Sandreas.hansson@arm.com MSHR *mshr = getNextMSHR(); 233611051Sandreas.hansson@arm.com 233711051Sandreas.hansson@arm.com if (mshr == NULL) { 233811051Sandreas.hansson@arm.com return NULL; 233911051Sandreas.hansson@arm.com } 234011051Sandreas.hansson@arm.com 234111051Sandreas.hansson@arm.com // use request from 1st target 234211051Sandreas.hansson@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 234311051Sandreas.hansson@arm.com PacketPtr pkt = NULL; 234411051Sandreas.hansson@arm.com 234511051Sandreas.hansson@arm.com DPRINTF(CachePort, "%s %s for addr %#llx size %d\n", __func__, 234611051Sandreas.hansson@arm.com tgt_pkt->cmdString(), tgt_pkt->getAddr(), tgt_pkt->getSize()); 234711051Sandreas.hansson@arm.com 234811051Sandreas.hansson@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 234911051Sandreas.hansson@arm.com 235011051Sandreas.hansson@arm.com if (tgt_pkt->cmd == MemCmd::HardPFReq && forwardSnoops) { 235111051Sandreas.hansson@arm.com // We need to check the caches above us to verify that 235211051Sandreas.hansson@arm.com // they don't have a copy of this block in the dirty state 235311051Sandreas.hansson@arm.com // at the moment. Without this check we could get a stale 235411051Sandreas.hansson@arm.com // copy from memory that might get used in place of the 235511051Sandreas.hansson@arm.com // dirty one. 235611051Sandreas.hansson@arm.com Packet snoop_pkt(tgt_pkt, true, false); 235711051Sandreas.hansson@arm.com snoop_pkt.setExpressSnoop(); 235811275Sandreas.hansson@arm.com // We are sending this packet upwards, but if it hits we will 235911275Sandreas.hansson@arm.com // get a snoop response that we end up treating just like a 236011275Sandreas.hansson@arm.com // normal response, hence it needs the MSHR as its sender 236111275Sandreas.hansson@arm.com // state 236211051Sandreas.hansson@arm.com snoop_pkt.senderState = mshr; 236311051Sandreas.hansson@arm.com cpuSidePort->sendTimingSnoopReq(&snoop_pkt); 236411051Sandreas.hansson@arm.com 236511051Sandreas.hansson@arm.com // Check to see if the prefetch was squashed by an upper cache (to 236611051Sandreas.hansson@arm.com // prevent us from grabbing the line) or if a Check to see if a 236711051Sandreas.hansson@arm.com // writeback arrived between the time the prefetch was placed in 236811051Sandreas.hansson@arm.com // the MSHRs and when it was selected to be sent or if the 236911051Sandreas.hansson@arm.com // prefetch was squashed by an upper cache. 237011051Sandreas.hansson@arm.com 237111284Sandreas.hansson@arm.com // It is important to check cacheResponding before 237211284Sandreas.hansson@arm.com // prefetchSquashed. If another cache has committed to 237311284Sandreas.hansson@arm.com // responding, it will be sending a dirty response which will 237411284Sandreas.hansson@arm.com // arrive at the MSHR allocated for this request. Checking the 237511284Sandreas.hansson@arm.com // prefetchSquash first may result in the MSHR being 237611284Sandreas.hansson@arm.com // prematurely deallocated. 237711284Sandreas.hansson@arm.com if (snoop_pkt.cacheResponding()) { 237811276Sandreas.hansson@arm.com auto M5_VAR_USED r = outstandingSnoop.insert(snoop_pkt.req); 237911276Sandreas.hansson@arm.com assert(r.second); 238011284Sandreas.hansson@arm.com 238111284Sandreas.hansson@arm.com // if we are getting a snoop response with no sharers it 238211284Sandreas.hansson@arm.com // will be allocated as Modified 238311284Sandreas.hansson@arm.com bool pending_modified_resp = !snoop_pkt.hasSharers(); 238411284Sandreas.hansson@arm.com markInService(mshr, pending_modified_resp); 238511284Sandreas.hansson@arm.com 238611051Sandreas.hansson@arm.com DPRINTF(Cache, "Upward snoop of prefetch for addr" 238711051Sandreas.hansson@arm.com " %#x (%s) hit\n", 238811051Sandreas.hansson@arm.com tgt_pkt->getAddr(), tgt_pkt->isSecure()? "s": "ns"); 238911051Sandreas.hansson@arm.com return NULL; 239011051Sandreas.hansson@arm.com } 239111051Sandreas.hansson@arm.com 239211051Sandreas.hansson@arm.com if (snoop_pkt.isBlockCached() || blk != NULL) { 239311051Sandreas.hansson@arm.com DPRINTF(Cache, "Block present, prefetch squashed by cache. " 239411051Sandreas.hansson@arm.com "Deallocating mshr target %#x.\n", 239511051Sandreas.hansson@arm.com mshr->blkAddr); 239611051Sandreas.hansson@arm.com // Deallocate the mshr target 239711277Sandreas.hansson@arm.com if (mshr->queue->forceDeallocateTarget(mshr)) { 239811277Sandreas.hansson@arm.com // Clear block if this deallocation resulted freed an 239911277Sandreas.hansson@arm.com // mshr when all had previously been utilized 240011277Sandreas.hansson@arm.com clearBlocked((BlockedCause)(mshr->queue->index)); 240111051Sandreas.hansson@arm.com } 240211277Sandreas.hansson@arm.com return NULL; 240311051Sandreas.hansson@arm.com } 240411051Sandreas.hansson@arm.com } 240511051Sandreas.hansson@arm.com 240611051Sandreas.hansson@arm.com if (mshr->isForwardNoResponse()) { 240711051Sandreas.hansson@arm.com // no response expected, just forward packet as it is 240811051Sandreas.hansson@arm.com assert(tags->findBlock(mshr->blkAddr, mshr->isSecure) == NULL); 240911051Sandreas.hansson@arm.com pkt = tgt_pkt; 241011051Sandreas.hansson@arm.com } else { 241111284Sandreas.hansson@arm.com pkt = getBusPacket(tgt_pkt, blk, mshr->needsWritable()); 241211051Sandreas.hansson@arm.com 241311051Sandreas.hansson@arm.com mshr->isForward = (pkt == NULL); 241411051Sandreas.hansson@arm.com 241511051Sandreas.hansson@arm.com if (mshr->isForward) { 241611051Sandreas.hansson@arm.com // not a cache block request, but a response is expected 241711051Sandreas.hansson@arm.com // make copy of current packet to forward, keep current 241811051Sandreas.hansson@arm.com // copy for response handling 241911051Sandreas.hansson@arm.com pkt = new Packet(tgt_pkt, false, true); 242011051Sandreas.hansson@arm.com if (pkt->isWrite()) { 242111051Sandreas.hansson@arm.com pkt->setData(tgt_pkt->getConstPtr<uint8_t>()); 242211051Sandreas.hansson@arm.com } 242311051Sandreas.hansson@arm.com } 242411051Sandreas.hansson@arm.com } 242511051Sandreas.hansson@arm.com 242611051Sandreas.hansson@arm.com assert(pkt != NULL); 242711275Sandreas.hansson@arm.com // play it safe and append (rather than set) the sender state, as 242811275Sandreas.hansson@arm.com // forwarded packets may already have existing state 242911275Sandreas.hansson@arm.com pkt->pushSenderState(mshr); 243011051Sandreas.hansson@arm.com return pkt; 243111051Sandreas.hansson@arm.com} 243211051Sandreas.hansson@arm.com 243311051Sandreas.hansson@arm.com 243411051Sandreas.hansson@arm.comTick 243511051Sandreas.hansson@arm.comCache::nextMSHRReadyTime() const 243611051Sandreas.hansson@arm.com{ 243711051Sandreas.hansson@arm.com Tick nextReady = std::min(mshrQueue.nextMSHRReadyTime(), 243811051Sandreas.hansson@arm.com writeBuffer.nextMSHRReadyTime()); 243911051Sandreas.hansson@arm.com 244011051Sandreas.hansson@arm.com // Don't signal prefetch ready time if no MSHRs available 244111051Sandreas.hansson@arm.com // Will signal once enoguh MSHRs are deallocated 244211051Sandreas.hansson@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 244311051Sandreas.hansson@arm.com nextReady = std::min(nextReady, 244411051Sandreas.hansson@arm.com prefetcher->nextPrefetchReadyTime()); 244511051Sandreas.hansson@arm.com } 244611051Sandreas.hansson@arm.com 244711051Sandreas.hansson@arm.com return nextReady; 244811051Sandreas.hansson@arm.com} 244911051Sandreas.hansson@arm.com 245011051Sandreas.hansson@arm.comvoid 245111051Sandreas.hansson@arm.comCache::serialize(CheckpointOut &cp) const 245211051Sandreas.hansson@arm.com{ 245311051Sandreas.hansson@arm.com bool dirty(isDirty()); 245411051Sandreas.hansson@arm.com 245511051Sandreas.hansson@arm.com if (dirty) { 245611051Sandreas.hansson@arm.com warn("*** The cache still contains dirty data. ***\n"); 245711051Sandreas.hansson@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 245811051Sandreas.hansson@arm.com warn(" This checkpoint will not restore correctly and dirty data in " 245911051Sandreas.hansson@arm.com "the cache will be lost!\n"); 246011051Sandreas.hansson@arm.com } 246111051Sandreas.hansson@arm.com 246211051Sandreas.hansson@arm.com // Since we don't checkpoint the data in the cache, any dirty data 246311051Sandreas.hansson@arm.com // will be lost when restoring from a checkpoint of a system that 246411051Sandreas.hansson@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 246511051Sandreas.hansson@arm.com // cache contains dirty data. 246611051Sandreas.hansson@arm.com bool bad_checkpoint(dirty); 246711051Sandreas.hansson@arm.com SERIALIZE_SCALAR(bad_checkpoint); 246811051Sandreas.hansson@arm.com} 246911051Sandreas.hansson@arm.com 247011051Sandreas.hansson@arm.comvoid 247111051Sandreas.hansson@arm.comCache::unserialize(CheckpointIn &cp) 247211051Sandreas.hansson@arm.com{ 247311051Sandreas.hansson@arm.com bool bad_checkpoint; 247411051Sandreas.hansson@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 247511051Sandreas.hansson@arm.com if (bad_checkpoint) { 247611051Sandreas.hansson@arm.com fatal("Restoring from checkpoints with dirty caches is not supported " 247711051Sandreas.hansson@arm.com "in the classic memory system. Please remove any caches or " 247811051Sandreas.hansson@arm.com " drain them properly before taking checkpoints.\n"); 247911051Sandreas.hansson@arm.com } 248011051Sandreas.hansson@arm.com} 248111051Sandreas.hansson@arm.com 248211051Sandreas.hansson@arm.com/////////////// 248311051Sandreas.hansson@arm.com// 248411051Sandreas.hansson@arm.com// CpuSidePort 248511051Sandreas.hansson@arm.com// 248611051Sandreas.hansson@arm.com/////////////// 248711051Sandreas.hansson@arm.com 248811051Sandreas.hansson@arm.comAddrRangeList 248911051Sandreas.hansson@arm.comCache::CpuSidePort::getAddrRanges() const 249011051Sandreas.hansson@arm.com{ 249111051Sandreas.hansson@arm.com return cache->getAddrRanges(); 249211051Sandreas.hansson@arm.com} 249311051Sandreas.hansson@arm.com 249411051Sandreas.hansson@arm.combool 249511051Sandreas.hansson@arm.comCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 249611051Sandreas.hansson@arm.com{ 249711051Sandreas.hansson@arm.com assert(!cache->system->bypassCaches()); 249811051Sandreas.hansson@arm.com 249911051Sandreas.hansson@arm.com bool success = false; 250011051Sandreas.hansson@arm.com 250111284Sandreas.hansson@arm.com // always let packets through if an upstream cache has committed 250211284Sandreas.hansson@arm.com // to responding, even if blocked (we should technically look at 250311284Sandreas.hansson@arm.com // the isExpressSnoop flag, but it is set by the cache itself, and 250411284Sandreas.hansson@arm.com // consequently we have to rely on the cacheResponding flag) 250511284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 250611051Sandreas.hansson@arm.com // do not change the current retry state 250711051Sandreas.hansson@arm.com bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt); 250811051Sandreas.hansson@arm.com assert(bypass_success); 250911051Sandreas.hansson@arm.com return true; 251011051Sandreas.hansson@arm.com } else if (blocked || mustSendRetry) { 251111051Sandreas.hansson@arm.com // either already committed to send a retry, or blocked 251211051Sandreas.hansson@arm.com success = false; 251311051Sandreas.hansson@arm.com } else { 251411051Sandreas.hansson@arm.com // pass it on to the cache, and let the cache decide if we 251511051Sandreas.hansson@arm.com // have to retry or not 251611051Sandreas.hansson@arm.com success = cache->recvTimingReq(pkt); 251711051Sandreas.hansson@arm.com } 251811051Sandreas.hansson@arm.com 251911051Sandreas.hansson@arm.com // remember if we have to retry 252011051Sandreas.hansson@arm.com mustSendRetry = !success; 252111051Sandreas.hansson@arm.com return success; 252211051Sandreas.hansson@arm.com} 252311051Sandreas.hansson@arm.com 252411051Sandreas.hansson@arm.comTick 252511051Sandreas.hansson@arm.comCache::CpuSidePort::recvAtomic(PacketPtr pkt) 252611051Sandreas.hansson@arm.com{ 252711051Sandreas.hansson@arm.com return cache->recvAtomic(pkt); 252811051Sandreas.hansson@arm.com} 252911051Sandreas.hansson@arm.com 253011051Sandreas.hansson@arm.comvoid 253111051Sandreas.hansson@arm.comCache::CpuSidePort::recvFunctional(PacketPtr pkt) 253211051Sandreas.hansson@arm.com{ 253311051Sandreas.hansson@arm.com // functional request 253411051Sandreas.hansson@arm.com cache->functionalAccess(pkt, true); 253511051Sandreas.hansson@arm.com} 253611051Sandreas.hansson@arm.com 253711051Sandreas.hansson@arm.comCache:: 253811051Sandreas.hansson@arm.comCpuSidePort::CpuSidePort(const std::string &_name, Cache *_cache, 253911051Sandreas.hansson@arm.com const std::string &_label) 254011051Sandreas.hansson@arm.com : BaseCache::CacheSlavePort(_name, _cache, _label), cache(_cache) 254111051Sandreas.hansson@arm.com{ 254211051Sandreas.hansson@arm.com} 254311051Sandreas.hansson@arm.com 254411053Sandreas.hansson@arm.comCache* 254511053Sandreas.hansson@arm.comCacheParams::create() 254611053Sandreas.hansson@arm.com{ 254711053Sandreas.hansson@arm.com assert(tags); 254811053Sandreas.hansson@arm.com 254911053Sandreas.hansson@arm.com return new Cache(this); 255011053Sandreas.hansson@arm.com} 255111051Sandreas.hansson@arm.com/////////////// 255211051Sandreas.hansson@arm.com// 255311051Sandreas.hansson@arm.com// MemSidePort 255411051Sandreas.hansson@arm.com// 255511051Sandreas.hansson@arm.com/////////////// 255611051Sandreas.hansson@arm.com 255711051Sandreas.hansson@arm.combool 255811051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingResp(PacketPtr pkt) 255911051Sandreas.hansson@arm.com{ 256011051Sandreas.hansson@arm.com cache->recvTimingResp(pkt); 256111051Sandreas.hansson@arm.com return true; 256211051Sandreas.hansson@arm.com} 256311051Sandreas.hansson@arm.com 256411051Sandreas.hansson@arm.com// Express snooping requests to memside port 256511051Sandreas.hansson@arm.comvoid 256611051Sandreas.hansson@arm.comCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 256711051Sandreas.hansson@arm.com{ 256811051Sandreas.hansson@arm.com // handle snooping requests 256911051Sandreas.hansson@arm.com cache->recvTimingSnoopReq(pkt); 257011051Sandreas.hansson@arm.com} 257111051Sandreas.hansson@arm.com 257211051Sandreas.hansson@arm.comTick 257311051Sandreas.hansson@arm.comCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 257411051Sandreas.hansson@arm.com{ 257511051Sandreas.hansson@arm.com return cache->recvAtomicSnoop(pkt); 257611051Sandreas.hansson@arm.com} 257711051Sandreas.hansson@arm.com 257811051Sandreas.hansson@arm.comvoid 257911051Sandreas.hansson@arm.comCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 258011051Sandreas.hansson@arm.com{ 258111051Sandreas.hansson@arm.com // functional snoop (note that in contrast to atomic we don't have 258211051Sandreas.hansson@arm.com // a specific functionalSnoop method, as they have the same 258311051Sandreas.hansson@arm.com // behaviour regardless) 258411051Sandreas.hansson@arm.com cache->functionalAccess(pkt, false); 258511051Sandreas.hansson@arm.com} 258611051Sandreas.hansson@arm.com 258711051Sandreas.hansson@arm.comvoid 258811051Sandreas.hansson@arm.comCache::CacheReqPacketQueue::sendDeferredPacket() 258911051Sandreas.hansson@arm.com{ 259011051Sandreas.hansson@arm.com // sanity check 259111051Sandreas.hansson@arm.com assert(!waitingOnRetry); 259211051Sandreas.hansson@arm.com 259311051Sandreas.hansson@arm.com // there should never be any deferred request packets in the 259411051Sandreas.hansson@arm.com // queue, instead we resly on the cache to provide the packets 259511051Sandreas.hansson@arm.com // from the MSHR queue or write queue 259611051Sandreas.hansson@arm.com assert(deferredPacketReadyTime() == MaxTick); 259711051Sandreas.hansson@arm.com 259811051Sandreas.hansson@arm.com // check for request packets (requests & writebacks) 259911051Sandreas.hansson@arm.com PacketPtr pkt = cache.getTimingPacket(); 260011051Sandreas.hansson@arm.com if (pkt == NULL) { 260111051Sandreas.hansson@arm.com // can happen if e.g. we attempt a writeback and fail, but 260211051Sandreas.hansson@arm.com // before the retry, the writeback is eliminated because 260311051Sandreas.hansson@arm.com // we snoop another cache's ReadEx. 260411051Sandreas.hansson@arm.com } else { 260511051Sandreas.hansson@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->senderState); 260611051Sandreas.hansson@arm.com // in most cases getTimingPacket allocates a new packet, and 260711051Sandreas.hansson@arm.com // we must delete it unless it is successfully sent 260811051Sandreas.hansson@arm.com bool delete_pkt = !mshr->isForwardNoResponse(); 260911051Sandreas.hansson@arm.com 261011051Sandreas.hansson@arm.com // let our snoop responses go first if there are responses to 261111051Sandreas.hansson@arm.com // the same addresses we are about to writeback, note that 261211051Sandreas.hansson@arm.com // this creates a dependency between requests and snoop 261311051Sandreas.hansson@arm.com // responses, but that should not be a problem since there is 261411051Sandreas.hansson@arm.com // a chain already and the key is that the snoop responses can 261511051Sandreas.hansson@arm.com // sink unconditionally 261611051Sandreas.hansson@arm.com if (snoopRespQueue.hasAddr(pkt->getAddr())) { 261711051Sandreas.hansson@arm.com DPRINTF(CachePort, "Waiting for snoop response to be sent\n"); 261811051Sandreas.hansson@arm.com Tick when = snoopRespQueue.deferredPacketReadyTime(); 261911051Sandreas.hansson@arm.com schedSendEvent(when); 262011051Sandreas.hansson@arm.com 262111051Sandreas.hansson@arm.com if (delete_pkt) 262211051Sandreas.hansson@arm.com delete pkt; 262311051Sandreas.hansson@arm.com 262411051Sandreas.hansson@arm.com return; 262511051Sandreas.hansson@arm.com } 262611051Sandreas.hansson@arm.com 262711051Sandreas.hansson@arm.com 262811051Sandreas.hansson@arm.com waitingOnRetry = !masterPort.sendTimingReq(pkt); 262911051Sandreas.hansson@arm.com 263011051Sandreas.hansson@arm.com if (waitingOnRetry) { 263111051Sandreas.hansson@arm.com DPRINTF(CachePort, "now waiting on a retry\n"); 263211051Sandreas.hansson@arm.com if (delete_pkt) { 263311051Sandreas.hansson@arm.com // we are awaiting a retry, but we 263411051Sandreas.hansson@arm.com // delete the packet and will be creating a new packet 263511051Sandreas.hansson@arm.com // when we get the opportunity 263611051Sandreas.hansson@arm.com delete pkt; 263711051Sandreas.hansson@arm.com } 263811051Sandreas.hansson@arm.com // note that we have now masked any requestBus and 263911051Sandreas.hansson@arm.com // schedSendEvent (we will wait for a retry before 264011051Sandreas.hansson@arm.com // doing anything), and this is so even if we do not 264111051Sandreas.hansson@arm.com // care about this packet and might override it before 264211051Sandreas.hansson@arm.com // it gets retried 264311051Sandreas.hansson@arm.com } else { 264411051Sandreas.hansson@arm.com // As part of the call to sendTimingReq the packet is 264511284Sandreas.hansson@arm.com // forwarded to all neighbouring caches (and any caches 264611284Sandreas.hansson@arm.com // above them) as a snoop. Thus at this point we know if 264711284Sandreas.hansson@arm.com // any of the neighbouring caches are responding, and if 264811284Sandreas.hansson@arm.com // so, we know it is dirty, and we can determine if it is 264911284Sandreas.hansson@arm.com // being passed as Modified, making our MSHR the ordering 265011284Sandreas.hansson@arm.com // point 265111284Sandreas.hansson@arm.com bool pending_modified_resp = !pkt->hasSharers() && 265211284Sandreas.hansson@arm.com pkt->cacheResponding(); 265311051Sandreas.hansson@arm.com 265411284Sandreas.hansson@arm.com cache.markInService(mshr, pending_modified_resp); 265511051Sandreas.hansson@arm.com } 265611051Sandreas.hansson@arm.com } 265711051Sandreas.hansson@arm.com 265811051Sandreas.hansson@arm.com // if we succeeded and are not waiting for a retry, schedule the 265911051Sandreas.hansson@arm.com // next send considering when the next MSHR is ready, note that 266011051Sandreas.hansson@arm.com // snoop responses have their own packet queue and thus schedule 266111051Sandreas.hansson@arm.com // their own events 266211051Sandreas.hansson@arm.com if (!waitingOnRetry) { 266311051Sandreas.hansson@arm.com schedSendEvent(cache.nextMSHRReadyTime()); 266411051Sandreas.hansson@arm.com } 266511051Sandreas.hansson@arm.com} 266611051Sandreas.hansson@arm.com 266711051Sandreas.hansson@arm.comCache:: 266811051Sandreas.hansson@arm.comMemSidePort::MemSidePort(const std::string &_name, Cache *_cache, 266911051Sandreas.hansson@arm.com const std::string &_label) 267011051Sandreas.hansson@arm.com : BaseCache::CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 267111051Sandreas.hansson@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 267211051Sandreas.hansson@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 267311051Sandreas.hansson@arm.com{ 267411051Sandreas.hansson@arm.com} 2675