base.cc revision 11486
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 4811486Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 4911486Snikos.nikoleris@arm.com 508232Snate@binkert.org#include "debug/Cache.hh" 519152Satgutier@umich.edu#include "debug/Drain.hh" 5211486Snikos.nikoleris@arm.com#include "mem/cache/cache.hh" 5311486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 559795Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 5610263Satgutier@umich.edu#include "mem/cache/tags/random_repl.hh" 578786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 582810SN/A 592810SN/Ausing namespace std; 602810SN/A 618856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 628856Sandreas.hansson@arm.com BaseCache *_cache, 638856Sandreas.hansson@arm.com const std::string &_label) 648922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 658914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 668856Sandreas.hansson@arm.com{ 678856Sandreas.hansson@arm.com} 684475SN/A 6911053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 705034SN/A : MemObject(p), 7110360Sandreas.hansson@arm.com cpuSidePort(nullptr), memSidePort(nullptr), 7211377Sandreas.hansson@arm.com mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 7311377Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 7411053Sandreas.hansson@arm.com blkSize(blk_size), 7510693SMarco.Balboni@ARM.com lookupLatency(p->hit_latency), 7610693SMarco.Balboni@ARM.com forwardLatency(p->hit_latency), 7710693SMarco.Balboni@ARM.com fillLatency(p->response_latency), 789263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 795034SN/A numTarget(p->tgts_per_mshr), 8011331Sandreas.hansson@arm.com forwardSnoops(true), 8110884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 824626SN/A blocked(0), 8310360Sandreas.hansson@arm.com order(0), 8411484Snikos.nikoleris@arm.com noTargetMSHR(nullptr), 855034SN/A missCount(p->max_miss_count), 868883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 878833Sdam.sunwoo@arm.com system(p->system) 884458SN/A{ 8911377Sandreas.hansson@arm.com // the MSHR queue has no reserve entries as we check the MSHR 9011377Sandreas.hansson@arm.com // queue on every single allocation, whereas the write queue has 9111377Sandreas.hansson@arm.com // as many reserve entries as we have MSHRs, since every MSHR may 9211377Sandreas.hansson@arm.com // eventually require a writeback, and we do not check the write 9311377Sandreas.hansson@arm.com // buffer before committing to an MSHR 9411377Sandreas.hansson@arm.com 9511331Sandreas.hansson@arm.com // forward snoops is overridden in init() once we can query 9611331Sandreas.hansson@arm.com // whether the connected master is actually snooping or not 972810SN/A} 982810SN/A 993013SN/Avoid 1008856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 1012810SN/A{ 1023013SN/A assert(!blocked); 10310714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1042810SN/A blocked = true; 1059614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 1069614Srene.dejong@arm.com // happened, cancel it 1079614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 10810345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 10910714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 11010345SCurtis.Dunham@arm.com mustSendRetry = true; 1119614Srene.dejong@arm.com } 1122810SN/A} 1132810SN/A 1142810SN/Avoid 1158856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1162810SN/A{ 1173013SN/A assert(blocked); 11810714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1193013SN/A blocked = false; 1208856Sandreas.hansson@arm.com if (mustSendRetry) { 12110714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1228922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1232897SN/A } 1242810SN/A} 1252810SN/A 12610344Sandreas.hansson@arm.comvoid 12710344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 12810344Sandreas.hansson@arm.com{ 12910714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 13010344Sandreas.hansson@arm.com 13110344Sandreas.hansson@arm.com // reset the flag and call retry 13210344Sandreas.hansson@arm.com mustSendRetry = false; 13310713Sandreas.hansson@arm.com sendRetryReq(); 13410344Sandreas.hansson@arm.com} 1352844SN/A 1362810SN/Avoid 1372858SN/ABaseCache::init() 1382858SN/A{ 1398856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1408922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1418711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 14211331Sandreas.hansson@arm.com forwardSnoops = cpuSidePort->isSnooping(); 1432858SN/A} 1442858SN/A 1459294Sandreas.hansson@arm.comBaseMasterPort & 1469294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1478922Swilliam.wang@arm.com{ 1488922Swilliam.wang@arm.com if (if_name == "mem_side") { 1498922Swilliam.wang@arm.com return *memSidePort; 1508922Swilliam.wang@arm.com } else { 1518922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1528922Swilliam.wang@arm.com } 1538922Swilliam.wang@arm.com} 1548922Swilliam.wang@arm.com 1559294Sandreas.hansson@arm.comBaseSlavePort & 1569294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1578922Swilliam.wang@arm.com{ 1588922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1598922Swilliam.wang@arm.com return *cpuSidePort; 1608922Swilliam.wang@arm.com } else { 1618922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1628922Swilliam.wang@arm.com } 1638922Swilliam.wang@arm.com} 1644628SN/A 16510821Sandreas.hansson@arm.combool 16610821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 16710821Sandreas.hansson@arm.com{ 16810821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 16910821Sandreas.hansson@arm.com if (r.contains(addr)) { 17010821Sandreas.hansson@arm.com return true; 17110821Sandreas.hansson@arm.com } 17210821Sandreas.hansson@arm.com } 17310821Sandreas.hansson@arm.com return false; 17410821Sandreas.hansson@arm.com} 17510821Sandreas.hansson@arm.com 1762858SN/Avoid 1772810SN/ABaseCache::regStats() 1782810SN/A{ 1792810SN/A using namespace Stats; 1802810SN/A 1812810SN/A // Hit statistics 1824022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1834022SN/A MemCmd cmd(access_idx); 1844022SN/A const string &cstr = cmd.toString(); 1852810SN/A 1862810SN/A hits[access_idx] 1878833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1882810SN/A .name(name() + "." + cstr + "_hits") 1892810SN/A .desc("number of " + cstr + " hits") 1902810SN/A .flags(total | nozero | nonan) 1912810SN/A ; 1928833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1938833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1948833Sdam.sunwoo@arm.com } 1952810SN/A } 1962810SN/A 1974871SN/A// These macros make it easier to sum the right subset of commands and 1984871SN/A// to change the subset of commands that are considered "demand" vs 1994871SN/A// "non-demand" 2004871SN/A#define SUM_DEMAND(s) \ 20111455Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 20210885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 2034871SN/A 2044871SN/A// should writebacks be included here? prior code was inconsistent... 2054871SN/A#define SUM_NON_DEMAND(s) \ 2064871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 2074871SN/A 2082810SN/A demandHits 2092810SN/A .name(name() + ".demand_hits") 2102810SN/A .desc("number of demand (read+write) hits") 2118833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2122810SN/A ; 2134871SN/A demandHits = SUM_DEMAND(hits); 2148833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2158833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 2168833Sdam.sunwoo@arm.com } 2172810SN/A 2182810SN/A overallHits 2192810SN/A .name(name() + ".overall_hits") 2202810SN/A .desc("number of overall hits") 2218833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2222810SN/A ; 2234871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 2248833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2258833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 2268833Sdam.sunwoo@arm.com } 2272810SN/A 2282810SN/A // Miss statistics 2294022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2304022SN/A MemCmd cmd(access_idx); 2314022SN/A const string &cstr = cmd.toString(); 2322810SN/A 2332810SN/A misses[access_idx] 2348833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2352810SN/A .name(name() + "." + cstr + "_misses") 2362810SN/A .desc("number of " + cstr + " misses") 2372810SN/A .flags(total | nozero | nonan) 2382810SN/A ; 2398833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2408833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2418833Sdam.sunwoo@arm.com } 2422810SN/A } 2432810SN/A 2442810SN/A demandMisses 2452810SN/A .name(name() + ".demand_misses") 2462810SN/A .desc("number of demand (read+write) misses") 2478833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2482810SN/A ; 2494871SN/A demandMisses = SUM_DEMAND(misses); 2508833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2518833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2528833Sdam.sunwoo@arm.com } 2532810SN/A 2542810SN/A overallMisses 2552810SN/A .name(name() + ".overall_misses") 2562810SN/A .desc("number of overall misses") 2578833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2582810SN/A ; 2594871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2618833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2628833Sdam.sunwoo@arm.com } 2632810SN/A 2642810SN/A // Miss latency statistics 2654022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2664022SN/A MemCmd cmd(access_idx); 2674022SN/A const string &cstr = cmd.toString(); 2682810SN/A 2692810SN/A missLatency[access_idx] 2708833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2712810SN/A .name(name() + "." + cstr + "_miss_latency") 2722810SN/A .desc("number of " + cstr + " miss cycles") 2732810SN/A .flags(total | nozero | nonan) 2742810SN/A ; 2758833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2768833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2778833Sdam.sunwoo@arm.com } 2782810SN/A } 2792810SN/A 2802810SN/A demandMissLatency 2812810SN/A .name(name() + ".demand_miss_latency") 2822810SN/A .desc("number of demand (read+write) miss cycles") 2838833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2842810SN/A ; 2854871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2868833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2878833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2888833Sdam.sunwoo@arm.com } 2892810SN/A 2902810SN/A overallMissLatency 2912810SN/A .name(name() + ".overall_miss_latency") 2922810SN/A .desc("number of overall miss cycles") 2938833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2942810SN/A ; 2954871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2968833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2978833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2988833Sdam.sunwoo@arm.com } 2992810SN/A 3002810SN/A // access formulas 3014022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3024022SN/A MemCmd cmd(access_idx); 3034022SN/A const string &cstr = cmd.toString(); 3042810SN/A 3052810SN/A accesses[access_idx] 3062810SN/A .name(name() + "." + cstr + "_accesses") 3072810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 3082810SN/A .flags(total | nozero | nonan) 3092810SN/A ; 3108833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 3112810SN/A 3128833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3138833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 3148833Sdam.sunwoo@arm.com } 3152810SN/A } 3162810SN/A 3172810SN/A demandAccesses 3182810SN/A .name(name() + ".demand_accesses") 3192810SN/A .desc("number of demand (read+write) accesses") 3208833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3212810SN/A ; 3222810SN/A demandAccesses = demandHits + demandMisses; 3238833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3248833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3258833Sdam.sunwoo@arm.com } 3262810SN/A 3272810SN/A overallAccesses 3282810SN/A .name(name() + ".overall_accesses") 3292810SN/A .desc("number of overall (read+write) accesses") 3308833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3312810SN/A ; 3322810SN/A overallAccesses = overallHits + overallMisses; 3338833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3348833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3358833Sdam.sunwoo@arm.com } 3362810SN/A 3372810SN/A // miss rate formulas 3384022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3394022SN/A MemCmd cmd(access_idx); 3404022SN/A const string &cstr = cmd.toString(); 3412810SN/A 3422810SN/A missRate[access_idx] 3432810SN/A .name(name() + "." + cstr + "_miss_rate") 3442810SN/A .desc("miss rate for " + cstr + " accesses") 3452810SN/A .flags(total | nozero | nonan) 3462810SN/A ; 3478833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3482810SN/A 3498833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3508833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3518833Sdam.sunwoo@arm.com } 3522810SN/A } 3532810SN/A 3542810SN/A demandMissRate 3552810SN/A .name(name() + ".demand_miss_rate") 3562810SN/A .desc("miss rate for demand accesses") 3578833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3582810SN/A ; 3592810SN/A demandMissRate = demandMisses / demandAccesses; 3608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3618833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3628833Sdam.sunwoo@arm.com } 3632810SN/A 3642810SN/A overallMissRate 3652810SN/A .name(name() + ".overall_miss_rate") 3662810SN/A .desc("miss rate for overall accesses") 3678833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3682810SN/A ; 3692810SN/A overallMissRate = overallMisses / overallAccesses; 3708833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3718833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3728833Sdam.sunwoo@arm.com } 3732810SN/A 3742810SN/A // miss latency formulas 3754022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3764022SN/A MemCmd cmd(access_idx); 3774022SN/A const string &cstr = cmd.toString(); 3782810SN/A 3792810SN/A avgMissLatency[access_idx] 3802810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3812810SN/A .desc("average " + cstr + " miss latency") 3822810SN/A .flags(total | nozero | nonan) 3832810SN/A ; 3842810SN/A avgMissLatency[access_idx] = 3852810SN/A missLatency[access_idx] / misses[access_idx]; 3868833Sdam.sunwoo@arm.com 3878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3888833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3898833Sdam.sunwoo@arm.com } 3902810SN/A } 3912810SN/A 3922810SN/A demandAvgMissLatency 3932810SN/A .name(name() + ".demand_avg_miss_latency") 3942810SN/A .desc("average overall miss latency") 3958833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3962810SN/A ; 3972810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3998833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 4008833Sdam.sunwoo@arm.com } 4012810SN/A 4022810SN/A overallAvgMissLatency 4032810SN/A .name(name() + ".overall_avg_miss_latency") 4042810SN/A .desc("average overall miss latency") 4058833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4062810SN/A ; 4072810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 4088833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4098833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 4108833Sdam.sunwoo@arm.com } 4112810SN/A 4122810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 4132810SN/A blocked_cycles 4142810SN/A .name(name() + ".blocked_cycles") 4152810SN/A .desc("number of cycles access was blocked") 4162810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4172810SN/A .subname(Blocked_NoTargets, "no_targets") 4182810SN/A ; 4192810SN/A 4202810SN/A 4212810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 4222810SN/A blocked_causes 4232810SN/A .name(name() + ".blocked") 4242810SN/A .desc("number of cycles access was blocked") 4252810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4262810SN/A .subname(Blocked_NoTargets, "no_targets") 4272810SN/A ; 4282810SN/A 4292810SN/A avg_blocked 4302810SN/A .name(name() + ".avg_blocked_cycles") 4312810SN/A .desc("average number of cycles each access was blocked") 4322810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4332810SN/A .subname(Blocked_NoTargets, "no_targets") 4342810SN/A ; 4352810SN/A 4362810SN/A avg_blocked = blocked_cycles / blocked_causes; 4372810SN/A 43811436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches 43911436SRekai.GonzalezAlberquilla@arm.com .name(name() + ".unused_prefetches") 44011436SRekai.GonzalezAlberquilla@arm.com .desc("number of HardPF blocks evicted w/o reference") 44111436SRekai.GonzalezAlberquilla@arm.com .flags(nozero) 44211436SRekai.GonzalezAlberquilla@arm.com ; 44311436SRekai.GonzalezAlberquilla@arm.com 4444626SN/A writebacks 4458833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4464626SN/A .name(name() + ".writebacks") 4474626SN/A .desc("number of writebacks") 4488833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4494626SN/A ; 4508833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4518833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4528833Sdam.sunwoo@arm.com } 4534626SN/A 4544626SN/A // MSHR statistics 4554626SN/A // MSHR hit statistics 4564626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4574626SN/A MemCmd cmd(access_idx); 4584626SN/A const string &cstr = cmd.toString(); 4594626SN/A 4604626SN/A mshr_hits[access_idx] 4618833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4624626SN/A .name(name() + "." + cstr + "_mshr_hits") 4634626SN/A .desc("number of " + cstr + " MSHR hits") 4644626SN/A .flags(total | nozero | nonan) 4654626SN/A ; 4668833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4678833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4688833Sdam.sunwoo@arm.com } 4694626SN/A } 4704626SN/A 4714626SN/A demandMshrHits 4724626SN/A .name(name() + ".demand_mshr_hits") 4734626SN/A .desc("number of demand (read+write) MSHR hits") 4748833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4754626SN/A ; 4764871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4778833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4788833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4798833Sdam.sunwoo@arm.com } 4804626SN/A 4814626SN/A overallMshrHits 4824626SN/A .name(name() + ".overall_mshr_hits") 4834626SN/A .desc("number of overall MSHR hits") 4848833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4854626SN/A ; 4864871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4888833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4898833Sdam.sunwoo@arm.com } 4904626SN/A 4914626SN/A // MSHR miss statistics 4924626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4934626SN/A MemCmd cmd(access_idx); 4944626SN/A const string &cstr = cmd.toString(); 4954626SN/A 4964626SN/A mshr_misses[access_idx] 4978833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4984626SN/A .name(name() + "." + cstr + "_mshr_misses") 4994626SN/A .desc("number of " + cstr + " MSHR misses") 5004626SN/A .flags(total | nozero | nonan) 5014626SN/A ; 5028833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5038833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 5048833Sdam.sunwoo@arm.com } 5054626SN/A } 5064626SN/A 5074626SN/A demandMshrMisses 5084626SN/A .name(name() + ".demand_mshr_misses") 5094626SN/A .desc("number of demand (read+write) MSHR misses") 5108833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5114626SN/A ; 5124871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 5138833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5148833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 5158833Sdam.sunwoo@arm.com } 5164626SN/A 5174626SN/A overallMshrMisses 5184626SN/A .name(name() + ".overall_mshr_misses") 5194626SN/A .desc("number of overall MSHR misses") 5208833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5214626SN/A ; 5224871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5238833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5248833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 5258833Sdam.sunwoo@arm.com } 5264626SN/A 5274626SN/A // MSHR miss latency statistics 5284626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5294626SN/A MemCmd cmd(access_idx); 5304626SN/A const string &cstr = cmd.toString(); 5314626SN/A 5324626SN/A mshr_miss_latency[access_idx] 5338833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5344626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5354626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5364626SN/A .flags(total | nozero | nonan) 5374626SN/A ; 5388833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5398833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5408833Sdam.sunwoo@arm.com } 5414626SN/A } 5424626SN/A 5434626SN/A demandMshrMissLatency 5444626SN/A .name(name() + ".demand_mshr_miss_latency") 5454626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5468833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5474626SN/A ; 5484871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5498833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5508833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5518833Sdam.sunwoo@arm.com } 5524626SN/A 5534626SN/A overallMshrMissLatency 5544626SN/A .name(name() + ".overall_mshr_miss_latency") 5554626SN/A .desc("number of overall MSHR miss cycles") 5568833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5574626SN/A ; 5584871SN/A overallMshrMissLatency = 5594871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5618833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5628833Sdam.sunwoo@arm.com } 5634626SN/A 5644626SN/A // MSHR uncacheable statistics 5654626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5664626SN/A MemCmd cmd(access_idx); 5674626SN/A const string &cstr = cmd.toString(); 5684626SN/A 5694626SN/A mshr_uncacheable[access_idx] 5708833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5714626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5724626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5734626SN/A .flags(total | nozero | nonan) 5744626SN/A ; 5758833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5768833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5778833Sdam.sunwoo@arm.com } 5784626SN/A } 5794626SN/A 5804626SN/A overallMshrUncacheable 5814626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5824626SN/A .desc("number of overall MSHR uncacheable misses") 5838833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5844626SN/A ; 5854871SN/A overallMshrUncacheable = 5864871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5888833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5898833Sdam.sunwoo@arm.com } 5904626SN/A 5914626SN/A // MSHR miss latency statistics 5924626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5934626SN/A MemCmd cmd(access_idx); 5944626SN/A const string &cstr = cmd.toString(); 5954626SN/A 5964626SN/A mshr_uncacheable_lat[access_idx] 5978833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5984626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 5994626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 6004626SN/A .flags(total | nozero | nonan) 6014626SN/A ; 6028833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 60311483Snikos.nikoleris@arm.com mshr_uncacheable_lat[access_idx].subname( 60411483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 6058833Sdam.sunwoo@arm.com } 6064626SN/A } 6074626SN/A 6084626SN/A overallMshrUncacheableLatency 6094626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 6104626SN/A .desc("number of overall MSHR uncacheable cycles") 6118833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6124626SN/A ; 6134871SN/A overallMshrUncacheableLatency = 6144871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 6154871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 6168833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6178833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 6188833Sdam.sunwoo@arm.com } 6194626SN/A 6204626SN/A#if 0 6214626SN/A // MSHR access formulas 6224626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6234626SN/A MemCmd cmd(access_idx); 6244626SN/A const string &cstr = cmd.toString(); 6254626SN/A 6264626SN/A mshrAccesses[access_idx] 6274626SN/A .name(name() + "." + cstr + "_mshr_accesses") 6284626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6294626SN/A .flags(total | nozero | nonan) 6304626SN/A ; 6314626SN/A mshrAccesses[access_idx] = 6324626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6334626SN/A + mshr_uncacheable[access_idx]; 6344626SN/A } 6354626SN/A 6364626SN/A demandMshrAccesses 6374626SN/A .name(name() + ".demand_mshr_accesses") 6384626SN/A .desc("number of demand (read+write) mshr accesses") 6394626SN/A .flags(total | nozero | nonan) 6404626SN/A ; 6414626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6424626SN/A 6434626SN/A overallMshrAccesses 6444626SN/A .name(name() + ".overall_mshr_accesses") 6454626SN/A .desc("number of overall (read+write) mshr accesses") 6464626SN/A .flags(total | nozero | nonan) 6474626SN/A ; 6484626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6494626SN/A + overallMshrUncacheable; 6504626SN/A#endif 6514626SN/A 6524626SN/A // MSHR miss rate formulas 6534626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6544626SN/A MemCmd cmd(access_idx); 6554626SN/A const string &cstr = cmd.toString(); 6564626SN/A 6574626SN/A mshrMissRate[access_idx] 6584626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6594626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6604626SN/A .flags(total | nozero | nonan) 6614626SN/A ; 6624626SN/A mshrMissRate[access_idx] = 6634626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6648833Sdam.sunwoo@arm.com 6658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6668833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6678833Sdam.sunwoo@arm.com } 6684626SN/A } 6694626SN/A 6704626SN/A demandMshrMissRate 6714626SN/A .name(name() + ".demand_mshr_miss_rate") 6724626SN/A .desc("mshr miss rate for demand accesses") 6738833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6744626SN/A ; 6754626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6768833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6778833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6788833Sdam.sunwoo@arm.com } 6794626SN/A 6804626SN/A overallMshrMissRate 6814626SN/A .name(name() + ".overall_mshr_miss_rate") 6824626SN/A .desc("mshr miss rate for overall accesses") 6838833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6844626SN/A ; 6854626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6868833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6878833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6888833Sdam.sunwoo@arm.com } 6894626SN/A 6904626SN/A // mshrMiss latency formulas 6914626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6924626SN/A MemCmd cmd(access_idx); 6934626SN/A const string &cstr = cmd.toString(); 6944626SN/A 6954626SN/A avgMshrMissLatency[access_idx] 6964626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6974626SN/A .desc("average " + cstr + " mshr miss latency") 6984626SN/A .flags(total | nozero | nonan) 6994626SN/A ; 7004626SN/A avgMshrMissLatency[access_idx] = 7014626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 7028833Sdam.sunwoo@arm.com 7038833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 70411483Snikos.nikoleris@arm.com avgMshrMissLatency[access_idx].subname( 70511483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 7068833Sdam.sunwoo@arm.com } 7074626SN/A } 7084626SN/A 7094626SN/A demandAvgMshrMissLatency 7104626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 7114626SN/A .desc("average overall mshr miss latency") 7128833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7134626SN/A ; 7144626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 7158833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7168833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7178833Sdam.sunwoo@arm.com } 7184626SN/A 7194626SN/A overallAvgMshrMissLatency 7204626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 7214626SN/A .desc("average overall mshr miss latency") 7228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7234626SN/A ; 7244626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 7258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7268833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7278833Sdam.sunwoo@arm.com } 7284626SN/A 7294626SN/A // mshrUncacheable latency formulas 7304626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7314626SN/A MemCmd cmd(access_idx); 7324626SN/A const string &cstr = cmd.toString(); 7334626SN/A 7344626SN/A avgMshrUncacheableLatency[access_idx] 7354626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7364626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7374626SN/A .flags(total | nozero | nonan) 7384626SN/A ; 7394626SN/A avgMshrUncacheableLatency[access_idx] = 7404626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7418833Sdam.sunwoo@arm.com 7428833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 74311483Snikos.nikoleris@arm.com avgMshrUncacheableLatency[access_idx].subname( 74411483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 7458833Sdam.sunwoo@arm.com } 7464626SN/A } 7474626SN/A 7484626SN/A overallAvgMshrUncacheableLatency 7494626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7504626SN/A .desc("average overall mshr uncacheable latency") 7518833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7524626SN/A ; 75311483Snikos.nikoleris@arm.com overallAvgMshrUncacheableLatency = 75411483Snikos.nikoleris@arm.com overallMshrUncacheableLatency / overallMshrUncacheable; 7558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7568833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7578833Sdam.sunwoo@arm.com } 7584626SN/A 7592810SN/A} 760