base.cc revision 11486
110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2012-2013 ARM Limited 314127Sgiacomo.travaglini@arm.com * All rights reserved. 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Copyright (c) 2003-2005 The Regents of The University of Michigan 1510037SARM gem5 Developers * All rights reserved. 1610037SARM gem5 Developers * 1710037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1810037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1910037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 2010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 2110037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 2210037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2310037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2410037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2510037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2610037SARM gem5 Developers * this software without specific prior written permission. 2710037SARM gem5 Developers * 2810037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910037SARM gem5 Developers * 4010037SARM gem5 Developers * Authors: Erik Hallnor 4110037SARM gem5 Developers */ 4210037SARM gem5 Developers 4310037SARM gem5 Developers/** 4410037SARM gem5 Developers * @file 4510037SARM gem5 Developers * Definition of BaseCache functions. 4610037SARM gem5 Developers */ 4710037SARM gem5 Developers 4810037SARM gem5 Developers#include "mem/cache/base.hh" 4910037SARM gem5 Developers 5010037SARM gem5 Developers#include "debug/Cache.hh" 5110037SARM gem5 Developers#include "debug/Drain.hh" 5210037SARM gem5 Developers#include "mem/cache/cache.hh" 5311862Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 5410037SARM gem5 Developers#include "mem/cache/tags/fa_lru.hh" 5510037SARM gem5 Developers#include "mem/cache/tags/lru.hh" 5610037SARM gem5 Developers#include "mem/cache/tags/random_repl.hh" 5710037SARM gem5 Developers#include "sim/full_system.hh" 5810037SARM gem5 Developers 5910037SARM gem5 Developersusing namespace std; 6010037SARM gem5 Developers 6110037SARM gem5 DevelopersBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 6210037SARM gem5 Developers BaseCache *_cache, 6310037SARM gem5 Developers const std::string &_label) 6410037SARM gem5 Developers : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 6510037SARM gem5 Developers blocked(false), mustSendRetry(false), sendRetryEvent(this) 6610037SARM gem5 Developers{ 6710037SARM gem5 Developers} 6810037SARM gem5 Developers 6910037SARM gem5 DevelopersBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 7010037SARM gem5 Developers : MemObject(p), 7110037SARM gem5 Developers cpuSidePort(nullptr), memSidePort(nullptr), 7210037SARM gem5 Developers mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 7310037SARM gem5 Developers writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 7410037SARM gem5 Developers blkSize(blk_size), 7510037SARM gem5 Developers lookupLatency(p->hit_latency), 7610037SARM gem5 Developers forwardLatency(p->hit_latency), 7710037SARM gem5 Developers fillLatency(p->response_latency), 7810037SARM gem5 Developers responseLatency(p->response_latency), 7910037SARM gem5 Developers numTarget(p->tgts_per_mshr), 8010037SARM gem5 Developers forwardSnoops(true), 8110037SARM gem5 Developers isReadOnly(p->is_read_only), 8210037SARM gem5 Developers blocked(0), 8310037SARM gem5 Developers order(0), 8410037SARM gem5 Developers noTargetMSHR(nullptr), 8510037SARM gem5 Developers missCount(p->max_miss_count), 8610037SARM gem5 Developers addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 8710037SARM gem5 Developers system(p->system) 8810037SARM gem5 Developers{ 8910037SARM gem5 Developers // the MSHR queue has no reserve entries as we check the MSHR 9010037SARM gem5 Developers // queue on every single allocation, whereas the write queue has 9110037SARM gem5 Developers // as many reserve entries as we have MSHRs, since every MSHR may 9210037SARM gem5 Developers // eventually require a writeback, and we do not check the write 9310037SARM gem5 Developers // buffer before committing to an MSHR 9410037SARM gem5 Developers 9510037SARM gem5 Developers // forward snoops is overridden in init() once we can query 9610037SARM gem5 Developers // whether the connected master is actually snooping or not 9710037SARM gem5 Developers} 9810037SARM gem5 Developers 9910037SARM gem5 Developersvoid 10010037SARM gem5 DevelopersBaseCache::CacheSlavePort::setBlocked() 10110037SARM gem5 Developers{ 10210037SARM gem5 Developers assert(!blocked); 10310037SARM gem5 Developers DPRINTF(CachePort, "Port is blocking new requests\n"); 10410037SARM gem5 Developers blocked = true; 10510037SARM gem5 Developers // if we already scheduled a retry in this cycle, but it has not yet 10610037SARM gem5 Developers // happened, cancel it 10710037SARM gem5 Developers if (sendRetryEvent.scheduled()) { 10810037SARM gem5 Developers owner.deschedule(sendRetryEvent); 10910037SARM gem5 Developers DPRINTF(CachePort, "Port descheduled retry\n"); 11010037SARM gem5 Developers mustSendRetry = true; 11110037SARM gem5 Developers } 11210037SARM gem5 Developers} 11310037SARM gem5 Developers 11410037SARM gem5 Developersvoid 11510037SARM gem5 DevelopersBaseCache::CacheSlavePort::clearBlocked() 11610037SARM gem5 Developers{ 11710037SARM gem5 Developers assert(blocked); 11810037SARM gem5 Developers DPRINTF(CachePort, "Port is accepting new requests\n"); 11910037SARM gem5 Developers blocked = false; 12010037SARM gem5 Developers if (mustSendRetry) { 12110037SARM gem5 Developers // @TODO: need to find a better time (next cycle?) 12210037SARM gem5 Developers owner.schedule(sendRetryEvent, curTick() + 1); 12310037SARM gem5 Developers } 12410037SARM gem5 Developers} 12510037SARM gem5 Developers 12610037SARM gem5 Developersvoid 12710037SARM gem5 DevelopersBaseCache::CacheSlavePort::processSendRetry() 12810037SARM gem5 Developers{ 12910037SARM gem5 Developers DPRINTF(CachePort, "Port is sending retry\n"); 13010037SARM gem5 Developers 13110037SARM gem5 Developers // reset the flag and call retry 13210037SARM gem5 Developers mustSendRetry = false; 13310037SARM gem5 Developers sendRetryReq(); 13410037SARM gem5 Developers} 13510037SARM gem5 Developers 13610037SARM gem5 Developersvoid 13710037SARM gem5 DevelopersBaseCache::init() 13810037SARM gem5 Developers{ 13910037SARM gem5 Developers if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 14010037SARM gem5 Developers fatal("Cache ports on %s are not connected\n", name()); 14110037SARM gem5 Developers cpuSidePort->sendRangeChange(); 14210037SARM gem5 Developers forwardSnoops = cpuSidePort->isSnooping(); 14310037SARM gem5 Developers} 14410037SARM gem5 Developers 14510037SARM gem5 DevelopersBaseMasterPort & 14610037SARM gem5 DevelopersBaseCache::getMasterPort(const std::string &if_name, PortID idx) 14710037SARM gem5 Developers{ 14810037SARM gem5 Developers if (if_name == "mem_side") { 14910037SARM gem5 Developers return *memSidePort; 15010037SARM gem5 Developers } else { 15110037SARM gem5 Developers return MemObject::getMasterPort(if_name, idx); 15210037SARM gem5 Developers } 15310037SARM gem5 Developers} 15410037SARM gem5 Developers 15510037SARM gem5 DevelopersBaseSlavePort & 15610037SARM gem5 DevelopersBaseCache::getSlavePort(const std::string &if_name, PortID idx) 15710037SARM gem5 Developers{ 15810037SARM gem5 Developers if (if_name == "cpu_side") { 15910037SARM gem5 Developers return *cpuSidePort; 16010037SARM gem5 Developers } else { 16110037SARM gem5 Developers return MemObject::getSlavePort(if_name, idx); 16210037SARM gem5 Developers } 16310037SARM gem5 Developers} 16410037SARM gem5 Developers 16510037SARM gem5 Developersbool 16610037SARM gem5 DevelopersBaseCache::inRange(Addr addr) const 16710037SARM gem5 Developers{ 16810037SARM gem5 Developers for (const auto& r : addrRanges) { 16910037SARM gem5 Developers if (r.contains(addr)) { 17010037SARM gem5 Developers return true; 17110037SARM gem5 Developers } 17210037SARM gem5 Developers } 17310037SARM gem5 Developers return false; 17410037SARM gem5 Developers} 17510037SARM gem5 Developers 17610037SARM gem5 Developersvoid 17710037SARM gem5 DevelopersBaseCache::regStats() 17810037SARM gem5 Developers{ 17910037SARM gem5 Developers using namespace Stats; 18010037SARM gem5 Developers 18110037SARM gem5 Developers // Hit statistics 18210037SARM gem5 Developers for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 18310037SARM gem5 Developers MemCmd cmd(access_idx); 18410037SARM gem5 Developers const string &cstr = cmd.toString(); 18510037SARM gem5 Developers 18610037SARM gem5 Developers hits[access_idx] 18710037SARM gem5 Developers .init(system->maxMasters()) 18810037SARM gem5 Developers .name(name() + "." + cstr + "_hits") 18910037SARM gem5 Developers .desc("number of " + cstr + " hits") 19010037SARM gem5 Developers .flags(total | nozero | nonan) 19110037SARM gem5 Developers ; 19210037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 19310037SARM gem5 Developers hits[access_idx].subname(i, system->getMasterName(i)); 19410037SARM gem5 Developers } 19510037SARM gem5 Developers } 19610037SARM gem5 Developers 19710037SARM gem5 Developers// These macros make it easier to sum the right subset of commands and 19810037SARM gem5 Developers// to change the subset of commands that are considered "demand" vs 19910037SARM gem5 Developers// "non-demand" 20010037SARM gem5 Developers#define SUM_DEMAND(s) \ 20110037SARM gem5 Developers (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 20210037SARM gem5 Developers s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 20310037SARM gem5 Developers 20410037SARM gem5 Developers// should writebacks be included here? prior code was inconsistent... 20510037SARM gem5 Developers#define SUM_NON_DEMAND(s) \ 20610037SARM gem5 Developers (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 20710037SARM gem5 Developers 20810037SARM gem5 Developers demandHits 20910037SARM gem5 Developers .name(name() + ".demand_hits") 21010037SARM gem5 Developers .desc("number of demand (read+write) hits") 21110037SARM gem5 Developers .flags(total | nozero | nonan) 21210037SARM gem5 Developers ; 21310037SARM gem5 Developers demandHits = SUM_DEMAND(hits); 21410037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 21510037SARM gem5 Developers demandHits.subname(i, system->getMasterName(i)); 21610037SARM gem5 Developers } 21710037SARM gem5 Developers 21810037SARM gem5 Developers overallHits 21910037SARM gem5 Developers .name(name() + ".overall_hits") 22010037SARM gem5 Developers .desc("number of overall hits") 22110037SARM gem5 Developers .flags(total | nozero | nonan) 22210037SARM gem5 Developers ; 22310037SARM gem5 Developers overallHits = demandHits + SUM_NON_DEMAND(hits); 22410037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 22510037SARM gem5 Developers overallHits.subname(i, system->getMasterName(i)); 22610037SARM gem5 Developers } 22710037SARM gem5 Developers 22810037SARM gem5 Developers // Miss statistics 22912258Sgiacomo.travaglini@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 23012258Sgiacomo.travaglini@arm.com MemCmd cmd(access_idx); 23112258Sgiacomo.travaglini@arm.com const string &cstr = cmd.toString(); 23212258Sgiacomo.travaglini@arm.com 23312258Sgiacomo.travaglini@arm.com misses[access_idx] 23412258Sgiacomo.travaglini@arm.com .init(system->maxMasters()) 23512258Sgiacomo.travaglini@arm.com .name(name() + "." + cstr + "_misses") 23612258Sgiacomo.travaglini@arm.com .desc("number of " + cstr + " misses") 23712258Sgiacomo.travaglini@arm.com .flags(total | nozero | nonan) 23812258Sgiacomo.travaglini@arm.com ; 23912258Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 24012258Sgiacomo.travaglini@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 24112258Sgiacomo.travaglini@arm.com } 24212258Sgiacomo.travaglini@arm.com } 24312258Sgiacomo.travaglini@arm.com 24412258Sgiacomo.travaglini@arm.com demandMisses 24512258Sgiacomo.travaglini@arm.com .name(name() + ".demand_misses") 24612258Sgiacomo.travaglini@arm.com .desc("number of demand (read+write) misses") 24712258Sgiacomo.travaglini@arm.com .flags(total | nozero | nonan) 24812258Sgiacomo.travaglini@arm.com ; 24912258Sgiacomo.travaglini@arm.com demandMisses = SUM_DEMAND(misses); 25012258Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 25112258Sgiacomo.travaglini@arm.com demandMisses.subname(i, system->getMasterName(i)); 25212258Sgiacomo.travaglini@arm.com } 25312258Sgiacomo.travaglini@arm.com 25412258Sgiacomo.travaglini@arm.com overallMisses 25512258Sgiacomo.travaglini@arm.com .name(name() + ".overall_misses") 25612258Sgiacomo.travaglini@arm.com .desc("number of overall misses") 25712258Sgiacomo.travaglini@arm.com .flags(total | nozero | nonan) 25812258Sgiacomo.travaglini@arm.com ; 25912258Sgiacomo.travaglini@arm.com overallMisses = demandMisses + SUM_NON_DEMAND(misses); 26012258Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 26112258Sgiacomo.travaglini@arm.com overallMisses.subname(i, system->getMasterName(i)); 26212258Sgiacomo.travaglini@arm.com } 26312258Sgiacomo.travaglini@arm.com 26412258Sgiacomo.travaglini@arm.com // Miss latency statistics 26510037SARM gem5 Developers for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 26610037SARM gem5 Developers MemCmd cmd(access_idx); 26710037SARM gem5 Developers const string &cstr = cmd.toString(); 26810037SARM gem5 Developers 26910037SARM gem5 Developers missLatency[access_idx] 27010037SARM gem5 Developers .init(system->maxMasters()) 27110037SARM gem5 Developers .name(name() + "." + cstr + "_miss_latency") 27210037SARM gem5 Developers .desc("number of " + cstr + " miss cycles") 27310037SARM gem5 Developers .flags(total | nozero | nonan) 27410037SARM gem5 Developers ; 27510037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 27610037SARM gem5 Developers missLatency[access_idx].subname(i, system->getMasterName(i)); 27710037SARM gem5 Developers } 27810037SARM gem5 Developers } 27910037SARM gem5 Developers 28010037SARM gem5 Developers demandMissLatency 28110037SARM gem5 Developers .name(name() + ".demand_miss_latency") 28210037SARM gem5 Developers .desc("number of demand (read+write) miss cycles") 28310037SARM gem5 Developers .flags(total | nozero | nonan) 28410037SARM gem5 Developers ; 28510037SARM gem5 Developers demandMissLatency = SUM_DEMAND(missLatency); 28610037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 28712227Sgiacomo.travaglini@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 28810037SARM gem5 Developers } 28910037SARM gem5 Developers 29010037SARM gem5 Developers overallMissLatency 29110037SARM gem5 Developers .name(name() + ".overall_miss_latency") 29210037SARM gem5 Developers .desc("number of overall miss cycles") 29310037SARM gem5 Developers .flags(total | nozero | nonan) 29410037SARM gem5 Developers ; 29510037SARM gem5 Developers overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 29610037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 29710037SARM gem5 Developers overallMissLatency.subname(i, system->getMasterName(i)); 29810037SARM gem5 Developers } 29910037SARM gem5 Developers 30010037SARM gem5 Developers // access formulas 30110037SARM gem5 Developers for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 30210037SARM gem5 Developers MemCmd cmd(access_idx); 30310037SARM gem5 Developers const string &cstr = cmd.toString(); 30410037SARM gem5 Developers 30510037SARM gem5 Developers accesses[access_idx] 30610037SARM gem5 Developers .name(name() + "." + cstr + "_accesses") 30710037SARM gem5 Developers .desc("number of " + cstr + " accesses(hits+misses)") 30810037SARM gem5 Developers .flags(total | nozero | nonan) 30910037SARM gem5 Developers ; 31010037SARM gem5 Developers accesses[access_idx] = hits[access_idx] + misses[access_idx]; 31110037SARM gem5 Developers 31210037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 31310037SARM gem5 Developers accesses[access_idx].subname(i, system->getMasterName(i)); 31410037SARM gem5 Developers } 31510037SARM gem5 Developers } 31610037SARM gem5 Developers 31710037SARM gem5 Developers demandAccesses 31810037SARM gem5 Developers .name(name() + ".demand_accesses") 31910037SARM gem5 Developers .desc("number of demand (read+write) accesses") 32012508Snikos.nikoleris@arm.com .flags(total | nozero | nonan) 32110037SARM gem5 Developers ; 32210474Sandreas.hansson@arm.com demandAccesses = demandHits + demandMisses; 32310474Sandreas.hansson@arm.com for (int i = 0; i < system->maxMasters(); i++) { 32410205SAli.Saidi@ARM.com demandAccesses.subname(i, system->getMasterName(i)); 32510474Sandreas.hansson@arm.com } 32610474Sandreas.hansson@arm.com 32710037SARM gem5 Developers overallAccesses 32810037SARM gem5 Developers .name(name() + ".overall_accesses") 32913364Sgiacomo.travaglini@arm.com .desc("number of overall (read+write) accesses") 33013364Sgiacomo.travaglini@arm.com .flags(total | nozero | nonan) 33110037SARM gem5 Developers ; 33210037SARM gem5 Developers overallAccesses = overallHits + overallMisses; 33314241Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 33414241Sgiacomo.travaglini@arm.com overallAccesses.subname(i, system->getMasterName(i)); 33514241Sgiacomo.travaglini@arm.com } 33614241Sgiacomo.travaglini@arm.com 33714241Sgiacomo.travaglini@arm.com // miss rate formulas 33814241Sgiacomo.travaglini@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 33914241Sgiacomo.travaglini@arm.com MemCmd cmd(access_idx); 34014241Sgiacomo.travaglini@arm.com const string &cstr = cmd.toString(); 34114241Sgiacomo.travaglini@arm.com 34210037SARM gem5 Developers missRate[access_idx] 34312106SRekai.GonzalezAlberquilla@arm.com .name(name() + "." + cstr + "_miss_rate") 34410037SARM gem5 Developers .desc("miss rate for " + cstr + " accesses") 34510037SARM gem5 Developers .flags(total | nozero | nonan) 34610037SARM gem5 Developers ; 34713364Sgiacomo.travaglini@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 34812280Sgiacomo.travaglini@arm.com 34914241Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 35014241Sgiacomo.travaglini@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 35114241Sgiacomo.travaglini@arm.com } 35214241Sgiacomo.travaglini@arm.com } 35312280Sgiacomo.travaglini@arm.com 35412280Sgiacomo.travaglini@arm.com demandMissRate 35512280Sgiacomo.travaglini@arm.com .name(name() + ".demand_miss_rate") 35612280Sgiacomo.travaglini@arm.com .desc("miss rate for demand accesses") 35712280Sgiacomo.travaglini@arm.com .flags(total | nozero | nonan) 35812280Sgiacomo.travaglini@arm.com ; 35910037SARM gem5 Developers demandMissRate = demandMisses / demandAccesses; 36010037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 36110037SARM gem5 Developers demandMissRate.subname(i, system->getMasterName(i)); 36210037SARM gem5 Developers } 36310037SARM gem5 Developers 36410037SARM gem5 Developers overallMissRate 36510037SARM gem5 Developers .name(name() + ".overall_miss_rate") 36610037SARM gem5 Developers .desc("miss rate for overall accesses") 36710037SARM gem5 Developers .flags(total | nozero | nonan) 36814241Sgiacomo.travaglini@arm.com ; 36910037SARM gem5 Developers overallMissRate = overallMisses / overallAccesses; 37014241Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 37112280Sgiacomo.travaglini@arm.com overallMissRate.subname(i, system->getMasterName(i)); 37212280Sgiacomo.travaglini@arm.com } 37312280Sgiacomo.travaglini@arm.com 37412280Sgiacomo.travaglini@arm.com // miss latency formulas 37512280Sgiacomo.travaglini@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 37612280Sgiacomo.travaglini@arm.com MemCmd cmd(access_idx); 37712280Sgiacomo.travaglini@arm.com const string &cstr = cmd.toString(); 37810037SARM gem5 Developers 37910037SARM gem5 Developers avgMissLatency[access_idx] 38010037SARM gem5 Developers .name(name() + "." + cstr + "_avg_miss_latency") 38110037SARM gem5 Developers .desc("average " + cstr + " miss latency") 38210037SARM gem5 Developers .flags(total | nozero | nonan) 38310037SARM gem5 Developers ; 38410037SARM gem5 Developers avgMissLatency[access_idx] = 38510037SARM gem5 Developers missLatency[access_idx] / misses[access_idx]; 38612507Snikos.nikoleris@arm.com 38712507Snikos.nikoleris@arm.com for (int i = 0; i < system->maxMasters(); i++) { 38810037SARM gem5 Developers avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 38912507Snikos.nikoleris@arm.com } 39012507Snikos.nikoleris@arm.com } 39110037SARM gem5 Developers 39210037SARM gem5 Developers demandAvgMissLatency 39310037SARM gem5 Developers .name(name() + ".demand_avg_miss_latency") 39410037SARM gem5 Developers .desc("average overall miss latency") 39510037SARM gem5 Developers .flags(total | nozero | nonan) 39610037SARM gem5 Developers ; 39710037SARM gem5 Developers demandAvgMissLatency = demandMissLatency / demandMisses; 39812504Snikos.nikoleris@arm.com for (int i = 0; i < system->maxMasters(); i++) { 39912507Snikos.nikoleris@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 40012507Snikos.nikoleris@arm.com } 40112507Snikos.nikoleris@arm.com 40212507Snikos.nikoleris@arm.com overallAvgMissLatency 40312507Snikos.nikoleris@arm.com .name(name() + ".overall_avg_miss_latency") 40412507Snikos.nikoleris@arm.com .desc("average overall miss latency") 40510037SARM gem5 Developers .flags(total | nozero | nonan) 40610037SARM gem5 Developers ; 40710037SARM gem5 Developers overallAvgMissLatency = overallMissLatency / overallMisses; 40810037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 40910037SARM gem5 Developers overallAvgMissLatency.subname(i, system->getMasterName(i)); 41010037SARM gem5 Developers } 41110037SARM gem5 Developers 41212507Snikos.nikoleris@arm.com blocked_cycles.init(NUM_BLOCKED_CAUSES); 41312359Snikos.nikoleris@arm.com blocked_cycles 41412359Snikos.nikoleris@arm.com .name(name() + ".blocked_cycles") 41512359Snikos.nikoleris@arm.com .desc("number of cycles access was blocked") 41612359Snikos.nikoleris@arm.com .subname(Blocked_NoMSHRs, "no_mshrs") 41712359Snikos.nikoleris@arm.com .subname(Blocked_NoTargets, "no_targets") 41812359Snikos.nikoleris@arm.com ; 41912359Snikos.nikoleris@arm.com 42012359Snikos.nikoleris@arm.com 42112359Snikos.nikoleris@arm.com blocked_causes.init(NUM_BLOCKED_CAUSES); 42212359Snikos.nikoleris@arm.com blocked_causes 42312507Snikos.nikoleris@arm.com .name(name() + ".blocked") 42412507Snikos.nikoleris@arm.com .desc("number of cycles access was blocked") 42512507Snikos.nikoleris@arm.com .subname(Blocked_NoMSHRs, "no_mshrs") 42612507Snikos.nikoleris@arm.com .subname(Blocked_NoTargets, "no_targets") 42712507Snikos.nikoleris@arm.com ; 42812359Snikos.nikoleris@arm.com 42912359Snikos.nikoleris@arm.com avg_blocked 43012359Snikos.nikoleris@arm.com .name(name() + ".avg_blocked_cycles") 43112359Snikos.nikoleris@arm.com .desc("average number of cycles each access was blocked") 43212359Snikos.nikoleris@arm.com .subname(Blocked_NoMSHRs, "no_mshrs") 43312359Snikos.nikoleris@arm.com .subname(Blocked_NoTargets, "no_targets") 43412359Snikos.nikoleris@arm.com ; 43512507Snikos.nikoleris@arm.com 43612359Snikos.nikoleris@arm.com avg_blocked = blocked_cycles / blocked_causes; 43712359Snikos.nikoleris@arm.com 43812359Snikos.nikoleris@arm.com unusedPrefetches 43912359Snikos.nikoleris@arm.com .name(name() + ".unused_prefetches") 44012359Snikos.nikoleris@arm.com .desc("number of HardPF blocks evicted w/o reference") 44112359Snikos.nikoleris@arm.com .flags(nozero) 44212359Snikos.nikoleris@arm.com ; 44312359Snikos.nikoleris@arm.com 44412359Snikos.nikoleris@arm.com writebacks 44512359Snikos.nikoleris@arm.com .init(system->maxMasters()) 44612507Snikos.nikoleris@arm.com .name(name() + ".writebacks") 44712507Snikos.nikoleris@arm.com .desc("number of writebacks") 44812507Snikos.nikoleris@arm.com .flags(total | nozero | nonan) 44912507Snikos.nikoleris@arm.com ; 45012507Snikos.nikoleris@arm.com for (int i = 0; i < system->maxMasters(); i++) { 45112359Snikos.nikoleris@arm.com writebacks.subname(i, system->getMasterName(i)); 45212359Snikos.nikoleris@arm.com } 45312359Snikos.nikoleris@arm.com 45412359Snikos.nikoleris@arm.com // MSHR statistics 45512359Snikos.nikoleris@arm.com // MSHR hit statistics 45612359Snikos.nikoleris@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 45712359Snikos.nikoleris@arm.com MemCmd cmd(access_idx); 45812507Snikos.nikoleris@arm.com const string &cstr = cmd.toString(); 45912359Snikos.nikoleris@arm.com 46012359Snikos.nikoleris@arm.com mshr_hits[access_idx] 46112359Snikos.nikoleris@arm.com .init(system->maxMasters()) 46212359Snikos.nikoleris@arm.com .name(name() + "." + cstr + "_mshr_hits") 46312359Snikos.nikoleris@arm.com .desc("number of " + cstr + " MSHR hits") 46412359Snikos.nikoleris@arm.com .flags(total | nozero | nonan) 46512359Snikos.nikoleris@arm.com ; 46612359Snikos.nikoleris@arm.com for (int i = 0; i < system->maxMasters(); i++) { 46712359Snikos.nikoleris@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 46812359Snikos.nikoleris@arm.com } 46912507Snikos.nikoleris@arm.com } 47012507Snikos.nikoleris@arm.com 47112507Snikos.nikoleris@arm.com demandMshrHits 47212507Snikos.nikoleris@arm.com .name(name() + ".demand_mshr_hits") 47312507Snikos.nikoleris@arm.com .desc("number of demand (read+write) MSHR hits") 47412359Snikos.nikoleris@arm.com .flags(total | nozero | nonan) 47512359Snikos.nikoleris@arm.com ; 47612359Snikos.nikoleris@arm.com demandMshrHits = SUM_DEMAND(mshr_hits); 47712359Snikos.nikoleris@arm.com for (int i = 0; i < system->maxMasters(); i++) { 47812359Snikos.nikoleris@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 47912359Snikos.nikoleris@arm.com } 48012359Snikos.nikoleris@arm.com 48112507Snikos.nikoleris@arm.com overallMshrHits 48212359Snikos.nikoleris@arm.com .name(name() + ".overall_mshr_hits") 48312359Snikos.nikoleris@arm.com .desc("number of overall MSHR hits") 48412359Snikos.nikoleris@arm.com .flags(total | nozero | nonan) 48512359Snikos.nikoleris@arm.com ; 48612505Snikos.nikoleris@arm.com overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 48712505Snikos.nikoleris@arm.com for (int i = 0; i < system->maxMasters(); i++) { 48812505Snikos.nikoleris@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 48912505Snikos.nikoleris@arm.com } 49012505Snikos.nikoleris@arm.com 49112505Snikos.nikoleris@arm.com // MSHR miss statistics 49212359Snikos.nikoleris@arm.com for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 49312359Snikos.nikoleris@arm.com MemCmd cmd(access_idx); 49412359Snikos.nikoleris@arm.com const string &cstr = cmd.toString(); 49512359Snikos.nikoleris@arm.com 49612359Snikos.nikoleris@arm.com mshr_misses[access_idx] 49712359Snikos.nikoleris@arm.com .init(system->maxMasters()) 49812507Snikos.nikoleris@arm.com .name(name() + "." + cstr + "_mshr_misses") 49912507Snikos.nikoleris@arm.com .desc("number of " + cstr + " MSHR misses") 50012507Snikos.nikoleris@arm.com .flags(total | nozero | nonan) 50112507Snikos.nikoleris@arm.com ; 50212507Snikos.nikoleris@arm.com for (int i = 0; i < system->maxMasters(); i++) { 50312359Snikos.nikoleris@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 50412359Snikos.nikoleris@arm.com } 50512359Snikos.nikoleris@arm.com } 50612359Snikos.nikoleris@arm.com 50712359Snikos.nikoleris@arm.com demandMshrMisses 50812359Snikos.nikoleris@arm.com .name(name() + ".demand_mshr_misses") 50914127Sgiacomo.travaglini@arm.com .desc("number of demand (read+write) MSHR misses") 51014127Sgiacomo.travaglini@arm.com .flags(total | nozero | nonan) 51114127Sgiacomo.travaglini@arm.com ; 51214128Sgiacomo.travaglini@arm.com demandMshrMisses = SUM_DEMAND(mshr_misses); 51314128Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 51414128Sgiacomo.travaglini@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 51514128Sgiacomo.travaglini@arm.com } 51614128Sgiacomo.travaglini@arm.com 51714128Sgiacomo.travaglini@arm.com overallMshrMisses 51814128Sgiacomo.travaglini@arm.com .name(name() + ".overall_mshr_misses") 51914128Sgiacomo.travaglini@arm.com .desc("number of overall MSHR misses") 52014128Sgiacomo.travaglini@arm.com .flags(total | nozero | nonan) 52114128Sgiacomo.travaglini@arm.com ; 52214128Sgiacomo.travaglini@arm.com overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 52314128Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 52414128Sgiacomo.travaglini@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 52514128Sgiacomo.travaglini@arm.com } 52614128Sgiacomo.travaglini@arm.com 52714127Sgiacomo.travaglini@arm.com // MSHR miss latency statistics 52810037SARM gem5 Developers for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 52914127Sgiacomo.travaglini@arm.com MemCmd cmd(access_idx); 53014127Sgiacomo.travaglini@arm.com const string &cstr = cmd.toString(); 53114127Sgiacomo.travaglini@arm.com 53214127Sgiacomo.travaglini@arm.com mshr_miss_latency[access_idx] 53314127Sgiacomo.travaglini@arm.com .init(system->maxMasters()) 53414127Sgiacomo.travaglini@arm.com .name(name() + "." + cstr + "_mshr_miss_latency") 53514127Sgiacomo.travaglini@arm.com .desc("number of " + cstr + " MSHR miss cycles") 53610037SARM gem5 Developers .flags(total | nozero | nonan) 53714127Sgiacomo.travaglini@arm.com ; 53814127Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 53914127Sgiacomo.travaglini@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 54014127Sgiacomo.travaglini@arm.com } 54114127Sgiacomo.travaglini@arm.com } 54214127Sgiacomo.travaglini@arm.com 54314127Sgiacomo.travaglini@arm.com demandMshrMissLatency 54410037SARM gem5 Developers .name(name() + ".demand_mshr_miss_latency") 54510037SARM gem5 Developers .desc("number of demand (read+write) MSHR miss cycles") 54610037SARM gem5 Developers .flags(total | nozero | nonan) 54714127Sgiacomo.travaglini@arm.com ; 54810037SARM gem5 Developers demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 54914127Sgiacomo.travaglini@arm.com for (int i = 0; i < system->maxMasters(); i++) { 55010037SARM gem5 Developers demandMshrMissLatency.subname(i, system->getMasterName(i)); 55110037SARM gem5 Developers } 55210037SARM gem5 Developers 55314127Sgiacomo.travaglini@arm.com overallMshrMissLatency 55410037SARM gem5 Developers .name(name() + ".overall_mshr_miss_latency") 55510037SARM gem5 Developers .desc("number of overall MSHR miss cycles") 55610037SARM gem5 Developers .flags(total | nozero | nonan) 55710037SARM gem5 Developers ; 55810037SARM gem5 Developers overallMshrMissLatency = 55910037SARM gem5 Developers demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 56010037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 56110037SARM gem5 Developers overallMshrMissLatency.subname(i, system->getMasterName(i)); 56210037SARM gem5 Developers } 56310037SARM gem5 Developers 56410037SARM gem5 Developers // MSHR uncacheable statistics 56510037SARM gem5 Developers for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 56610037SARM gem5 Developers MemCmd cmd(access_idx); 56710037SARM gem5 Developers const string &cstr = cmd.toString(); 56810037SARM gem5 Developers 56910037SARM gem5 Developers mshr_uncacheable[access_idx] 57010037SARM gem5 Developers .init(system->maxMasters()) 57110037SARM gem5 Developers .name(name() + "." + cstr + "_mshr_uncacheable") 57210037SARM gem5 Developers .desc("number of " + cstr + " MSHR uncacheable") 57310037SARM gem5 Developers .flags(total | nozero | nonan) 57410037SARM gem5 Developers ; 57510037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 57610037SARM gem5 Developers mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 57710037SARM gem5 Developers } 57810037SARM gem5 Developers } 57910037SARM gem5 Developers 58010037SARM gem5 Developers overallMshrUncacheable 58110037SARM gem5 Developers .name(name() + ".overall_mshr_uncacheable_misses") 58210037SARM gem5 Developers .desc("number of overall MSHR uncacheable misses") 58310037SARM gem5 Developers .flags(total | nozero | nonan) 58410037SARM gem5 Developers ; 58510037SARM gem5 Developers overallMshrUncacheable = 58610037SARM gem5 Developers SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 58710037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 58810037SARM gem5 Developers overallMshrUncacheable.subname(i, system->getMasterName(i)); 58910037SARM gem5 Developers } 59010037SARM gem5 Developers 59110037SARM gem5 Developers // MSHR miss latency statistics 59210037SARM gem5 Developers for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 59310037SARM gem5 Developers MemCmd cmd(access_idx); 59410037SARM gem5 Developers const string &cstr = cmd.toString(); 59510037SARM gem5 Developers 59610037SARM gem5 Developers mshr_uncacheable_lat[access_idx] 59710037SARM gem5 Developers .init(system->maxMasters()) 59810037SARM gem5 Developers .name(name() + "." + cstr + "_mshr_uncacheable_latency") 59910037SARM gem5 Developers .desc("number of " + cstr + " MSHR uncacheable cycles") 60010037SARM gem5 Developers .flags(total | nozero | nonan) 60110037SARM gem5 Developers ; 60210037SARM gem5 Developers for (int i = 0; i < system->maxMasters(); i++) { 60310037SARM gem5 Developers mshr_uncacheable_lat[access_idx].subname( 604 i, system->getMasterName(i)); 605 } 606 } 607 608 overallMshrUncacheableLatency 609 .name(name() + ".overall_mshr_uncacheable_latency") 610 .desc("number of overall MSHR uncacheable cycles") 611 .flags(total | nozero | nonan) 612 ; 613 overallMshrUncacheableLatency = 614 SUM_DEMAND(mshr_uncacheable_lat) + 615 SUM_NON_DEMAND(mshr_uncacheable_lat); 616 for (int i = 0; i < system->maxMasters(); i++) { 617 overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 618 } 619 620#if 0 621 // MSHR access formulas 622 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 623 MemCmd cmd(access_idx); 624 const string &cstr = cmd.toString(); 625 626 mshrAccesses[access_idx] 627 .name(name() + "." + cstr + "_mshr_accesses") 628 .desc("number of " + cstr + " mshr accesses(hits+misses)") 629 .flags(total | nozero | nonan) 630 ; 631 mshrAccesses[access_idx] = 632 mshr_hits[access_idx] + mshr_misses[access_idx] 633 + mshr_uncacheable[access_idx]; 634 } 635 636 demandMshrAccesses 637 .name(name() + ".demand_mshr_accesses") 638 .desc("number of demand (read+write) mshr accesses") 639 .flags(total | nozero | nonan) 640 ; 641 demandMshrAccesses = demandMshrHits + demandMshrMisses; 642 643 overallMshrAccesses 644 .name(name() + ".overall_mshr_accesses") 645 .desc("number of overall (read+write) mshr accesses") 646 .flags(total | nozero | nonan) 647 ; 648 overallMshrAccesses = overallMshrHits + overallMshrMisses 649 + overallMshrUncacheable; 650#endif 651 652 // MSHR miss rate formulas 653 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 654 MemCmd cmd(access_idx); 655 const string &cstr = cmd.toString(); 656 657 mshrMissRate[access_idx] 658 .name(name() + "." + cstr + "_mshr_miss_rate") 659 .desc("mshr miss rate for " + cstr + " accesses") 660 .flags(total | nozero | nonan) 661 ; 662 mshrMissRate[access_idx] = 663 mshr_misses[access_idx] / accesses[access_idx]; 664 665 for (int i = 0; i < system->maxMasters(); i++) { 666 mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 667 } 668 } 669 670 demandMshrMissRate 671 .name(name() + ".demand_mshr_miss_rate") 672 .desc("mshr miss rate for demand accesses") 673 .flags(total | nozero | nonan) 674 ; 675 demandMshrMissRate = demandMshrMisses / demandAccesses; 676 for (int i = 0; i < system->maxMasters(); i++) { 677 demandMshrMissRate.subname(i, system->getMasterName(i)); 678 } 679 680 overallMshrMissRate 681 .name(name() + ".overall_mshr_miss_rate") 682 .desc("mshr miss rate for overall accesses") 683 .flags(total | nozero | nonan) 684 ; 685 overallMshrMissRate = overallMshrMisses / overallAccesses; 686 for (int i = 0; i < system->maxMasters(); i++) { 687 overallMshrMissRate.subname(i, system->getMasterName(i)); 688 } 689 690 // mshrMiss latency formulas 691 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 692 MemCmd cmd(access_idx); 693 const string &cstr = cmd.toString(); 694 695 avgMshrMissLatency[access_idx] 696 .name(name() + "." + cstr + "_avg_mshr_miss_latency") 697 .desc("average " + cstr + " mshr miss latency") 698 .flags(total | nozero | nonan) 699 ; 700 avgMshrMissLatency[access_idx] = 701 mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 702 703 for (int i = 0; i < system->maxMasters(); i++) { 704 avgMshrMissLatency[access_idx].subname( 705 i, system->getMasterName(i)); 706 } 707 } 708 709 demandAvgMshrMissLatency 710 .name(name() + ".demand_avg_mshr_miss_latency") 711 .desc("average overall mshr miss latency") 712 .flags(total | nozero | nonan) 713 ; 714 demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 715 for (int i = 0; i < system->maxMasters(); i++) { 716 demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 717 } 718 719 overallAvgMshrMissLatency 720 .name(name() + ".overall_avg_mshr_miss_latency") 721 .desc("average overall mshr miss latency") 722 .flags(total | nozero | nonan) 723 ; 724 overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 725 for (int i = 0; i < system->maxMasters(); i++) { 726 overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 727 } 728 729 // mshrUncacheable latency formulas 730 for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 731 MemCmd cmd(access_idx); 732 const string &cstr = cmd.toString(); 733 734 avgMshrUncacheableLatency[access_idx] 735 .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 736 .desc("average " + cstr + " mshr uncacheable latency") 737 .flags(total | nozero | nonan) 738 ; 739 avgMshrUncacheableLatency[access_idx] = 740 mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 741 742 for (int i = 0; i < system->maxMasters(); i++) { 743 avgMshrUncacheableLatency[access_idx].subname( 744 i, system->getMasterName(i)); 745 } 746 } 747 748 overallAvgMshrUncacheableLatency 749 .name(name() + ".overall_avg_mshr_uncacheable_latency") 750 .desc("average overall mshr uncacheable latency") 751 .flags(total | nozero | nonan) 752 ; 753 overallAvgMshrUncacheableLatency = 754 overallMshrUncacheableLatency / overallMshrUncacheable; 755 for (int i = 0; i < system->maxMasters(); i++) { 756 overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 757 } 758 759} 760