abstract_mem.hh revision 9235
12124SN/A/* 22124SN/A * Copyright (c) 2012 ARM Limited 35268Sksewell@umich.edu * All rights reserved 45268Sksewell@umich.edu * 55268Sksewell@umich.edu * The license below extends only to copyright in the software and shall 65268Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75268Sksewell@umich.edu * property including but not limited to intellectual property relating 85268Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95268Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105268Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115268Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125268Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135268Sksewell@umich.edu * 145268Sksewell@umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 155268Sksewell@umich.edu * All rights reserved. 165268Sksewell@umich.edu * 175268Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 185268Sksewell@umich.edu * modification, are permitted provided that the following conditions are 195268Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 205268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 215268Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 225268Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 235268Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 245268Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 255268Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 265268Sksewell@umich.edu * this software without specific prior written permission. 275268Sksewell@umich.edu * 285268Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 295268Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 305268Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312022SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322649Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332649Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342706Sksewell@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352649Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362649Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372022SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382124SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392124SN/A * 402124SN/A * Authors: Ron Dreslinski 412124SN/A * Andreas Hansson 422124SN/A */ 432124SN/A 442124SN/A/** 455736Snate@binkert.org * @file 462239SN/A * AbstractMemory declaration 472124SN/A */ 482124SN/A 492124SN/A#ifndef __ABSTRACT_MEMORY_HH__ 502124SN/A#define __ABSTRACT_MEMORY_HH__ 516207Sksewell@umich.edu 522124SN/A#include "mem/mem_object.hh" 532742Sksewell@umich.edu#include "params/AbstractMemory.hh" 542022SN/A#include "sim/stats.hh" 552124SN/A 562022SN/A 572124SN/Aclass System; 582124SN/A 592124SN/A/** 602124SN/A * An abstract memory represents a contiguous block of physical 612742Sksewell@umich.edu * memory, with an associated address range, and also provides basic 622742Sksewell@umich.edu * functionality for reading and writing this memory without any 632742Sksewell@umich.edu * timing information. It is a MemObject since any subclass must have 642742Sksewell@umich.edu * at least one slave port. 652742Sksewell@umich.edu */ 662742Sksewell@umich.educlass AbstractMemory : public MemObject 672742Sksewell@umich.edu{ 682742Sksewell@umich.edu protected: 696207Sksewell@umich.edu 706207Sksewell@umich.edu // Address range of this memory 712742Sksewell@umich.edu AddrRange range; 722742Sksewell@umich.edu 732742Sksewell@umich.edu // Pointer to host memory used to implement this memory 742742Sksewell@umich.edu uint8_t* pmemAddr; 752742Sksewell@umich.edu 762742Sksewell@umich.edu // Enable specific memories to be reported to the configuration table 772022SN/A bool confTableReported; 782022SN/A 792124SN/A // Should the memory appear in the global address map 802022SN/A bool inAddrMap; 812124SN/A 822124SN/A class LockedAddr { 832124SN/A 842742Sksewell@umich.edu public: 852239SN/A // on alpha, minimum LL/SC granularity is 16 bytes, so lower 862124SN/A // bits need to masked off. 872124SN/A static const Addr Addr_Mask = 0xf; 882742Sksewell@umich.edu 892742Sksewell@umich.edu static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 902742Sksewell@umich.edu 912742Sksewell@umich.edu Addr addr; // locked address 922742Sksewell@umich.edu int contextId; // locking hw context 932742Sksewell@umich.edu 942742Sksewell@umich.edu // check for matching execution context 952742Sksewell@umich.edu bool matchesContext(Request *req) 964661Sksewell@umich.edu { 974661Sksewell@umich.edu return (contextId == req->contextId()); 984661Sksewell@umich.edu } 994661Sksewell@umich.edu 1004661Sksewell@umich.edu LockedAddr(Request *req) : addr(mask(req->getPaddr())), 1014661Sksewell@umich.edu contextId(req->contextId()) 1024661Sksewell@umich.edu { 1035222Sksewell@umich.edu } 1044661Sksewell@umich.edu // constructor for unserialization use 1054661Sksewell@umich.edu LockedAddr(Addr _addr, int _cid) : addr(_addr), contextId(_cid) 1065222Sksewell@umich.edu { 1074661Sksewell@umich.edu } 1084661Sksewell@umich.edu }; 1095222Sksewell@umich.edu 1104661Sksewell@umich.edu std::list<LockedAddr> lockedAddrList; 1114661Sksewell@umich.edu 1125222Sksewell@umich.edu // helper function for checkLockedAddrs(): we really want to 1134661Sksewell@umich.edu // inline a quick check for an empty locked addr list (hopefully 1144661Sksewell@umich.edu // the common case), and do the full list search (if necessary) in 1155222Sksewell@umich.edu // this out-of-line function 1164661Sksewell@umich.edu bool checkLockedAddrList(PacketPtr pkt); 1174661Sksewell@umich.edu 1184661Sksewell@umich.edu // Record the address of a load-locked operation so that we can 1194661Sksewell@umich.edu // clear the execution context's lock flag if a matching store is 1204661Sksewell@umich.edu // performed 1214661Sksewell@umich.edu void trackLoadLocked(PacketPtr pkt); 1224661Sksewell@umich.edu 1234661Sksewell@umich.edu // Compare a store address with any locked addresses so we can 1244661Sksewell@umich.edu // clear the lock flag appropriately. Return value set to 'false' 1254661Sksewell@umich.edu // if store operation should be suppressed (because it was a 1264661Sksewell@umich.edu // conditional store and the address was no longer locked by the 1272022SN/A // requesting execution context), 'true' otherwise. Note that 1282022SN/A // this method must be called on *all* stores since even 1292124SN/A // non-conditional stores must clear any matching lock addresses. 1302124SN/A bool writeOK(PacketPtr pkt) { 1312124SN/A Request *req = pkt->req; 1322124SN/A if (lockedAddrList.empty()) { 1332124SN/A // no locked addrs: nothing to check, store_conditional fails 1342124SN/A bool isLLSC = pkt->isLLSC(); 1352124SN/A if (isLLSC) { 1362124SN/A req->setExtraData(0); 1372124SN/A } 1384661Sksewell@umich.edu return !isLLSC; // only do write if not an sc 1392124SN/A } else { 1402124SN/A // iterate over list... 1412124SN/A return checkLockedAddrList(pkt); 1426207Sksewell@umich.edu } 1436207Sksewell@umich.edu } 1442124SN/A 1452124SN/A /** Number of total bytes read from this memory */ 1462124SN/A Stats::Vector bytesRead; 1472124SN/A /** Number of instruction bytes read from this memory */ 1482022SN/A Stats::Vector bytesInstRead; 1492022SN/A /** Number of bytes written to this memory */ 1506207Sksewell@umich.edu Stats::Vector bytesWritten; 1516207Sksewell@umich.edu /** Number of read requests */ 1526207Sksewell@umich.edu Stats::Vector numReads; 1532124SN/A /** Number of write requests */ 1542124SN/A Stats::Vector numWrites; 1552132SN/A /** Number of other requests */ 1562022SN/A Stats::Vector numOther; 1572124SN/A /** Read bandwidth from this memory */ 1582124SN/A Stats::Formula bwRead; 1592124SN/A /** Read bandwidth from this memory */ 1604661Sksewell@umich.edu Stats::Formula bwInstRead; 1612124SN/A /** Write bandwidth from this memory */ 1622124SN/A Stats::Formula bwWrite; 1636207Sksewell@umich.edu /** Total bandwidth from this memory */ 1646207Sksewell@umich.edu Stats::Formula bwTotal; 1656207Sksewell@umich.edu 1662124SN/A /** Pointor to the System object. 1673953Sstever@eecs.umich.edu * This is used for getting the number of masters in the system which is 1682124SN/A * needed when registering stats 1693953Sstever@eecs.umich.edu */ 1702124SN/A System *_system; 1713953Sstever@eecs.umich.edu 1722124SN/A 1732132SN/A private: 1746207Sksewell@umich.edu 1752124SN/A // Prevent copying 1762124SN/A AbstractMemory(const AbstractMemory&); 1772124SN/A 1782132SN/A // Prevent assignment 1792124SN/A AbstractMemory& operator=(const AbstractMemory&); 1805222Sksewell@umich.edu 1815222Sksewell@umich.edu public: 1825222Sksewell@umich.edu 1835222Sksewell@umich.edu typedef AbstractMemoryParams Params; 1845222Sksewell@umich.edu 1855222Sksewell@umich.edu AbstractMemory(const Params* p); 1865222Sksewell@umich.edu virtual ~AbstractMemory(); 1872124SN/A 1882124SN/A /** read the system pointer 1893953Sstever@eecs.umich.edu * Implemented for completeness with the setter 1902124SN/A * @return pointer to the system object */ 1914661Sksewell@umich.edu System* system() const { return _system; } 1922124SN/A 1932124SN/A /** Set the system pointer on this memory 1942124SN/A * This can't be done via a python parameter because the system needs 1952124SN/A * pointers to all the memories and the reverse would create a cycle in the 1962124SN/A * object graph. An init() this is set. 1972124SN/A * @param sys system pointer to set 1982124SN/A */ 1992124SN/A void system(System *sys) { _system = sys; } 2002124SN/A 2012132SN/A const Params * 2022124SN/A params() const 2032124SN/A { 2042124SN/A return dynamic_cast<const Params *>(_params); 2052132SN/A } 2062124SN/A 2075222Sksewell@umich.edu /** 2085222Sksewell@umich.edu * Get the address range 2095222Sksewell@umich.edu * 2105222Sksewell@umich.edu * @return a single contigous address range 2115222Sksewell@umich.edu */ 2125222Sksewell@umich.edu AddrRange getAddrRange() const; 2135222Sksewell@umich.edu 2142124SN/A /** 2152124SN/A * Get the memory size. 2162124SN/A * 2172124SN/A * @return the size of the memory 2182124SN/A */ 2192124SN/A uint64_t size() const { return range.size(); } 2202124SN/A 2212124SN/A /** 2222124SN/A * Get the start address. 2232124SN/A * 2242124SN/A * @return the start address of the memory 2252124SN/A */ 2262124SN/A Addr start() const { return range.start; } 2272124SN/A 2282124SN/A /** 2292124SN/A * Should this memory be passed to the kernel and part of the OS 2302124SN/A * physical memory layout. 2312124SN/A * 2322124SN/A * @return if this memory is reported 2332132SN/A */ 2342124SN/A bool isConfReported() const { return confTableReported; } 2352124SN/A 2362239SN/A /** 2372132SN/A * Some memories are used as shadow memories or should for other 2382239SN/A * reasons not be part of the global address map. 2395222Sksewell@umich.edu * 2405222Sksewell@umich.edu * @return if this memory is part of the address map 2415222Sksewell@umich.edu */ 2425222Sksewell@umich.edu bool isInAddrMap() const { return inAddrMap; } 2435222Sksewell@umich.edu 2445222Sksewell@umich.edu /** 2455222Sksewell@umich.edu * Perform an untimed memory access and update all the state 2462239SN/A * (e.g. locked addresses) and statistics accordingly. The packet 2472239SN/A * is turned into a response if required. 2482239SN/A * 2492239SN/A * @param pkt Packet performing the access 2502239SN/A */ 2512239SN/A void access(PacketPtr pkt); 2522239SN/A 2532239SN/A /** 2542124SN/A * Perform an untimed memory read or write without changing 2552124SN/A * anything but the memory itself. No stats are affected by this 2562124SN/A * access. In addition to normal accesses this also facilitates 2572124SN/A * print requests. 2582124SN/A * 2594661Sksewell@umich.edu * @param pkt Packet performing the access 2602124SN/A */ 2612124SN/A void functionalAccess(PacketPtr pkt); 2622124SN/A 2632132SN/A /** 2642239SN/A * Register Statistics 2655222Sksewell@umich.edu */ 2665222Sksewell@umich.edu virtual void regStats(); 2675222Sksewell@umich.edu 2685222Sksewell@umich.edu virtual void serialize(std::ostream &os); 2695222Sksewell@umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2705222Sksewell@umich.edu 2715222Sksewell@umich.edu}; 2722506SN/A 2734661Sksewell@umich.edu#endif //__ABSTRACT_MEMORY_HH__ 2742239SN/A