abstract_mem.hh revision 8931
12391SN/A/* 28931Sandreas.hansson@arm.com * Copyright (c) 2012 ARM Limited 38931Sandreas.hansson@arm.com * All rights reserved 48931Sandreas.hansson@arm.com * 58931Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68931Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78931Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88931Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98931Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108931Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118931Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128931Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138931Sandreas.hansson@arm.com * 142391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152391SN/A * All rights reserved. 162391SN/A * 172391SN/A * Redistribution and use in source and binary forms, with or without 182391SN/A * modification, are permitted provided that the following conditions are 192391SN/A * met: redistributions of source code must retain the above copyright 202391SN/A * notice, this list of conditions and the following disclaimer; 212391SN/A * redistributions in binary form must reproduce the above copyright 222391SN/A * notice, this list of conditions and the following disclaimer in the 232391SN/A * documentation and/or other materials provided with the distribution; 242391SN/A * neither the name of the copyright holders nor the names of its 252391SN/A * contributors may be used to endorse or promote products derived from 262391SN/A * this software without specific prior written permission. 272391SN/A * 282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ron Dreslinski 418931Sandreas.hansson@arm.com * Andreas Hansson 422391SN/A */ 432391SN/A 448931Sandreas.hansson@arm.com/** 458931Sandreas.hansson@arm.com * @file 468931Sandreas.hansson@arm.com * AbstractMemory declaration 472391SN/A */ 482391SN/A 498931Sandreas.hansson@arm.com#ifndef __ABSTRACT_MEMORY_HH__ 508931Sandreas.hansson@arm.com#define __ABSTRACT_MEMORY_HH__ 512391SN/A 522462SN/A#include "mem/mem_object.hh" 538931Sandreas.hansson@arm.com#include "params/AbstractMemory.hh" 548719SN/A#include "sim/stats.hh" 552462SN/A 568931Sandreas.hansson@arm.com/** 578931Sandreas.hansson@arm.com * An abstract memory represents a contiguous block of physical 588931Sandreas.hansson@arm.com * memory, with an associated address range, and also provides basic 598931Sandreas.hansson@arm.com * functionality for reading and writing this memory without any 608931Sandreas.hansson@arm.com * timing information. It is a MemObject since any subclass must have 618931Sandreas.hansson@arm.com * at least one slave port. 628931Sandreas.hansson@arm.com */ 638931Sandreas.hansson@arm.comclass AbstractMemory : public MemObject 642391SN/A{ 656107SN/A protected: 666107SN/A 678931Sandreas.hansson@arm.com // Address range of this memory 688931Sandreas.hansson@arm.com Range<Addr> range; 692413SN/A 708931Sandreas.hansson@arm.com // Pointer to host memory used to implement this memory 718931Sandreas.hansson@arm.com uint8_t* pmemAddr; 722413SN/A 738931Sandreas.hansson@arm.com // Enable specific memories to be reported to the configuration table 748931Sandreas.hansson@arm.com bool confTableReported; 752413SN/A 768931Sandreas.hansson@arm.com // Should the memory appear in the global address map 778931Sandreas.hansson@arm.com bool inAddrMap; 783170SN/A 793170SN/A class LockedAddr { 808931Sandreas.hansson@arm.com 813170SN/A public: 823170SN/A // on alpha, minimum LL/SC granularity is 16 bytes, so lower 833170SN/A // bits need to masked off. 843170SN/A static const Addr Addr_Mask = 0xf; 853170SN/A 863170SN/A static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 873170SN/A 885543SN/A Addr addr; // locked address 895714SN/A int contextId; // locking hw context 903170SN/A 913170SN/A // check for matching execution context 923170SN/A bool matchesContext(Request *req) 933170SN/A { 945714SN/A return (contextId == req->contextId()); 953170SN/A } 963170SN/A 978931Sandreas.hansson@arm.com LockedAddr(Request *req) : addr(mask(req->getPaddr())), 988931Sandreas.hansson@arm.com contextId(req->contextId()) 993170SN/A { 1003170SN/A } 1017733SN/A // constructor for unserialization use 1028931Sandreas.hansson@arm.com LockedAddr(Addr _addr, int _cid) : addr(_addr), contextId(_cid) 1037733SN/A { 1047733SN/A } 1053170SN/A }; 1063170SN/A 1073170SN/A std::list<LockedAddr> lockedAddrList; 1083170SN/A 1093170SN/A // helper function for checkLockedAddrs(): we really want to 1103170SN/A // inline a quick check for an empty locked addr list (hopefully 1113170SN/A // the common case), and do the full list search (if necessary) in 1123170SN/A // this out-of-line function 1134626SN/A bool checkLockedAddrList(PacketPtr pkt); 1143170SN/A 1153170SN/A // Record the address of a load-locked operation so that we can 1163170SN/A // clear the execution context's lock flag if a matching store is 1173170SN/A // performed 1184626SN/A void trackLoadLocked(PacketPtr pkt); 1193170SN/A 1203170SN/A // Compare a store address with any locked addresses so we can 1213170SN/A // clear the lock flag appropriately. Return value set to 'false' 1223170SN/A // if store operation should be suppressed (because it was a 1233170SN/A // conditional store and the address was no longer locked by the 1243170SN/A // requesting execution context), 'true' otherwise. Note that 1253170SN/A // this method must be called on *all* stores since even 1263170SN/A // non-conditional stores must clear any matching lock addresses. 1274626SN/A bool writeOK(PacketPtr pkt) { 1284626SN/A Request *req = pkt->req; 1293170SN/A if (lockedAddrList.empty()) { 1303170SN/A // no locked addrs: nothing to check, store_conditional fails 1316102SN/A bool isLLSC = pkt->isLLSC(); 1326102SN/A if (isLLSC) { 1334040SN/A req->setExtraData(0); 1343170SN/A } 1356102SN/A return !isLLSC; // only do write if not an sc 1363170SN/A } else { 1373170SN/A // iterate over list... 1384626SN/A return checkLockedAddrList(pkt); 1393170SN/A } 1403170SN/A } 1413170SN/A 1428719SN/A /** Number of total bytes read from this memory */ 1438719SN/A Stats::Scalar bytesRead; 1448719SN/A /** Number of instruction bytes read from this memory */ 1458719SN/A Stats::Scalar bytesInstRead; 1468719SN/A /** Number of bytes written to this memory */ 1478719SN/A Stats::Scalar bytesWritten; 1488719SN/A /** Number of read requests */ 1498719SN/A Stats::Scalar numReads; 1508719SN/A /** Number of write requests */ 1518719SN/A Stats::Scalar numWrites; 1528719SN/A /** Number of other requests */ 1538719SN/A Stats::Scalar numOther; 1548719SN/A /** Read bandwidth from this memory */ 1558719SN/A Stats::Formula bwRead; 1568719SN/A /** Read bandwidth from this memory */ 1578719SN/A Stats::Formula bwInstRead; 1588719SN/A /** Write bandwidth from this memory */ 1598719SN/A Stats::Formula bwWrite; 1608719SN/A /** Total bandwidth from this memory */ 1618719SN/A Stats::Formula bwTotal; 1628719SN/A 1638931Sandreas.hansson@arm.com private: 1648931Sandreas.hansson@arm.com 1658931Sandreas.hansson@arm.com // Prevent copying 1668931Sandreas.hansson@arm.com AbstractMemory(const AbstractMemory&); 1678931Sandreas.hansson@arm.com 1688931Sandreas.hansson@arm.com // Prevent assignment 1698931Sandreas.hansson@arm.com AbstractMemory& operator=(const AbstractMemory&); 1702391SN/A 1712391SN/A public: 1728931Sandreas.hansson@arm.com 1738931Sandreas.hansson@arm.com typedef AbstractMemoryParams Params; 1748931Sandreas.hansson@arm.com 1758931Sandreas.hansson@arm.com AbstractMemory(const Params* p); 1768931Sandreas.hansson@arm.com virtual ~AbstractMemory(); 1772391SN/A 1784762SN/A const Params * 1794762SN/A params() const 1804762SN/A { 1814762SN/A return dynamic_cast<const Params *>(_params); 1824762SN/A } 1834762SN/A 1848931Sandreas.hansson@arm.com /** 1858931Sandreas.hansson@arm.com * Get the address range 1868931Sandreas.hansson@arm.com * 1878931Sandreas.hansson@arm.com * @return a single contigous address range 1888931Sandreas.hansson@arm.com */ 1898931Sandreas.hansson@arm.com Range<Addr> getAddrRange(); 1902391SN/A 1918931Sandreas.hansson@arm.com /** 1928931Sandreas.hansson@arm.com * Get the memory size. 1938931Sandreas.hansson@arm.com * 1948931Sandreas.hansson@arm.com * @return the size of the memory 1958931Sandreas.hansson@arm.com */ 1968931Sandreas.hansson@arm.com uint64_t size() { return range.size(); } 1978923SN/A 1988931Sandreas.hansson@arm.com /** 1998931Sandreas.hansson@arm.com * Get the start address. 2008931Sandreas.hansson@arm.com * 2018931Sandreas.hansson@arm.com * @return the start address of the memory 2028931Sandreas.hansson@arm.com */ 2038931Sandreas.hansson@arm.com Addr start() { return range.start; } 2048923SN/A 2058931Sandreas.hansson@arm.com /** 2068931Sandreas.hansson@arm.com * Should this memory be passed to the kernel and part of the OS 2078931Sandreas.hansson@arm.com * physical memory layout. 2088931Sandreas.hansson@arm.com * 2098931Sandreas.hansson@arm.com * @return if this memory is reported 2108931Sandreas.hansson@arm.com */ 2118931Sandreas.hansson@arm.com bool isConfReported() const { return confTableReported; } 2122391SN/A 2138931Sandreas.hansson@arm.com /** 2148931Sandreas.hansson@arm.com * Some memories are used as shadow memories or should for other 2158931Sandreas.hansson@arm.com * reasons not be part of the global address map. 2168931Sandreas.hansson@arm.com * 2178931Sandreas.hansson@arm.com * @return if this memory is part of the address map 2188931Sandreas.hansson@arm.com */ 2198931Sandreas.hansson@arm.com bool isInAddrMap() const { return inAddrMap; } 2208931Sandreas.hansson@arm.com 2218931Sandreas.hansson@arm.com /** 2228931Sandreas.hansson@arm.com * Perform an untimed memory access and update all the state 2238931Sandreas.hansson@arm.com * (e.g. locked addresses) and statistics accordingly. The packet 2248931Sandreas.hansson@arm.com * is turned into a response if required. 2258931Sandreas.hansson@arm.com * 2268931Sandreas.hansson@arm.com * @param pkt Packet performing the access 2278931Sandreas.hansson@arm.com */ 2288931Sandreas.hansson@arm.com void access(PacketPtr pkt); 2298931Sandreas.hansson@arm.com 2308931Sandreas.hansson@arm.com /** 2318931Sandreas.hansson@arm.com * Perform an untimed memory read or write without changing 2328931Sandreas.hansson@arm.com * anything but the memory itself. No stats are affected by this 2338931Sandreas.hansson@arm.com * access. In addition to normal accesses this also facilitates 2348931Sandreas.hansson@arm.com * print requests. 2358931Sandreas.hansson@arm.com * 2368931Sandreas.hansson@arm.com * @param pkt Packet performing the access 2378931Sandreas.hansson@arm.com */ 2388931Sandreas.hansson@arm.com void functionalAccess(PacketPtr pkt); 2398931Sandreas.hansson@arm.com 2408931Sandreas.hansson@arm.com /** 2418719SN/A * Register Statistics 2428719SN/A */ 2438931Sandreas.hansson@arm.com virtual void regStats(); 2448719SN/A 2452391SN/A virtual void serialize(std::ostream &os); 2462391SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 2472497SN/A 2482391SN/A}; 2492391SN/A 2508931Sandreas.hansson@arm.com#endif //__ABSTRACT_MEMORY_HH__ 251