abstract_mem.hh revision 8719
111527Sdavid.guillen@arm.com/* 211527Sdavid.guillen@arm.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 311527Sdavid.guillen@arm.com * All rights reserved. 411527Sdavid.guillen@arm.com * 511527Sdavid.guillen@arm.com * Redistribution and use in source and binary forms, with or without 611527Sdavid.guillen@arm.com * modification, are permitted provided that the following conditions are 711527Sdavid.guillen@arm.com * met: redistributions of source code must retain the above copyright 811527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer; 911527Sdavid.guillen@arm.com * redistributions in binary form must reproduce the above copyright 1011527Sdavid.guillen@arm.com * notice, this list of conditions and the following disclaimer in the 1111527Sdavid.guillen@arm.com * documentation and/or other materials provided with the distribution; 1211527Sdavid.guillen@arm.com * neither the name of the copyright holders nor the names of its 1311527Sdavid.guillen@arm.com * contributors may be used to endorse or promote products derived from 1411527Sdavid.guillen@arm.com * this software without specific prior written permission. 1511527Sdavid.guillen@arm.com * 1611527Sdavid.guillen@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711527Sdavid.guillen@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811527Sdavid.guillen@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911527Sdavid.guillen@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011527Sdavid.guillen@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111527Sdavid.guillen@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211527Sdavid.guillen@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311527Sdavid.guillen@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411527Sdavid.guillen@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511527Sdavid.guillen@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611527Sdavid.guillen@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711527Sdavid.guillen@arm.com * 2811527Sdavid.guillen@arm.com * Authors: Ron Dreslinski 2911527Sdavid.guillen@arm.com */ 3011527Sdavid.guillen@arm.com 3111527Sdavid.guillen@arm.com/* @file 3211527Sdavid.guillen@arm.com */ 3311527Sdavid.guillen@arm.com 3411527Sdavid.guillen@arm.com#ifndef __PHYSICAL_MEMORY_HH__ 3511527Sdavid.guillen@arm.com#define __PHYSICAL_MEMORY_HH__ 3611527Sdavid.guillen@arm.com 3711527Sdavid.guillen@arm.com#include <map> 3811988Sandreas.sandberg@arm.com#include <string> 3911527Sdavid.guillen@arm.com 4011527Sdavid.guillen@arm.com#include "base/range.hh" 4111527Sdavid.guillen@arm.com#include "base/statistics.hh" 4211527Sdavid.guillen@arm.com#include "mem/mem_object.hh" 4311527Sdavid.guillen@arm.com#include "mem/packet.hh" 4411527Sdavid.guillen@arm.com#include "mem/tport.hh" 4511527Sdavid.guillen@arm.com#include "params/PhysicalMemory.hh" 4611527Sdavid.guillen@arm.com#include "sim/eventq.hh" 4711527Sdavid.guillen@arm.com#include "sim/stats.hh" 4811988Sandreas.sandberg@arm.com 4911988Sandreas.sandberg@arm.com// 5011988Sandreas.sandberg@arm.com// Functional model for a contiguous block of physical memory. (i.e. RAM) 5111988Sandreas.sandberg@arm.com// 5211527Sdavid.guillen@arm.comclass PhysicalMemory : public MemObject 5311527Sdavid.guillen@arm.com{ 5411988Sandreas.sandberg@arm.com protected: 55 56 class MemoryPort : public SimpleTimingPort 57 { 58 PhysicalMemory *memory; 59 60 public: 61 62 MemoryPort(const std::string &_name, PhysicalMemory *_memory); 63 64 protected: 65 66 virtual Tick recvAtomic(PacketPtr pkt); 67 68 virtual void recvFunctional(PacketPtr pkt); 69 70 virtual void recvRangeChange(); 71 72 virtual AddrRangeList getAddrRanges(); 73 74 virtual unsigned deviceBlockSize() const; 75 }; 76 77 int numPorts; 78 79 80 private: 81 // prevent copying of a MainMemory object 82 PhysicalMemory(const PhysicalMemory &specmem); 83 const PhysicalMemory &operator=(const PhysicalMemory &specmem); 84 85 protected: 86 87 class LockedAddr { 88 public: 89 // on alpha, minimum LL/SC granularity is 16 bytes, so lower 90 // bits need to masked off. 91 static const Addr Addr_Mask = 0xf; 92 93 static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 94 95 Addr addr; // locked address 96 int contextId; // locking hw context 97 98 // check for matching execution context 99 bool matchesContext(Request *req) 100 { 101 return (contextId == req->contextId()); 102 } 103 104 LockedAddr(Request *req) 105 : addr(mask(req->getPaddr())), 106 contextId(req->contextId()) 107 { 108 } 109 // constructor for unserialization use 110 LockedAddr(Addr _addr, int _cid) 111 : addr(_addr), contextId(_cid) 112 { 113 } 114 }; 115 116 std::list<LockedAddr> lockedAddrList; 117 118 // helper function for checkLockedAddrs(): we really want to 119 // inline a quick check for an empty locked addr list (hopefully 120 // the common case), and do the full list search (if necessary) in 121 // this out-of-line function 122 bool checkLockedAddrList(PacketPtr pkt); 123 124 // Record the address of a load-locked operation so that we can 125 // clear the execution context's lock flag if a matching store is 126 // performed 127 void trackLoadLocked(PacketPtr pkt); 128 129 // Compare a store address with any locked addresses so we can 130 // clear the lock flag appropriately. Return value set to 'false' 131 // if store operation should be suppressed (because it was a 132 // conditional store and the address was no longer locked by the 133 // requesting execution context), 'true' otherwise. Note that 134 // this method must be called on *all* stores since even 135 // non-conditional stores must clear any matching lock addresses. 136 bool writeOK(PacketPtr pkt) { 137 Request *req = pkt->req; 138 if (lockedAddrList.empty()) { 139 // no locked addrs: nothing to check, store_conditional fails 140 bool isLLSC = pkt->isLLSC(); 141 if (isLLSC) { 142 req->setExtraData(0); 143 } 144 return !isLLSC; // only do write if not an sc 145 } else { 146 // iterate over list... 147 return checkLockedAddrList(pkt); 148 } 149 } 150 151 uint8_t *pmemAddr; 152 Tick lat; 153 Tick lat_var; 154 std::vector<MemoryPort*> ports; 155 typedef std::vector<MemoryPort*>::iterator PortIterator; 156 157 uint64_t _size; 158 uint64_t _start; 159 160 /** Number of total bytes read from this memory */ 161 Stats::Scalar bytesRead; 162 /** Number of instruction bytes read from this memory */ 163 Stats::Scalar bytesInstRead; 164 /** Number of bytes written to this memory */ 165 Stats::Scalar bytesWritten; 166 /** Number of read requests */ 167 Stats::Scalar numReads; 168 /** Number of write requests */ 169 Stats::Scalar numWrites; 170 /** Number of other requests */ 171 Stats::Scalar numOther; 172 /** Read bandwidth from this memory */ 173 Stats::Formula bwRead; 174 /** Read bandwidth from this memory */ 175 Stats::Formula bwInstRead; 176 /** Write bandwidth from this memory */ 177 Stats::Formula bwWrite; 178 /** Total bandwidth from this memory */ 179 Stats::Formula bwTotal; 180 181 public: 182 uint64_t size() { return _size; } 183 uint64_t start() { return _start; } 184 185 public: 186 typedef PhysicalMemoryParams Params; 187 PhysicalMemory(const Params *p); 188 virtual ~PhysicalMemory(); 189 190 const Params * 191 params() const 192 { 193 return dynamic_cast<const Params *>(_params); 194 } 195 196 public: 197 unsigned deviceBlockSize() const; 198 AddrRangeList getAddrRanges(); 199 virtual Port *getPort(const std::string &if_name, int idx = -1); 200 void virtual init(); 201 unsigned int drain(Event *de); 202 203 protected: 204 Tick doAtomicAccess(PacketPtr pkt); 205 void doFunctionalAccess(PacketPtr pkt); 206 virtual Tick calculateLatency(PacketPtr pkt); 207 208 public: 209 /** 210 * Register Statistics 211 */ 212 void regStats(); 213 214 virtual void serialize(std::ostream &os); 215 virtual void unserialize(Checkpoint *cp, const std::string §ion); 216 217}; 218 219#endif //__PHYSICAL_MEMORY_HH__ 220