abstract_mem.hh revision 6107
12440SN/A/* 22440SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 32440SN/A * All rights reserved. 42440SN/A * 52440SN/A * Redistribution and use in source and binary forms, with or without 62440SN/A * modification, are permitted provided that the following conditions are 72440SN/A * met: redistributions of source code must retain the above copyright 82440SN/A * notice, this list of conditions and the following disclaimer; 92440SN/A * redistributions in binary form must reproduce the above copyright 102440SN/A * notice, this list of conditions and the following disclaimer in the 112440SN/A * documentation and/or other materials provided with the distribution; 122440SN/A * neither the name of the copyright holders nor the names of its 132440SN/A * contributors may be used to endorse or promote products derived from 142440SN/A * this software without specific prior written permission. 152440SN/A * 162440SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172440SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182440SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192440SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202440SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212440SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222440SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232440SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242440SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252440SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262440SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Ron Dreslinski 292665Ssaidi@eecs.umich.edu */ 302440SN/A 312440SN/A/* @file 322440SN/A */ 332440SN/A 342440SN/A#ifndef __PHYSICAL_MEMORY_HH__ 352972Sgblack@eecs.umich.edu#define __PHYSICAL_MEMORY_HH__ 366330Sgblack@eecs.umich.edu 378229Snate@binkert.org#include <map> 382440SN/A#include <string> 397720Sgblack@eecs.umich.edu 403120Sgblack@eecs.umich.edu#include "base/range.hh" 418300Schander.sudanthi@arm.com#include "mem/mem_object.hh" 422440SN/A#include "mem/packet.hh" 435569Snate@binkert.org#include "mem/tport.hh" 445569Snate@binkert.org#include "params/PhysicalMemory.hh" 457720Sgblack@eecs.umich.edu#include "sim/eventq.hh" 467720Sgblack@eecs.umich.edu 477720Sgblack@eecs.umich.edu// 487720Sgblack@eecs.umich.edu// Functional model for a contiguous block of physical memory. (i.e. RAM) 497720Sgblack@eecs.umich.edu// 507720Sgblack@eecs.umich.educlass PhysicalMemory : public MemObject 517720Sgblack@eecs.umich.edu{ 527720Sgblack@eecs.umich.edu protected: 537707Sgblack@eecs.umich.edu 545569Snate@binkert.org class MemoryPort : public SimpleTimingPort 555569Snate@binkert.org { 565569Snate@binkert.org PhysicalMemory *memory; 572440SN/A 585569Snate@binkert.org public: 595569Snate@binkert.org 604826Ssaidi@eecs.umich.edu MemoryPort(const std::string &_name, PhysicalMemory *_memory); 615569Snate@binkert.org 625569Snate@binkert.org protected: 635569Snate@binkert.org 645569Snate@binkert.org virtual Tick recvAtomic(PacketPtr pkt); 655569Snate@binkert.org 665569Snate@binkert.org virtual void recvFunctional(PacketPtr pkt); 672440SN/A 685569Snate@binkert.org virtual void recvStatusChange(Status status); 695569Snate@binkert.org 709180Sandreas.hansson@arm.com virtual void getDeviceAddressRanges(AddrRangeList &resp, 7110407Smitch.hayenga@arm.com bool &snoop); 722440SN/A 735569Snate@binkert.org virtual int deviceBlockSize(); 745569Snate@binkert.org }; 755569Snate@binkert.org 765569Snate@binkert.org int numPorts; 772440SN/A 785569Snate@binkert.org 792440SN/A private: 805569Snate@binkert.org // prevent copying of a MainMemory object 815569Snate@binkert.org PhysicalMemory(const PhysicalMemory &specmem); 822440SN/A const PhysicalMemory &operator=(const PhysicalMemory &specmem); 835569Snate@binkert.org 845569Snate@binkert.org protected: 855569Snate@binkert.org 862440SN/A class LockedAddr { 875569Snate@binkert.org public: 885569Snate@binkert.org // on alpha, minimum LL/SC granularity is 16 bytes, so lower 892440SN/A // bits need to masked off. 905569Snate@binkert.org static const Addr Addr_Mask = 0xf; 915569Snate@binkert.org 925569Snate@binkert.org static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 932440SN/A 945569Snate@binkert.org Addr addr; // locked address 955569Snate@binkert.org int contextId; // locking hw context 965569Snate@binkert.org 972440SN/A // check for matching execution context 985569Snate@binkert.org bool matchesContext(Request *req) 995569Snate@binkert.org { 1002440SN/A return (contextId == req->contextId()); 1016329Sgblack@eecs.umich.edu } 1026329Sgblack@eecs.umich.edu 1036329Sgblack@eecs.umich.edu LockedAddr(Request *req) 1046329Sgblack@eecs.umich.edu : addr(mask(req->getPaddr())), 1057693SAli.Saidi@ARM.com contextId(req->contextId()) 1067720Sgblack@eecs.umich.edu { 1077720Sgblack@eecs.umich.edu } 10810417Sandreas.hansson@arm.com }; 1097720Sgblack@eecs.umich.edu 1107720Sgblack@eecs.umich.edu std::list<LockedAddr> lockedAddrList; 1117720Sgblack@eecs.umich.edu 1127720Sgblack@eecs.umich.edu // helper function for checkLockedAddrs(): we really want to 1138300Schander.sudanthi@arm.com // inline a quick check for an empty locked addr list (hopefully 1148300Schander.sudanthi@arm.com // the common case), and do the full list search (if necessary) in 1158300Schander.sudanthi@arm.com // this out-of-line function 1168300Schander.sudanthi@arm.com bool checkLockedAddrList(PacketPtr pkt); 1178300Schander.sudanthi@arm.com 1188300Schander.sudanthi@arm.com // Record the address of a load-locked operation so that we can 1192440SN/A // clear the execution context's lock flag if a matching store is 1202440SN/A // performed 1215569Snate@binkert.org void trackLoadLocked(PacketPtr pkt); 122 123 // Compare a store address with any locked addresses so we can 124 // clear the lock flag appropriately. Return value set to 'false' 125 // if store operation should be suppressed (because it was a 126 // conditional store and the address was no longer locked by the 127 // requesting execution context), 'true' otherwise. Note that 128 // this method must be called on *all* stores since even 129 // non-conditional stores must clear any matching lock addresses. 130 bool writeOK(PacketPtr pkt) { 131 Request *req = pkt->req; 132 if (lockedAddrList.empty()) { 133 // no locked addrs: nothing to check, store_conditional fails 134 bool isLLSC = pkt->isLLSC(); 135 if (isLLSC) { 136 req->setExtraData(0); 137 } 138 return !isLLSC; // only do write if not an sc 139 } else { 140 // iterate over list... 141 return checkLockedAddrList(pkt); 142 } 143 } 144 145 uint8_t *pmemAddr; 146 int pagePtr; 147 Tick lat; 148 Tick lat_var; 149 std::vector<MemoryPort*> ports; 150 typedef std::vector<MemoryPort*>::iterator PortIterator; 151 152 uint64_t cachedSize; 153 uint64_t cachedStart; 154 public: 155 Addr new_page(); 156 uint64_t size() { return cachedSize; } 157 uint64_t start() { return cachedStart; } 158 159 public: 160 typedef PhysicalMemoryParams Params; 161 PhysicalMemory(const Params *p); 162 virtual ~PhysicalMemory(); 163 164 const Params * 165 params() const 166 { 167 return dynamic_cast<const Params *>(_params); 168 } 169 170 public: 171 int deviceBlockSize(); 172 void getAddressRanges(AddrRangeList &resp, bool &snoop); 173 virtual Port *getPort(const std::string &if_name, int idx = -1); 174 void virtual init(); 175 unsigned int drain(Event *de); 176 177 protected: 178 Tick doAtomicAccess(PacketPtr pkt); 179 void doFunctionalAccess(PacketPtr pkt); 180 virtual Tick calculateLatency(PacketPtr pkt); 181 void recvStatusChange(Port::Status status); 182 183 public: 184 virtual void serialize(std::ostream &os); 185 virtual void unserialize(Checkpoint *cp, const std::string §ion); 186 187}; 188 189#endif //__PHYSICAL_MEMORY_HH__ 190