abstract_mem.hh revision 6102
111723Sar4jc@virginia.edu/* 211723Sar4jc@virginia.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 311723Sar4jc@virginia.edu * All rights reserved. 411723Sar4jc@virginia.edu * 511723Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 611723Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 711723Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 811723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 911723Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1011723Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1111723Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1211723Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1311723Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1411723Sar4jc@virginia.edu * this software without specific prior written permission. 1511723Sar4jc@virginia.edu * 1611723Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711723Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811723Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911723Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011723Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111723Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211723Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311723Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411723Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511723Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611723Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711723Sar4jc@virginia.edu * 2811723Sar4jc@virginia.edu * Authors: Ron Dreslinski 2911723Sar4jc@virginia.edu */ 3011723Sar4jc@virginia.edu 3111723Sar4jc@virginia.edu/* @file 3211723Sar4jc@virginia.edu */ 3311723Sar4jc@virginia.edu 3411723Sar4jc@virginia.edu#ifndef __PHYSICAL_MEMORY_HH__ 3511723Sar4jc@virginia.edu#define __PHYSICAL_MEMORY_HH__ 3611723Sar4jc@virginia.edu 3711723Sar4jc@virginia.edu#include <map> 3811723Sar4jc@virginia.edu#include <string> 3911723Sar4jc@virginia.edu 4011723Sar4jc@virginia.edu#include "base/range.hh" 4111723Sar4jc@virginia.edu#include "mem/mem_object.hh" 4211723Sar4jc@virginia.edu#include "mem/packet.hh" 4312181Sgabeblack@google.com#include "mem/tport.hh" 4411723Sar4jc@virginia.edu#include "params/PhysicalMemory.hh" 4511723Sar4jc@virginia.edu#include "sim/eventq.hh" 4611723Sar4jc@virginia.edu 4711723Sar4jc@virginia.edu// 4811723Sar4jc@virginia.edu// Functional model for a contiguous block of physical memory. (i.e. RAM) 4911723Sar4jc@virginia.edu// 5011723Sar4jc@virginia.educlass PhysicalMemory : public MemObject 51{ 52 class MemoryPort : public SimpleTimingPort 53 { 54 PhysicalMemory *memory; 55 56 public: 57 58 MemoryPort(const std::string &_name, PhysicalMemory *_memory); 59 60 protected: 61 62 virtual Tick recvAtomic(PacketPtr pkt); 63 64 virtual void recvFunctional(PacketPtr pkt); 65 66 virtual void recvStatusChange(Status status); 67 68 virtual void getDeviceAddressRanges(AddrRangeList &resp, 69 bool &snoop); 70 71 virtual int deviceBlockSize(); 72 }; 73 74 int numPorts; 75 76 77 private: 78 // prevent copying of a MainMemory object 79 PhysicalMemory(const PhysicalMemory &specmem); 80 const PhysicalMemory &operator=(const PhysicalMemory &specmem); 81 82 protected: 83 84 class LockedAddr { 85 public: 86 // on alpha, minimum LL/SC granularity is 16 bytes, so lower 87 // bits need to masked off. 88 static const Addr Addr_Mask = 0xf; 89 90 static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 91 92 Addr addr; // locked address 93 int contextId; // locking hw context 94 95 // check for matching execution context 96 bool matchesContext(Request *req) 97 { 98 return (contextId == req->contextId()); 99 } 100 101 LockedAddr(Request *req) 102 : addr(mask(req->getPaddr())), 103 contextId(req->contextId()) 104 { 105 } 106 }; 107 108 std::list<LockedAddr> lockedAddrList; 109 110 // helper function for checkLockedAddrs(): we really want to 111 // inline a quick check for an empty locked addr list (hopefully 112 // the common case), and do the full list search (if necessary) in 113 // this out-of-line function 114 bool checkLockedAddrList(PacketPtr pkt); 115 116 // Record the address of a load-locked operation so that we can 117 // clear the execution context's lock flag if a matching store is 118 // performed 119 void trackLoadLocked(PacketPtr pkt); 120 121 // Compare a store address with any locked addresses so we can 122 // clear the lock flag appropriately. Return value set to 'false' 123 // if store operation should be suppressed (because it was a 124 // conditional store and the address was no longer locked by the 125 // requesting execution context), 'true' otherwise. Note that 126 // this method must be called on *all* stores since even 127 // non-conditional stores must clear any matching lock addresses. 128 bool writeOK(PacketPtr pkt) { 129 Request *req = pkt->req; 130 if (lockedAddrList.empty()) { 131 // no locked addrs: nothing to check, store_conditional fails 132 bool isLLSC = pkt->isLLSC(); 133 if (isLLSC) { 134 req->setExtraData(0); 135 } 136 return !isLLSC; // only do write if not an sc 137 } else { 138 // iterate over list... 139 return checkLockedAddrList(pkt); 140 } 141 } 142 143 uint8_t *pmemAddr; 144 int pagePtr; 145 Tick lat; 146 Tick lat_var; 147 std::vector<MemoryPort*> ports; 148 typedef std::vector<MemoryPort*>::iterator PortIterator; 149 150 uint64_t cachedSize; 151 uint64_t cachedStart; 152 public: 153 Addr new_page(); 154 uint64_t size() { return cachedSize; } 155 uint64_t start() { return cachedStart; } 156 157 public: 158 typedef PhysicalMemoryParams Params; 159 PhysicalMemory(const Params *p); 160 virtual ~PhysicalMemory(); 161 162 const Params * 163 params() const 164 { 165 return dynamic_cast<const Params *>(_params); 166 } 167 168 public: 169 int deviceBlockSize(); 170 void getAddressRanges(AddrRangeList &resp, bool &snoop); 171 virtual Port *getPort(const std::string &if_name, int idx = -1); 172 void virtual init(); 173 unsigned int drain(Event *de); 174 175 protected: 176 Tick doAtomicAccess(PacketPtr pkt); 177 void doFunctionalAccess(PacketPtr pkt); 178 virtual Tick calculateLatency(PacketPtr pkt); 179 void recvStatusChange(Port::Status status); 180 181 public: 182 virtual void serialize(std::ostream &os); 183 virtual void unserialize(Checkpoint *cp, const std::string §ion); 184 185}; 186 187#endif //__PHYSICAL_MEMORY_HH__ 188