XBar.py revision 5354
12086SN/A# Copyright (c) 2005-2008 The Regents of The University of Michigan 22086SN/A# All rights reserved. 35268Sksewell@umich.edu# 42086SN/A# Redistribution and use in source and binary forms, with or without 52086SN/A# modification, are permitted provided that the following conditions are 62086SN/A# met: redistributions of source code must retain the above copyright 72086SN/A# notice, this list of conditions and the following disclaimer; 82086SN/A# redistributions in binary form must reproduce the above copyright 92086SN/A# notice, this list of conditions and the following disclaimer in the 102086SN/A# documentation and/or other materials provided with the distribution; 112086SN/A# neither the name of the copyright holders nor the names of its 122086SN/A# contributors may be used to endorse or promote products derived from 132086SN/A# this software without specific prior written permission. 142086SN/A# 152086SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162086SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172086SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182086SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192086SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202086SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212086SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222086SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232086SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242086SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252086SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262086SN/A# 272086SN/A# Authors: Nathan Binkert 282665Ssaidi@eecs.umich.edu 292665Ssaidi@eecs.umich.edufrom m5 import build_env 302665Ssaidi@eecs.umich.edufrom m5.params import * 312686Sksewell@umich.edufrom m5.proxy import * 322086SN/Afrom MemObject import MemObject 334202Sbinkertn@umich.edu 342086SN/Aif build_env['FULL_SYSTEM']: 354202Sbinkertn@umich.edu from Device import BadAddr 368775Sgblack@eecs.umich.edu 379022Sgblack@eecs.umich.educlass Bus(MemObject): 388758Sgblack@eecs.umich.edu type = 'Bus' 394202Sbinkertn@umich.edu port = VectorPort("vector port for connecting devices") 408775Sgblack@eecs.umich.edu bus_id = Param.Int(0, "blah") 418745Sgblack@eecs.umich.edu clock = Param.Clock("1GHz", "bus clock speed") 426313Sgblack@eecs.umich.edu header_cycles = Param.Int(1, "cycles of overhead per transaction") 438775Sgblack@eecs.umich.edu width = Param.Int(64, "bus width (bytes)") 448775Sgblack@eecs.umich.edu responder_set = Param.Bool(False, "Did the user specify a default responder.") 458775Sgblack@eecs.umich.edu block_size = Param.Int(64, "The default block size if one isn't set by a device attached to the bus.") 468758Sgblack@eecs.umich.edu if build_env['FULL_SYSTEM']: 478775Sgblack@eecs.umich.edu responder = BadAddr(pio_addr=0x0, pio_latency="1ps") 488758Sgblack@eecs.umich.edu default = Port(Self.responder.pio, "Default port for requests that aren't handled by a device.") 498775Sgblack@eecs.umich.edu else: 508775Sgblack@eecs.umich.edu default = Port("Default port for requests that aren't handled by a device.") 514997Sgblack@eecs.umich.edu