XBar.py revision 10720
110719SMarco.Balboni@ARM.com# Copyright (c) 2012, 2015 ARM Limited 29036SN/A# All rights reserved. 39036SN/A# 49036SN/A# The license below extends only to copyright in the software and shall 59036SN/A# not be construed as granting a license to any other intellectual 69036SN/A# property including but not limited to intellectual property relating 79036SN/A# to a hardware implementation of the functionality of the software 89036SN/A# licensed hereunder. You may use the software subject to the license 99036SN/A# terms below provided that you ensure that this notice is replicated 109036SN/A# unmodified and in its entirety in all distributions of the software, 119036SN/A# modified or unmodified, in source code or in binary form. 129036SN/A# 135354SN/A# Copyright (c) 2005-2008 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 394486SN/A# Authors: Nathan Binkert 409036SN/A# Andreas Hansson 414486SN/A 429036SN/Afrom MemObject import MemObject 439524SN/Afrom System import System 443102SN/Afrom m5.params import * 459524SN/Afrom m5.proxy import * 4610399SN/Afrom m5.SimObject import SimObject 474486SN/A 4810405Sandreas.hansson@arm.comclass BaseXBar(MemObject): 4910405Sandreas.hansson@arm.com type = 'BaseXBar' 509036SN/A abstract = True 5110405Sandreas.hansson@arm.com cxx_header = "mem/xbar.hh" 5210719SMarco.Balboni@ARM.com 5310719SMarco.Balboni@ARM.com slave = VectorSlavePort("Vector port for connecting masters") 5410719SMarco.Balboni@ARM.com master = VectorMasterPort("Vector port for connecting slaves") 5510719SMarco.Balboni@ARM.com 5610719SMarco.Balboni@ARM.com # Latencies governing the time taken for the variuos paths a 5710719SMarco.Balboni@ARM.com # packet has through the crossbar. Note that the crossbar itself 5810719SMarco.Balboni@ARM.com # does not add the latency due to assumptions in the coherency 5910719SMarco.Balboni@ARM.com # mechanism. Instead the latency is annotated on the packet and 6010719SMarco.Balboni@ARM.com # left to the neighbouring modules. 6110719SMarco.Balboni@ARM.com # 6210719SMarco.Balboni@ARM.com # A request incurs the frontend latency, possibly snoop filter 6310719SMarco.Balboni@ARM.com # lookup latency, and forward latency. A response incurs the 6410719SMarco.Balboni@ARM.com # response latency. Frontend latency encompasses arbitration and 6510719SMarco.Balboni@ARM.com # deciding what to do when a request arrives. the forward latency 6610719SMarco.Balboni@ARM.com # is the latency involved once a decision is made to forward the 6710719SMarco.Balboni@ARM.com # request. The response latency, is similar to the forward 6810719SMarco.Balboni@ARM.com # latency, but for responses rather than requests. 6910720Sandreas.hansson@arm.com frontend_latency = Param.Cycles("Frontend latency") 7010720Sandreas.hansson@arm.com forward_latency = Param.Cycles("Forward latency") 7110720Sandreas.hansson@arm.com response_latency = Param.Cycles("Response latency") 7210719SMarco.Balboni@ARM.com 7310719SMarco.Balboni@ARM.com # Width governing the throughput of the crossbar 7410720Sandreas.hansson@arm.com width = Param.Unsigned("Datapath width per port (bytes)") 759036SN/A 769036SN/A # The default port can be left unconnected, or be used to connect 779036SN/A # a default slave port 789036SN/A default = MasterPort("Port for connecting an optional default slave") 799036SN/A 809036SN/A # The default port can be used unconditionally, or based on 819036SN/A # address range, in which case it may overlap with other 829036SN/A # ports. The default range is always checked first, thus creating 839036SN/A # a two-level hierarchical lookup. This is useful e.g. for the PCI 8410405Sandreas.hansson@arm.com # xbar configuration. 859036SN/A use_default_range = Param.Bool(False, "Perform address mapping for " \ 869036SN/A "the default port") 879036SN/A 8810405Sandreas.hansson@arm.comclass NoncoherentXBar(BaseXBar): 8910405Sandreas.hansson@arm.com type = 'NoncoherentXBar' 9010405Sandreas.hansson@arm.com cxx_header = "mem/noncoherent_xbar.hh" 919036SN/A 9210405Sandreas.hansson@arm.comclass CoherentXBar(BaseXBar): 9310405Sandreas.hansson@arm.com type = 'CoherentXBar' 9410405Sandreas.hansson@arm.com cxx_header = "mem/coherent_xbar.hh" 959524SN/A 9610719SMarco.Balboni@ARM.com # The coherent crossbar additionally has snoop responses that are 9710719SMarco.Balboni@ARM.com # forwarded after a specific latency. 9810720Sandreas.hansson@arm.com snoop_response_latency = Param.Cycles("Snoop response latency") 9910719SMarco.Balboni@ARM.com 10010719SMarco.Balboni@ARM.com # An optional snoop filter 10110719SMarco.Balboni@ARM.com snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter") 10210719SMarco.Balboni@ARM.com 10310405Sandreas.hansson@arm.com system = Param.System(Parent.any, "System that the crossbar belongs to.") 10410399SN/A 10510399SN/Aclass SnoopFilter(SimObject): 10610399SN/A type = 'SnoopFilter' 10710399SN/A cxx_header = "mem/snoop_filter.hh" 10810719SMarco.Balboni@ARM.com 10910719SMarco.Balboni@ARM.com # Lookup latency of the snoop filter, added to requests that pass 11010719SMarco.Balboni@ARM.com # through a coherent crossbar. 11110719SMarco.Balboni@ARM.com lookup_latency = Param.Cycles(1, "Lookup latency") 11210399SN/A 11310405Sandreas.hansson@arm.com system = Param.System(Parent.any, "System that the crossbar belongs to.") 11410720Sandreas.hansson@arm.com 11510720Sandreas.hansson@arm.com# We use a coherent crossbar to connect multiple masters to the L2 11610720Sandreas.hansson@arm.com# caches. Normally this crossbar would be part of the cache itself. 11710720Sandreas.hansson@arm.comclass L2XBar(CoherentXBar): 11810720Sandreas.hansson@arm.com # 256-bit crossbar by default 11910720Sandreas.hansson@arm.com width = 32 12010720Sandreas.hansson@arm.com 12110720Sandreas.hansson@arm.com # Assume that most of this is covered by the cache latencies, with 12210720Sandreas.hansson@arm.com # no more than a single pipeline stage for any packet. 12310720Sandreas.hansson@arm.com frontend_latency = 1 12410720Sandreas.hansson@arm.com forward_latency = 0 12510720Sandreas.hansson@arm.com response_latency = 1 12610720Sandreas.hansson@arm.com snoop_response_latency = 1 12710720Sandreas.hansson@arm.com 12810720Sandreas.hansson@arm.com# One of the key coherent crossbar instances is the system 12910720Sandreas.hansson@arm.com# interconnect, tying together the CPU clusters, GPUs, and any I/O 13010720Sandreas.hansson@arm.com# coherent masters, and DRAM controllers. 13110720Sandreas.hansson@arm.comclass SystemXBar(CoherentXBar): 13210720Sandreas.hansson@arm.com # 128-bit crossbar by default 13310720Sandreas.hansson@arm.com width = 16 13410720Sandreas.hansson@arm.com 13510720Sandreas.hansson@arm.com # A handful pipeline stages for each portion of the latency 13610720Sandreas.hansson@arm.com # contributions. 13710720Sandreas.hansson@arm.com frontend_latency = 3 13810720Sandreas.hansson@arm.com forward_latency = 4 13910720Sandreas.hansson@arm.com response_latency = 2 14010720Sandreas.hansson@arm.com snoop_response_latency = 4 14110720Sandreas.hansson@arm.com 14210720Sandreas.hansson@arm.com# In addition to the system interconnect, we typically also have one 14310720Sandreas.hansson@arm.com# or more on-chip I/O crossbars. Note that at some point we might want 14410720Sandreas.hansson@arm.com# to also define an off-chip I/O crossbar such as PCIe. 14510720Sandreas.hansson@arm.comclass IOXBar(NoncoherentXBar): 14610720Sandreas.hansson@arm.com # 128-bit crossbar by default 14710720Sandreas.hansson@arm.com width = 16 14810720Sandreas.hansson@arm.com 14910720Sandreas.hansson@arm.com # Assume a simpler datapath than a coherent crossbar, incuring 15010720Sandreas.hansson@arm.com # less pipeline stages for decision making and forwarding of 15110720Sandreas.hansson@arm.com # requests. 15210720Sandreas.hansson@arm.com frontend_latency = 2 15310720Sandreas.hansson@arm.com forward_latency = 1 15410720Sandreas.hansson@arm.com response_latency = 2 155