XBar.py revision 10399 
1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
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23# neither the name of the copyright holders nor the names of its
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25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38#
39# Authors: Nathan Binkert
40#          Andreas Hansson
41
42from MemObject import MemObject
43from System import System
44from m5.params import *
45from m5.proxy import *
46from m5.SimObject import SimObject
47
48class BaseBus(MemObject):
49    type = 'BaseBus'
50    abstract = True
51    cxx_header = "mem/bus.hh"
52    slave = VectorSlavePort("vector port for connecting masters")
53    master = VectorMasterPort("vector port for connecting slaves")
54    header_cycles = Param.Cycles(1, "cycles of overhead per transaction")
55    width = Param.Unsigned(8, "bus width (bytes)")
56
57    # The default port can be left unconnected, or be used to connect
58    # a default slave port
59    default = MasterPort("Port for connecting an optional default slave")
60
61    # The default port can be used unconditionally, or based on
62    # address range, in which case it may overlap with other
63    # ports. The default range is always checked first, thus creating
64    # a two-level hierarchical lookup. This is useful e.g. for the PCI
65    # bus configuration.
66    use_default_range = Param.Bool(False, "Perform address mapping for " \
67                                       "the default port")
68
69class NoncoherentBus(BaseBus):
70    type = 'NoncoherentBus'
71    cxx_header = "mem/noncoherent_bus.hh"
72
73class CoherentBus(BaseBus):
74    type = 'CoherentBus'
75    cxx_header = "mem/coherent_bus.hh"
76
77    system = Param.System(Parent.any, "System that the bus belongs to.")
78
79class SnoopFilter(SimObject):
80    type = 'SnoopFilter'
81    cxx_header = "mem/snoop_filter.hh"
82    lookup_latency = Param.Cycles(3, "lookup latency (cycles)")
83
84    system = Param.System(Parent.any, "System that the bus belongs to.")
85