DRAMCtrl.py revision 9728
15575SN/A# Copyright (c) 2012-2013 ARM Limited 25575SN/A# All rights reserved. 311570SCurtis.Dunham@arm.com# 48721SN/A# The license below extends only to copyright in the software and shall 58721SN/A# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37# Ani Udipi 38 39from m5.params import * 40from AbstractMemory import * 41 42# Enum for memory scheduling algorithms, currently First-Come 43# First-Served and a First-Row Hit then First-Come First-Served 44class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 45 46# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 47# column, bank and channel, respectively, and going from MSB to LSB. 48# Available are RaBaChCo and RaBaCoCh, that are suitable for an 49# open-page policy, optimising for sequential accesses hitting in the 50# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 51class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 52 53# Enum for the page policy, either open or close. 54class PageManage(Enum): vals = ['open', 'close'] 55 56# SimpleDRAM is a single-channel single-ported DRAM controller model 57# that aims to model the most important system-level performance 58# effects of a DRAM without getting into too much detail of the DRAM 59# itself. 60class SimpleDRAM(AbstractMemory): 61 type = 'SimpleDRAM' 62 cxx_header = "mem/simple_dram.hh" 63 64 @classmethod 65 def makeMultiChannel(cls, nbr_mem_ctrls, mem_start_addr, mem_size, 66 intlv_high_bit = 11): 67 """ 68 Make a multi-channel configuration of this class. 69 70 Create multiple instances of the specific class and set their 71 parameters such that the address range is interleaved between 72 them. 73 74 Returns a list of controllers. 75 """ 76 import math 77 from m5.util import fatal 78 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 79 if 2 ** intlv_bits != nbr_mem_ctrls: 80 fatal("Number of memory channels must be a power of 2") 81 mem_ctrls = [] 82 for i in xrange(nbr_mem_ctrls): 83 # The default interleaving granularity is tuned to match a 84 # row buffer size of 32 cache lines of 64 bytes (starting 85 # at bit 11 for 2048 bytes). There is unfortunately no 86 # good way of checking this at instantiation time. 87 mem_ctrls.append(cls(range = AddrRange(mem_start_addr, 88 size = mem_size, 89 intlvHighBit = \ 90 intlv_high_bit, 91 intlvBits = intlv_bits, 92 intlvMatch = i), 93 channels = nbr_mem_ctrls)) 94 return mem_ctrls 95 96 # single-ported on the system interface side, instantiate with a 97 # bus in front of the controller for multiple ports 98 port = SlavePort("Slave port") 99 100 # the basic configuration of the controller architecture 101 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 102 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 103 104 # threshold in percent for when to trigger writes and start 105 # emptying the write buffer as it starts to get full 106 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 107 108 # scheduler, address map and page policy 109 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 110 addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 111 page_policy = Param.PageManage('open', "Page closure management policy") 112 113 # pipeline latency of the controller and PHY, split into a 114 # frontend part and a backend part, with reads and writes serviced 115 # by the queues only seeing the frontend contribution, and reads 116 # serviced by the memory seeing the sum of the two 117 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 118 static_backend_latency = Param.Latency("10ns", "Static backend latency") 119 120 # the physical organisation of the DRAM 121 lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") 122 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 123 banks_per_rank = Param.Unsigned("Number of banks per rank") 124 # only used for the address mapping as the controller by 125 # construction is a single channel and multiple controllers have 126 # to be instantiated for a multi-channel configuration 127 channels = Param.Unsigned(1, "Number of channels") 128 129 # timing behaviour and constraints - all in nanoseconds 130 131 # the amount of time in nanoseconds from issuing an activate command 132 # to the data being available in the row buffer for a read/write 133 tRCD = Param.Latency("RAS to CAS delay") 134 135 # the time from issuing a read/write command to seeing the actual data 136 tCL = Param.Latency("CAS latency") 137 138 # minimum time between a precharge and subsequent activate 139 tRP = Param.Latency("Row precharge time") 140 141 # time to complete a burst transfer, typically the burst length 142 # divided by two due to the DDR bus, but by making it a parameter 143 # it is easier to also evaluate SDR memories like WideIO. 144 # This parameter has to account for bus width and burst length. 145 # Adjustment also necessary if cache line size is greater than 146 # data size read/written by one full burst. 147 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 148 149 # time taken to complete one refresh cycle (N rows in all banks) 150 tRFC = Param.Latency("Refresh cycle time") 151 152 # refresh command interval, how often a "ref" command needs 153 # to be sent. It is 7.8 us for a 64ms refresh requirement 154 tREFI = Param.Latency("Refresh command interval") 155 156 # write-to-read turn around penalty, assumed same as read-to-write 157 tWTR = Param.Latency("Write to read switching time") 158 159 # time window in which a maximum number of activates are allowed 160 # to take place, set to 0 to disable 161 tXAW = Param.Latency("X activation window") 162 activation_limit = Param.Unsigned("Max number of activates in window") 163 164 # Currently rolled into other params 165 ###################################################################### 166 167 # the minimum amount of time between a row being activated, and 168 # precharged (de-activated) 169 # tRAS - assumed to be 3 * tRP 170 171 # tRC - assumed to be 4 * tRP 172 173 # burst length for an access derived from peerBlockSize 174 175# A single DDR3 x64 interface (one command and address bus), with 176# default timings based on DDR3-1600 4 Gbit parts in an 8x8 177# configuration, which would amount to 4 Gbyte of memory. 178class DDR3_1600_x64(SimpleDRAM): 179 # Assuming 64 byte cache lines, and a 1kbyte page size per module 180 # (this depends on the memory density) 181 lines_per_rowbuffer = 128 182 183 # Use two ranks 184 ranks_per_channel = 2 185 186 # DDR3 has 8 banks in all configurations 187 banks_per_rank = 8 188 189 # DDR3-1600 11-11-11 190 tRCD = '13.75ns' 191 tCL = '13.75ns' 192 tRP = '13.75ns' 193 194 # Assuming 64 byte cache lines, across an x64 195 # interface, translates to BL8, 4 clocks @ 800 MHz 196 tBURST = '5ns' 197 198 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 199 tRFC = '300ns' 200 201 # DDR3, <=85C, half for >85C 202 tREFI = '7.8us' 203 204 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 205 tWTR = '7.5ns' 206 207 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 208 tXAW = '40ns' 209 activation_limit = 4 210 211 212# A single LPDDR2-S4 x32 interface (one command/address bus), with 213# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 214# configuration. 215class LPDDR2_S4_1066_x32(SimpleDRAM): 216 # Assuming 64 byte cache lines, use a 1kbyte page size, this 217 # depends on the memory density 218 lines_per_rowbuffer = 16 219 220 # Use a single rank 221 ranks_per_channel = 1 222 223 # LPDDR2-S4 has 8 banks in all configurations 224 banks_per_rank = 8 225 226 # Fixed at 15 ns 227 tRCD = '15ns' 228 229 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 230 tCL = '15ns' 231 232 # Pre-charge one bank 15 ns (all banks 18 ns) 233 tRP = '15ns' 234 235 # Assuming 64 byte cache lines, across a x32 DDR interface 236 # translates to two BL8, 8 clocks @ 533 MHz. Note that this is a 237 # simplification 238 tBURST = '15ns' 239 240 # LPDDR2-S4, 4 Gbit 241 tRFC = '130ns' 242 tREFI = '3.9us' 243 244 # Irrespective of speed grade, tWTR is 7.5 ns 245 tWTR = '7.5ns' 246 247 # Irrespective of density, tFAW is 50 ns 248 tXAW = '50ns' 249 activation_limit = 4 250 251# A single WideIO x128 interface (one command and address bus), with 252# default timings based on an estimated WIO-200 8 Gbit part. 253class WideIO_200_x128(SimpleDRAM): 254 # Assuming 64 byte cache lines, use a 4kbyte page size, this 255 # depends on the memory density 256 lines_per_rowbuffer = 64 257 258 # Use one rank for a one-high die stack 259 ranks_per_channel = 1 260 261 # WideIO has 4 banks in all configurations 262 banks_per_rank = 4 263 264 # WIO-200 265 tRCD = '18ns' 266 tCL = '18ns' 267 tRP = '18ns' 268 269 # Assuming 64 byte cache lines, across an x128 SDR interface, 270 # translates to BL4, 4 clocks @ 200 MHz 271 tBURST = '20ns' 272 273 # WIO 8 Gb 274 tRFC = '210ns' 275 276 # WIO 8 Gb, <=85C, half for >85C 277 tREFI = '3.9us' 278 279 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 280 tWTR = '15ns' 281 282 # Two instead of four activation window 283 tXAW = '50ns' 284 activation_limit = 2 285 286# A single LPDDR3 x32 interface (one command/address bus), with 287# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 288# configuration 289class LPDDR3_1600_x32(SimpleDRAM): 290 # 4 Gbit and 8 Gbit devices use a 1 kByte page size, so ssuming 64 291 # byte cache lines, that is 16 lines 292 lines_per_rowbuffer = 16 293 294 # Use a single rank 295 ranks_per_channel = 1 296 297 # LPDDR3 has 8 banks in all configurations 298 banks_per_rank = 8 299 300 # Fixed at 15 ns 301 tRCD = '15ns' 302 303 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 304 tCL = '15ns' 305 306 # Pre-charge one bank 15 ns (all banks 18 ns) 307 tRP = '15ns' 308 309 # Assuming 64 byte cache lines, across a x32 DDR interface 310 # translates to two bursts of BL8, 8 clocks @ 800 MHz 311 tBURST = '10ns' 312 313 # LPDDR3, 4 Gb 314 tRFC = '130ns' 315 tREFI = '3.9us' 316 317 # Irrespective of speed grade, tWTR is 7.5 ns 318 tWTR = '7.5ns' 319 320 # Irrespective of size, tFAW is 50 ns 321 tXAW = '50ns' 322 activation_limit = 4 323