DRAMCtrl.py revision 9566
18528SN/A# Copyright (c) 2012 ARM Limited 28528SN/A# All rights reserved. 38528SN/A# 49988Snilay@cs.wisc.edu# The license below extends only to copyright in the software and shall 58835SAli.Saidi@ARM.com# not be construed as granting a license to any other intellectual 69988Snilay@cs.wisc.edu# property including but not limited to intellectual property relating 78528SN/A# to a hardware implementation of the functionality of the software 88528SN/A# licensed hereunder. You may use the software subject to the license 98528SN/A# terms below provided that you ensure that this notice is replicated 108528SN/A# unmodified and in its entirety in all distributions of the software, 118528SN/A# modified or unmodified, in source code or in binary form. 128528SN/A# 1310315Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 1410513SAli.Saidi@ARM.com# modification, are permitted provided that the following conditions are 1511268Satgutier@umich.edu# met: redistributions of source code must retain the above copyright 1610513SAli.Saidi@ARM.com# notice, this list of conditions and the following disclaimer; 179885Sstever@gmail.com# redistributions in binary form must reproduce the above copyright 189885Sstever@gmail.com# notice, this list of conditions and the following disclaimer in the 1911268Satgutier@umich.edu# documentation and/or other materials provided with the distribution; 209055Ssaidi@eecs.umich.edu# neither the name of the copyright holders nor the names of its 219449SAli.Saidi@ARM.com# contributors may be used to endorse or promote products derived from 229988Snilay@cs.wisc.edu# this software without specific prior written permission. 2311312Santhony.gutierrez@amd.com# 2410513SAli.Saidi@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2510513SAli.Saidi@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2610038SAli.Saidi@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2710038SAli.Saidi@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2810038SAli.Saidi@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2910038SAli.Saidi@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3010038SAli.Saidi@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 318528SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211268Satgutier@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3310315Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 348528SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3510513SAli.Saidi@ARM.com# 3610513SAli.Saidi@ARM.com# Authors: Andreas Hansson 378528SN/A# Ani Udipi 3810513SAli.Saidi@ARM.com 3910636Snilay@cs.wisc.edufrom m5.params import * 4010736Snilay@cs.wisc.edufrom AbstractMemory import * 419079SAli.Saidi@ARM.com 4211219Snilay@cs.wisc.edu# Enum for memory scheduling algorithms, currently First-Come 438721SN/A# First-Served and a First-Row Hit then First-Come First-Served 449885Sstever@gmail.comclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 459885Sstever@gmail.com 4610038SAli.Saidi@ARM.com# Enum for the address mapping, currently corresponding to either 4711312Santhony.gutierrez@amd.com# optimising for sequential accesses hitting in the open row, or 4810038SAli.Saidi@ARM.com# striping across banks. 498528SN/Aclass AddrMap(Enum): vals = ['openmap', 'closemap'] 5011440SCurtis.Dunham@arm.com 5111440SCurtis.Dunham@arm.com# Enum for the page policy, either open or close. 528528SN/Aclass PageManage(Enum): vals = ['open', 'close'] 538528SN/A 548528SN/A# SimpleDRAM is a single-channel single-ported DRAM controller model 558528SN/A# that aims to model the most important system-level performance 568528SN/A# effects of a DRAM without getting into too much detail of the DRAM 578528SN/A# itself. 588528SN/Aclass SimpleDRAM(AbstractMemory): 5910513SAli.Saidi@ARM.com type = 'SimpleDRAM' 608528SN/A cxx_header = "mem/simple_dram.hh" 618528SN/A 628528SN/A # single-ported on the system interface side, instantiate with a 639885Sstever@gmail.com # bus in front of the controller for multiple ports 648528SN/A port = SlavePort("Slave port") 659988Snilay@cs.wisc.edu 6610513SAli.Saidi@ARM.com # the basic configuration of the controller architecture 678721SN/A write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 688721SN/A read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 698891SAli.Saidi@ARM.com 708891SAli.Saidi@ARM.com # threshold in percent for when to trigger writes and start 718528SN/A # emptying the write buffer as it starts to get full 728528SN/A write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 738528SN/A 748528SN/A # scheduler, address map and page policy 758528SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 768528SN/A addr_mapping = Param.AddrMap('openmap', "Address mapping policy") 779988Snilay@cs.wisc.edu page_policy = Param.PageManage('open', "Page closure management policy") 788528SN/A 798528SN/A # the physical organisation of the DRAM 808528SN/A lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") 818528SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 828528SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 838528SN/A # only used for the address mapping as the controller by 849988Snilay@cs.wisc.edu # construction is a single channel and multiple controllers have 858528SN/A # to be instantiated for a multi-channel configuration 868528SN/A channels = Param.Unsigned(1, "Number of channels") 878528SN/A 888528SN/A # timing behaviour and constraints - all in nanoseconds 898528SN/A 908528SN/A # the amount of time in nanoseconds from issuing an activate command 919988Snilay@cs.wisc.edu # to the data being available in the row buffer for a read/write 9211268Satgutier@umich.edu tRCD = Param.Latency("RAS to CAS delay") 938528SN/A 948528SN/A # the time from issuing a read/write command to seeing the actual data 959885Sstever@gmail.com tCL = Param.Latency("CAS latency") 969885Sstever@gmail.com 979885Sstever@gmail.com # minimum time between a precharge and subsequent activate 9810315Snilay@cs.wisc.edu tRP = Param.Latency("Row precharge time") 999988Snilay@cs.wisc.edu 10010315Snilay@cs.wisc.edu # time to complete a burst transfer, typically the burst length 1019885Sstever@gmail.com # divided by two due to the DDR bus, but by making it a parameter 1029885Sstever@gmail.com # it is easier to also evaluate SDR memories like WideIO. 1038528SN/A # This parameter has to account for bus width and burst length. 1048528SN/A # Adjustment also necessary if cache line size is greater than 10510451Snilay@cs.wisc.edu # data size read/written by one full burst. 10610315Snilay@cs.wisc.edu tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1078528SN/A 1089885Sstever@gmail.com # time taken to complete one refresh cycle (N rows in all banks) 1098528SN/A tRFC = Param.Latency("Refresh cycle time") 1108528SN/A 1118528SN/A # refresh command interval, how often a "ref" command needs 1128528SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 11310038SAli.Saidi@ARM.com tREFI = Param.Latency("Refresh command interval") 1148528SN/A 1159988Snilay@cs.wisc.edu # write-to-read turn around penalty, assumed same as read-to-write 1168528SN/A tWTR = Param.Latency("Write to read switching time") 1178528SN/A 1188528SN/A # time window in which a maximum number of activates are allowed 1199449SAli.Saidi@ARM.com # to take place, set to 0 to disable 12010038SAli.Saidi@ARM.com tXAW = Param.Latency("X activation window") 1218528SN/A activation_limit = Param.Unsigned("Max number of activates in window") 1228528SN/A 1238528SN/A # Currently rolled into other params 1248528SN/A ###################################################################### 1258528SN/A 1268528SN/A # the minimum amount of time between a row being activated, and 1278528SN/A # precharged (de-activated) 1288528SN/A # tRAS - assumed to be 3 * tRP 1299885Sstever@gmail.com 13010315Snilay@cs.wisc.edu # tRC - assumed to be 4 * tRP 1319449SAli.Saidi@ARM.com 1328528SN/A # burst length for an access derived from peerBlockSize 1338528SN/A 1348835SAli.Saidi@ARM.com# High-level model of a single DDR3 x64 interface (one command and 1358528SN/A# address bus), with default timings based on a DDR3-1600 4 Gbit part, 1368528SN/A# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4 1378528SN/A# configuration. 1388528SN/Aclass SimpleDDR3(SimpleDRAM): 13911103Snilay@cs.wisc.edu # Assuming 64 byte cache lines, use a 2kbyte page size, this 1409885Sstever@gmail.com # depends on the memory density 1418891SAli.Saidi@ARM.com lines_per_rowbuffer = 32 14210451Snilay@cs.wisc.edu 1439885Sstever@gmail.com # Use two ranks 14411219Snilay@cs.wisc.edu ranks_per_channel = 2 14510636Snilay@cs.wisc.edu 1469988Snilay@cs.wisc.edu # DDR3 has 8 banks in all configurations 1479449SAli.Saidi@ARM.com banks_per_rank = 8 14811014Sandreas.sandberg@arm.com 1498528SN/A # DDR3-1600 11-11-11 15010451Snilay@cs.wisc.edu tRCD = '13.75ns' 1518528SN/A tCL = '13.75ns' 1528835SAli.Saidi@ARM.com tRP = '13.75ns' 1539449SAli.Saidi@ARM.com 15410036SAli.Saidi@ARM.com # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4) 1558528SN/A # interface, translates to BL8, 4 clocks @ 800 MHz 1568835SAli.Saidi@ARM.com tBURST = '5ns' 1579885Sstever@gmail.com 15810451Snilay@cs.wisc.edu # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns 15910451Snilay@cs.wisc.edu tRFC = '300ns' 16011219Snilay@cs.wisc.edu 1618528SN/A # DDR3, <=85C, half for >85C 16210451Snilay@cs.wisc.edu tREFI = '7.8us' 1638528SN/A 1649885Sstever@gmail.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 1659885Sstever@gmail.com tWTR = '7.5ns' 16610451Snilay@cs.wisc.edu 1679885Sstever@gmail.com # With a 2kbyte page size, DDR3-1600 lands around 40 ns 1689885Sstever@gmail.com tXAW = '40ns' 1699988Snilay@cs.wisc.edu activation_limit = 4 1709885Sstever@gmail.com 17110036SAli.Saidi@ARM.com 1729885Sstever@gmail.com# High-level model of a single LPDDR2-S4 x64 interface (one 1739885Sstever@gmail.com# command/address bus), with default timings based on a LPDDR2-1066 17410038SAli.Saidi@ARM.com# 4Gbit part, which whould amount to 1 GByte of memory in 2x32 or 17510038SAli.Saidi@ARM.com# 2GByte in 4x16 configuration. 17610038SAli.Saidi@ARM.comclass SimpleLPDDR2_S4(SimpleDRAM): 17710038SAli.Saidi@ARM.com # Assuming 64 byte cache lines, use a 2kbyte page size, this 17810038SAli.Saidi@ARM.com # depends on the memory density 17910736Snilay@cs.wisc.edu lines_per_rowbuffer = 32 18010038SAli.Saidi@ARM.com 18110038SAli.Saidi@ARM.com # Use two ranks 18210038SAli.Saidi@ARM.com ranks_per_channel = 2 18310038SAli.Saidi@ARM.com 18410038SAli.Saidi@ARM.com # LPDDR2-S4 has 8 banks in all configurations 18510038SAli.Saidi@ARM.com banks_per_rank = 8 18610038SAli.Saidi@ARM.com 18710038SAli.Saidi@ARM.com # Fixed at 15 ns 18810038SAli.Saidi@ARM.com tRCD = '15ns' 18910038SAli.Saidi@ARM.com 19010038SAli.Saidi@ARM.com # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 19110038SAli.Saidi@ARM.com tCL = '15ns' 19210038SAli.Saidi@ARM.com 19310038SAli.Saidi@ARM.com # Pre-charge one bank 15 ns and all banks 18 ns 19410038SAli.Saidi@ARM.com tRP = '18ns' 19510038SAli.Saidi@ARM.com 19610038SAli.Saidi@ARM.com # Assuming 64 byte cache lines, across a x64 interface (2x32 or 19710038SAli.Saidi@ARM.com # 4x16), translates to BL8, 4 clocks @ 533 MHz 1988528SN/A tBURST = '7.5ns' 1998528SN/A 2008528SN/A # LPDDR2-S4, 4 Gb 2019988Snilay@cs.wisc.edu tRFC = '130ns' 20210038SAli.Saidi@ARM.com tREFI = '3.9us' 2038528SN/A 2048528SN/A # Irrespective of speed grade, tWTR is 7.5 ns 2058528SN/A tWTR = '7.5ns' 2068528SN/A 2078528SN/A # Irrespective of size, tFAW is 50 ns 2089885Sstever@gmail.com tXAW = '50ns' 2099988Snilay@cs.wisc.edu activation_limit = 4 21010038SAli.Saidi@ARM.com