DRAMCtrl.py revision 9972
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 50# column, bank and channel, respectively, and going from MSB to LSB. 51# Available are RaBaChCo and RaBaCoCh, that are suitable for an 52# open-page policy, optimising for sequential accesses hitting in the 53# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 54class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 55 56# Enum for the page policy, either open or close. 57class PageManage(Enum): vals = ['open', 'close'] 58 59# SimpleDRAM is a single-channel single-ported DRAM controller model 60# that aims to model the most important system-level performance 61# effects of a DRAM without getting into too much detail of the DRAM 62# itself. 63class SimpleDRAM(AbstractMemory): 64 type = 'SimpleDRAM' 65 cxx_header = "mem/simple_dram.hh" 66 67 # single-ported on the system interface side, instantiate with a 68 # bus in front of the controller for multiple ports 69 port = SlavePort("Slave port") 70 71 # the basic configuration of the controller architecture 72 write_buffer_size = Param.Unsigned(32, "Number of write queue entries") 73 read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 74 75 # threshold in percent for when to trigger writes and start 76 # emptying the write buffer as it starts to get full 77 write_high_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 78 79 # threshold in percentage for when to stop writes if the read 80 # queue has an entry. An optimisaton to give reads priority if 81 # sufficient number of writes are scheduled and write queue has 82 # sufficient number of free entries 83 write_low_thresh_perc = Param.Percent(0, "Threshold to stop writes") 84 85 # scheduler, address map and page policy 86 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 87 addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 88 page_policy = Param.PageManage('open', "Page closure management policy") 89 90 # pipeline latency of the controller and PHY, split into a 91 # frontend part and a backend part, with reads and writes serviced 92 # by the queues only seeing the frontend contribution, and reads 93 # serviced by the memory seeing the sum of the two 94 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 95 static_backend_latency = Param.Latency("10ns", "Static backend latency") 96 97 # the physical organisation of the DRAM 98 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 99 "device/chip") 100 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 101 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 102 "device/chip") 103 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 104 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 105 banks_per_rank = Param.Unsigned("Number of banks per rank") 106 # only used for the address mapping as the controller by 107 # construction is a single channel and multiple controllers have 108 # to be instantiated for a multi-channel configuration 109 channels = Param.Unsigned(1, "Number of channels") 110 111 # timing behaviour and constraints - all in nanoseconds 112 113 # the amount of time in nanoseconds from issuing an activate command 114 # to the data being available in the row buffer for a read/write 115 tRCD = Param.Latency("RAS to CAS delay") 116 117 # the time from issuing a read/write command to seeing the actual data 118 tCL = Param.Latency("CAS latency") 119 120 # minimum time between a precharge and subsequent activate 121 tRP = Param.Latency("Row precharge time") 122 123 # minimum time between an activate and a precharge to the same row 124 tRAS = Param.Latency("ACT to PRE delay") 125 126 # time to complete a burst transfer, typically the burst length 127 # divided by two due to the DDR bus, but by making it a parameter 128 # it is easier to also evaluate SDR memories like WideIO. 129 # This parameter has to account for burst length. 130 # Read/Write requests with data size larger than one full burst are broken 131 # down into multiple requests in the SimpleDRAM controller 132 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 133 134 # time taken to complete one refresh cycle (N rows in all banks) 135 tRFC = Param.Latency("Refresh cycle time") 136 137 # refresh command interval, how often a "ref" command needs 138 # to be sent. It is 7.8 us for a 64ms refresh requirement 139 tREFI = Param.Latency("Refresh command interval") 140 141 # write-to-read turn around penalty, assumed same as read-to-write 142 tWTR = Param.Latency("Write to read switching time") 143 144 # minimum row activate to row activate delay time 145 tRRD = Param.Latency("ACT to ACT delay") 146 147 # time window in which a maximum number of activates are allowed 148 # to take place, set to 0 to disable 149 tXAW = Param.Latency("X activation window") 150 activation_limit = Param.Unsigned("Max number of activates in window") 151 152 # Currently rolled into other params 153 ###################################################################### 154 155 # tRC - assumed to be tRAS + tRP 156 157# A single DDR3 x64 interface (one command and address bus), with 158# default timings based on DDR3-1600 4 Gbit parts in an 8x8 159# configuration, which would amount to 4 Gbyte of memory. 160class DDR3_1600_x64(SimpleDRAM): 161 # 8x8 configuration, 8 devices each with an 8-bit interface 162 device_bus_width = 8 163 164 # DDR3 is a BL8 device 165 burst_length = 8 166 167 # Each device has a page (row buffer) size of 1KB 168 # (this depends on the memory density) 169 device_rowbuffer_size = '1kB' 170 171 # 8x8 configuration, so 8 devices 172 devices_per_rank = 8 173 174 # Use two ranks 175 ranks_per_channel = 2 176 177 # DDR3 has 8 banks in all configurations 178 banks_per_rank = 8 179 180 # DDR3-1600 11-11-11-28 181 tRCD = '13.75ns' 182 tCL = '13.75ns' 183 tRP = '13.75ns' 184 tRAS = '35ns' 185 186 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 187 # Note this is a BL8 DDR device. 188 tBURST = '5ns' 189 190 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 191 tRFC = '300ns' 192 193 # DDR3, <=85C, half for >85C 194 tREFI = '7.8us' 195 196 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 197 tWTR = '7.5ns' 198 199 # Assume 5 CK for activate to activate for different banks 200 tRRD = '6.25ns' 201 202 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 203 tXAW = '40ns' 204 activation_limit = 4 205 206 207# A single LPDDR2-S4 x32 interface (one command/address bus), with 208# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 209# configuration. 210class LPDDR2_S4_1066_x32(SimpleDRAM): 211 # 1x32 configuration, 1 device with a 32-bit interface 212 device_bus_width = 32 213 214 # LPDDR2_S4 is a BL4 and BL8 device 215 burst_length = 8 216 217 # Each device has a page (row buffer) size of 1KB 218 # (this depends on the memory density) 219 device_rowbuffer_size = '1kB' 220 221 # 1x32 configuration, so 1 device 222 devices_per_rank = 1 223 224 # Use a single rank 225 ranks_per_channel = 1 226 227 # LPDDR2-S4 has 8 banks in all configurations 228 banks_per_rank = 8 229 230 # Fixed at 15 ns 231 tRCD = '15ns' 232 233 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 234 tCL = '15ns' 235 236 # Pre-charge one bank 15 ns (all banks 18 ns) 237 tRP = '15ns' 238 239 tRAS = '42ns' 240 241 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 242 # Note this is a BL8 DDR device. 243 # Requests larger than 32 bytes are broken down into multiple requests 244 # in the SimpleDRAM controller 245 tBURST = '7.5ns' 246 247 # LPDDR2-S4, 4 Gbit 248 tRFC = '130ns' 249 tREFI = '3.9us' 250 251 # Irrespective of speed grade, tWTR is 7.5 ns 252 tWTR = '7.5ns' 253 254 # Activate to activate irrespective of density and speed grade 255 tRRD = '10.0ns' 256 257 # Irrespective of density, tFAW is 50 ns 258 tXAW = '50ns' 259 activation_limit = 4 260 261# A single WideIO x128 interface (one command and address bus), with 262# default timings based on an estimated WIO-200 8 Gbit part. 263class WideIO_200_x128(SimpleDRAM): 264 # 1x128 configuration, 1 device with a 128-bit interface 265 device_bus_width = 128 266 267 # This is a BL4 device 268 burst_length = 4 269 270 # Each device has a page (row buffer) size of 4KB 271 # (this depends on the memory density) 272 device_rowbuffer_size = '4kB' 273 274 # 1x128 configuration, so 1 device 275 devices_per_rank = 1 276 277 # Use one rank for a one-high die stack 278 ranks_per_channel = 1 279 280 # WideIO has 4 banks in all configurations 281 banks_per_rank = 4 282 283 # WIO-200 284 tRCD = '18ns' 285 tCL = '18ns' 286 tRP = '18ns' 287 tRAS = '42ns' 288 289 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 290 # Note this is a BL4 SDR device. 291 tBURST = '20ns' 292 293 # WIO 8 Gb 294 tRFC = '210ns' 295 296 # WIO 8 Gb, <=85C, half for >85C 297 tREFI = '3.9us' 298 299 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 300 tWTR = '15ns' 301 302 # Activate to activate irrespective of density and speed grade 303 tRRD = '10.0ns' 304 305 # Two instead of four activation window 306 tXAW = '50ns' 307 activation_limit = 2 308 309# A single LPDDR3 x32 interface (one command/address bus), with 310# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 311# configuration 312class LPDDR3_1600_x32(SimpleDRAM): 313 # 1x32 configuration, 1 device with a 32-bit interface 314 device_bus_width = 32 315 316 # LPDDR3 is a BL8 device 317 burst_length = 8 318 319 # Each device has a page (row buffer) size of 1KB 320 # (this depends on the memory density) 321 device_rowbuffer_size = '1kB' 322 323 # 1x32 configuration, so 1 device 324 devices_per_rank = 1 325 326 # Use a single rank 327 ranks_per_channel = 1 328 329 # LPDDR3 has 8 banks in all configurations 330 banks_per_rank = 8 331 332 # Fixed at 15 ns 333 tRCD = '15ns' 334 335 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 336 tCL = '15ns' 337 338 tRAS = '42ns' 339 340 # Pre-charge one bank 15 ns (all banks 18 ns) 341 tRP = '15ns' 342 343 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 344 # Note this is a BL8 DDR device. 345 # Requests larger than 32 bytes are broken down into multiple requests 346 # in the SimpleDRAM controller 347 tBURST = '5ns' 348 349 # LPDDR3, 4 Gb 350 tRFC = '130ns' 351 tREFI = '3.9us' 352 353 # Irrespective of speed grade, tWTR is 7.5 ns 354 tWTR = '7.5ns' 355 356 # Activate to activate irrespective of density and speed grade 357 tRRD = '10.0ns' 358 359 # Irrespective of size, tFAW is 50 ns 360 tXAW = '50ns' 361 activation_limit = 4 362