DRAMCtrl.py revision 9726
19363Snilay@cs.wisc.edu# Copyright (c) 2012-2013 ARM Limited 29363Snilay@cs.wisc.edu# All rights reserved. 39363Snilay@cs.wisc.edu# 49363Snilay@cs.wisc.edu# The license below extends only to copyright in the software and shall 59363Snilay@cs.wisc.edu# not be construed as granting a license to any other intellectual 69363Snilay@cs.wisc.edu# property including but not limited to intellectual property relating 79363Snilay@cs.wisc.edu# to a hardware implementation of the functionality of the software 89363Snilay@cs.wisc.edu# licensed hereunder. You may use the software subject to the license 99363Snilay@cs.wisc.edu# terms below provided that you ensure that this notice is replicated 109363Snilay@cs.wisc.edu# unmodified and in its entirety in all distributions of the software, 119363Snilay@cs.wisc.edu# modified or unmodified, in source code or in binary form. 129363Snilay@cs.wisc.edu# 139363Snilay@cs.wisc.edu# Redistribution and use in source and binary forms, with or without 149363Snilay@cs.wisc.edu# modification, are permitted provided that the following conditions are 159363Snilay@cs.wisc.edu# met: redistributions of source code must retain the above copyright 169363Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer; 179363Snilay@cs.wisc.edu# redistributions in binary form must reproduce the above copyright 189363Snilay@cs.wisc.edu# notice, this list of conditions and the following disclaimer in the 199363Snilay@cs.wisc.edu# documentation and/or other materials provided with the distribution; 209363Snilay@cs.wisc.edu# neither the name of the copyright holders nor the names of its 219363Snilay@cs.wisc.edu# contributors may be used to endorse or promote products derived from 229363Snilay@cs.wisc.edu# this software without specific prior written permission. 239363Snilay@cs.wisc.edu# 249363Snilay@cs.wisc.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 259363Snilay@cs.wisc.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 269363Snilay@cs.wisc.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 279363Snilay@cs.wisc.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 289363Snilay@cs.wisc.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 299363Snilay@cs.wisc.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 309363Snilay@cs.wisc.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 319363Snilay@cs.wisc.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 329363Snilay@cs.wisc.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 339363Snilay@cs.wisc.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 349363Snilay@cs.wisc.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 359363Snilay@cs.wisc.edu# 369363Snilay@cs.wisc.edu# Authors: Andreas Hansson 379363Snilay@cs.wisc.edu# Ani Udipi 38 39from m5.params import * 40from AbstractMemory import * 41 42# Enum for memory scheduling algorithms, currently First-Come 43# First-Served and a First-Row Hit then First-Come First-Served 44class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 45 46# Enum for the address mapping. With Ra, Co, Ba and Ch denoting rank, 47# column, bank and channel, respectively, and going from MSB to LSB. 48# Available are RaBaChCo and RaBaCoCh, that are suitable for an 49# open-page policy, optimising for sequential accesses hitting in the 50# open row. For a closed-page policy, CoRaBaCh maximises parallelism. 51class AddrMap(Enum): vals = ['RaBaChCo', 'RaBaCoCh', 'CoRaBaCh'] 52 53# Enum for the page policy, either open or close. 54class PageManage(Enum): vals = ['open', 'close'] 55 56# SimpleDRAM is a single-channel single-ported DRAM controller model 57# that aims to model the most important system-level performance 58# effects of a DRAM without getting into too much detail of the DRAM 59# itself. 60class SimpleDRAM(AbstractMemory): 61 type = 'SimpleDRAM' 62 cxx_header = "mem/simple_dram.hh" 63 64 @classmethod 65 def makeMultiChannel(cls, nbr_mem_ctrls, mem_start_addr, mem_size, 66 intlv_high_bit = 11): 67 """ 68 Make a multi-channel configuration of this class. 69 70 Create multiple instances of the specific class and set their 71 parameters such that the address range is interleaved between 72 them. 73 74 Returns a list of controllers. 75 """ 76 import math 77 from m5.util import fatal 78 intlv_bits = int(math.log(nbr_mem_ctrls, 2)) 79 if 2 ** intlv_bits != nbr_mem_ctrls: 80 fatal("Number of memory channels must be a power of 2") 81 mem_ctrls = [] 82 for i in xrange(nbr_mem_ctrls): 83 # The default interleaving granularity is tuned to match a 84 # row buffer size of 32 cache lines of 64 bytes (starting 85 # at bit 11 for 2048 bytes). There is unfortunately no 86 # good way of checking this at instantiation time. 87 mem_ctrls.append(cls(range = AddrRange(mem_start_addr, 88 size = mem_size, 89 intlvHighBit = \ 90 intlv_high_bit, 91 intlvBits = intlv_bits, 92 intlvMatch = i), 93 channels = nbr_mem_ctrls)) 94 return mem_ctrls 95 96 # single-ported on the system interface side, instantiate with a 97 # bus in front of the controller for multiple ports 98 port = SlavePort("Slave port") 99 100 # the basic configuration of the controller architecture 101 write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 102 read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 103 104 # threshold in percent for when to trigger writes and start 105 # emptying the write buffer as it starts to get full 106 write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 107 108 # scheduler, address map and page policy 109 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 110 addr_mapping = Param.AddrMap('RaBaChCo', "Address mapping policy") 111 page_policy = Param.PageManage('open', "Page closure management policy") 112 113 # pipeline latency of the controller and PHY, split into a 114 # frontend part and a backend part, with reads and writes serviced 115 # by the queues only seeing the frontend contribution, and reads 116 # serviced by the memory seeing the sum of the two 117 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 118 static_backend_latency = Param.Latency("10ns", "Static backend latency") 119 120 # the physical organisation of the DRAM 121 lines_per_rowbuffer = Param.Unsigned("Row buffer size in cache lines") 122 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 123 banks_per_rank = Param.Unsigned("Number of banks per rank") 124 # only used for the address mapping as the controller by 125 # construction is a single channel and multiple controllers have 126 # to be instantiated for a multi-channel configuration 127 channels = Param.Unsigned(1, "Number of channels") 128 129 # timing behaviour and constraints - all in nanoseconds 130 131 # the amount of time in nanoseconds from issuing an activate command 132 # to the data being available in the row buffer for a read/write 133 tRCD = Param.Latency("RAS to CAS delay") 134 135 # the time from issuing a read/write command to seeing the actual data 136 tCL = Param.Latency("CAS latency") 137 138 # minimum time between a precharge and subsequent activate 139 tRP = Param.Latency("Row precharge time") 140 141 # time to complete a burst transfer, typically the burst length 142 # divided by two due to the DDR bus, but by making it a parameter 143 # it is easier to also evaluate SDR memories like WideIO. 144 # This parameter has to account for bus width and burst length. 145 # Adjustment also necessary if cache line size is greater than 146 # data size read/written by one full burst. 147 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 148 149 # time taken to complete one refresh cycle (N rows in all banks) 150 tRFC = Param.Latency("Refresh cycle time") 151 152 # refresh command interval, how often a "ref" command needs 153 # to be sent. It is 7.8 us for a 64ms refresh requirement 154 tREFI = Param.Latency("Refresh command interval") 155 156 # write-to-read turn around penalty, assumed same as read-to-write 157 tWTR = Param.Latency("Write to read switching time") 158 159 # time window in which a maximum number of activates are allowed 160 # to take place, set to 0 to disable 161 tXAW = Param.Latency("X activation window") 162 activation_limit = Param.Unsigned("Max number of activates in window") 163 164 # Currently rolled into other params 165 ###################################################################### 166 167 # the minimum amount of time between a row being activated, and 168 # precharged (de-activated) 169 # tRAS - assumed to be 3 * tRP 170 171 # tRC - assumed to be 4 * tRP 172 173 # burst length for an access derived from peerBlockSize 174 175# High-level model of a single DDR3 x64 interface (one command and 176# address bus), with default timings based on a DDR3-1600 4 Gbit part, 177# which would amount to 4 Gbyte of memory in 8x8 or 8 GByte in 16x4 178# configuration. 179class SimpleDDR3(SimpleDRAM): 180 # Assuming 64 byte cache lines, use a 2kbyte page size, this 181 # depends on the memory density 182 lines_per_rowbuffer = 32 183 184 # Use two ranks 185 ranks_per_channel = 2 186 187 # DDR3 has 8 banks in all configurations 188 banks_per_rank = 8 189 190 # DDR3-1600 11-11-11 191 tRCD = '13.75ns' 192 tCL = '13.75ns' 193 tRP = '13.75ns' 194 195 # Assuming 64 byte cache lines, across an x64 (8x8 or 16x4) 196 # interface, translates to BL8, 4 clocks @ 800 MHz 197 tBURST = '5ns' 198 199 # DDR3, 4 Gb has a tRFC of 240 CK and tCK = 1.25 ns 200 tRFC = '300ns' 201 202 # DDR3, <=85C, half for >85C 203 tREFI = '7.8us' 204 205 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 206 tWTR = '7.5ns' 207 208 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 209 tXAW = '40ns' 210 activation_limit = 4 211 212 213# High-level model of a single LPDDR2-S4 x32 interface (one 214# command/address bus), with default timings based on a LPDDR2-1066 215# 4 Gbit part 216class SimpleLPDDR2_S4(SimpleDRAM): 217 # Assuming 64 byte cache lines, use a 1kbyte page size, this 218 # depends on the memory density 219 lines_per_rowbuffer = 16 220 221 # Use a single rank 222 ranks_per_channel = 1 223 224 # LPDDR2-S4 has 8 banks in all configurations 225 banks_per_rank = 8 226 227 # Fixed at 15 ns 228 tRCD = '15ns' 229 230 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 231 tCL = '15ns' 232 233 # Pre-charge one bank 15 ns and all banks 18 ns 234 tRP = '18ns' 235 236 # Assuming 64 byte cache lines, across a x32 DDR interface 237 # translates to two BL8, 8 clocks @ 533 MHz. Note that this is a 238 # simplification 239 tBURST = '15ns' 240 241 # LPDDR2-S4, 4 Gbit 242 tRFC = '130ns' 243 tREFI = '3.9us' 244 245 # Irrespective of speed grade, tWTR is 7.5 ns 246 tWTR = '7.5ns' 247 248 # Irrespective of density, tFAW is 50 ns 249 tXAW = '50ns' 250 activation_limit = 4 251 252# High-level model of a single WideIO x128 interface (one command and 253# address bus), with default timings based on an estimated WIO-200 8 254# Gbit part. 255class SimpleWideIO(SimpleDRAM): 256 # Assuming 64 byte cache lines, use a 4kbyte page size, this 257 # depends on the memory density 258 lines_per_rowbuffer = 64 259 260 # Use one rank for a one-high die stack 261 ranks_per_channel = 1 262 263 # WideIO has 4 banks in all configurations 264 banks_per_rank = 4 265 266 # WIO-200 267 tRCD = '18ns' 268 tCL = '18ns' 269 tRP = '18ns' 270 271 # Assuming 64 byte cache lines, across an x128 SDR interface, 272 # translates to BL4, 4 clocks @ 200 MHz 273 tBURST = '20ns' 274 275 # WIO 8 Gb 276 tRFC = '210ns' 277 278 # WIO 8 Gb, <=85C, half for >85C 279 tREFI = '3.9us' 280 281 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 282 tWTR = '15ns' 283 284 # Two instead of four activation window 285 tXAW = '50ns' 286 activation_limit = 2 287 288# High-level model of a single LPDDR3 x32 interface (one 289# command/address bus), with default timings based on a LPDDR3-1600 4 290# Gbit part 291class SimpleLPDDR3(SimpleDRAM): 292 # 4 Gb and 8 Gb devices use a 1 kByte page size, so ssuming 64 byte 293 # cache lines, that is 16 lines 294 lines_per_rowbuffer = 16 295 296 # Use a single rank 297 ranks_per_channel = 1 298 299 # LPDDR3 has 8 banks in all configurations 300 banks_per_rank = 8 301 302 # Fixed at 15 ns 303 tRCD = '15ns' 304 305 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 306 tCL = '15ns' 307 308 # Pre-charge one bank 15 ns and all banks 18 ns 309 tRP = '18ns' 310 311 # Assuming 64 byte cache lines, across a x32 DDR interface 312 # translates to two bursts of BL8, 8 clocks @ 800 MHz 313 tBURST = '10ns' 314 315 # LPDDR3, 4 Gb 316 tRFC = '130ns' 317 tREFI = '3.9us' 318 319 # Irrespective of speed grade, tWTR is 7.5 ns 320 tWTR = '7.5ns' 321 322 # Irrespective of size, tFAW is 50 ns 323 tXAW = '50ns' 324 activation_limit = 4 325