DRAMCtrl.py revision 9488
113481Sgiacomo.travaglini@arm.com# Copyright (c) 2012 ARM Limited 213481Sgiacomo.travaglini@arm.com# All rights reserved. 313481Sgiacomo.travaglini@arm.com# 413481Sgiacomo.travaglini@arm.com# The license below extends only to copyright in the software and shall 513481Sgiacomo.travaglini@arm.com# not be construed as granting a license to any other intellectual 613481Sgiacomo.travaglini@arm.com# property including but not limited to intellectual property relating 713481Sgiacomo.travaglini@arm.com# to a hardware implementation of the functionality of the software 813481Sgiacomo.travaglini@arm.com# licensed hereunder. You may use the software subject to the license 913481Sgiacomo.travaglini@arm.com# terms below provided that you ensure that this notice is replicated 1013481Sgiacomo.travaglini@arm.com# unmodified and in its entirety in all distributions of the software, 1113481Sgiacomo.travaglini@arm.com# modified or unmodified, in source code or in binary form. 1213481Sgiacomo.travaglini@arm.com# 1313481Sgiacomo.travaglini@arm.com# Redistribution and use in source and binary forms, with or without 1413481Sgiacomo.travaglini@arm.com# modification, are permitted provided that the following conditions are 1513481Sgiacomo.travaglini@arm.com# met: redistributions of source code must retain the above copyright 1613481Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer; 1713481Sgiacomo.travaglini@arm.com# redistributions in binary form must reproduce the above copyright 1813481Sgiacomo.travaglini@arm.com# notice, this list of conditions and the following disclaimer in the 1913481Sgiacomo.travaglini@arm.com# documentation and/or other materials provided with the distribution; 2013481Sgiacomo.travaglini@arm.com# neither the name of the copyright holders nor the names of its 2113481Sgiacomo.travaglini@arm.com# contributors may be used to endorse or promote products derived from 2213481Sgiacomo.travaglini@arm.com# this software without specific prior written permission. 2313481Sgiacomo.travaglini@arm.com# 2413481Sgiacomo.travaglini@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2513481Sgiacomo.travaglini@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2613481Sgiacomo.travaglini@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2713481Sgiacomo.travaglini@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2813481Sgiacomo.travaglini@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2913481Sgiacomo.travaglini@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3013481Sgiacomo.travaglini@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3113481Sgiacomo.travaglini@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3213481Sgiacomo.travaglini@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3313481Sgiacomo.travaglini@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3413481Sgiacomo.travaglini@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3513481Sgiacomo.travaglini@arm.com# 3613481Sgiacomo.travaglini@arm.com# Authors: Andreas Hansson 3713481Sgiacomo.travaglini@arm.com# Ani Udipi 3813481Sgiacomo.travaglini@arm.com 3913481Sgiacomo.travaglini@arm.comfrom m5.params import * 4013481Sgiacomo.travaglini@arm.comfrom AbstractMemory import * 4113481Sgiacomo.travaglini@arm.com 4213481Sgiacomo.travaglini@arm.com# Enum for memory scheduling algorithms, currently First-Come 4313481Sgiacomo.travaglini@arm.com# First-Served and a First-Row Hit then First-Come First-Served 4413481Sgiacomo.travaglini@arm.comclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 4513481Sgiacomo.travaglini@arm.com 4613481Sgiacomo.travaglini@arm.com# Enum for the address mapping, currently corresponding to either 4713481Sgiacomo.travaglini@arm.com# optimising for sequential accesses hitting in the open row, or 4813481Sgiacomo.travaglini@arm.com# striping across banks. 4913481Sgiacomo.travaglini@arm.comclass AddrMap(Enum): vals = ['openmap', 'closemap'] 5013481Sgiacomo.travaglini@arm.com 5113481Sgiacomo.travaglini@arm.com# Enum for the page policy, either open or close. 5213481Sgiacomo.travaglini@arm.comclass PageManage(Enum): vals = ['open', 'close'] 5313481Sgiacomo.travaglini@arm.com 5413481Sgiacomo.travaglini@arm.com# SimpleDRAM is a single-channel single-ported DRAM controller model 5513481Sgiacomo.travaglini@arm.com# that aims to model the most important system-level performance 5613481Sgiacomo.travaglini@arm.com# effects of a DRAM without getting into too much detail of the DRAM 5713481Sgiacomo.travaglini@arm.com# itself. 5813481Sgiacomo.travaglini@arm.comclass SimpleDRAM(AbstractMemory): 5913481Sgiacomo.travaglini@arm.com type = 'SimpleDRAM' 6013481Sgiacomo.travaglini@arm.com cxx_header = "mem/simple_dram.hh" 6113481Sgiacomo.travaglini@arm.com 6213481Sgiacomo.travaglini@arm.com # single-ported on the system interface side, instantiate with a 6313481Sgiacomo.travaglini@arm.com # bus in front of the controller for multiple ports 6413481Sgiacomo.travaglini@arm.com port = SlavePort("Slave port") 6513481Sgiacomo.travaglini@arm.com 6613481Sgiacomo.travaglini@arm.com # the physical organisation of the DRAM 6713481Sgiacomo.travaglini@arm.com lines_per_rowbuffer = Param.Unsigned(64, "Row buffer size in cache lines") 6813481Sgiacomo.travaglini@arm.com ranks_per_channel = Param.Unsigned(2, "Number of ranks per channel") 6913481Sgiacomo.travaglini@arm.com banks_per_rank = Param.Unsigned(8, "Number of banks per rank") 7013481Sgiacomo.travaglini@arm.com 7113481Sgiacomo.travaglini@arm.com # the basic configuration of the controller architecture 7213481Sgiacomo.travaglini@arm.com write_buffer_size = Param.Unsigned(32, "Number of read queue entries") 7313481Sgiacomo.travaglini@arm.com read_buffer_size = Param.Unsigned(32, "Number of write queue entries") 7413481Sgiacomo.travaglini@arm.com 7513481Sgiacomo.travaglini@arm.com # threshold in percent for when to trigger writes and start 7613481Sgiacomo.travaglini@arm.com # emptying the write buffer as it starts to get full 7713481Sgiacomo.travaglini@arm.com write_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 7813481Sgiacomo.travaglini@arm.com 7913481Sgiacomo.travaglini@arm.com # scheduler, address map and page policy 8013481Sgiacomo.travaglini@arm.com mem_sched_policy = Param.MemSched('fcfs', "Memory scheduling policy") 8113481Sgiacomo.travaglini@arm.com addr_mapping = Param.AddrMap('openmap', "Address mapping policy") 8213481Sgiacomo.travaglini@arm.com page_policy = Param.PageManage('open', "Page closure management policy") 8313481Sgiacomo.travaglini@arm.com 8413481Sgiacomo.travaglini@arm.com # timing behaviour and constraints - all in nanoseconds 8513481Sgiacomo.travaglini@arm.com 8613481Sgiacomo.travaglini@arm.com # the amount of time in nanoseconds from issuing an activate command 8713481Sgiacomo.travaglini@arm.com # to the data being available in the row buffer for a read/write 8813481Sgiacomo.travaglini@arm.com tRCD = Param.Latency("14ns", "RAS to CAS delay") 8913481Sgiacomo.travaglini@arm.com 9013481Sgiacomo.travaglini@arm.com # the time from issuing a read/write command to seeing the actual data 9113481Sgiacomo.travaglini@arm.com tCL = Param.Latency("14ns", "CAS latency") 9213481Sgiacomo.travaglini@arm.com 9313481Sgiacomo.travaglini@arm.com # minimum time between a precharge and subsequent activate 9413481Sgiacomo.travaglini@arm.com tRP = Param.Latency("14ns", "Row precharge time") 9513481Sgiacomo.travaglini@arm.com 9613481Sgiacomo.travaglini@arm.com # time to complete a burst transfer, typically the burst length 9713481Sgiacomo.travaglini@arm.com # divided by two due to the DDR bus, but by making it a parameter 9813481Sgiacomo.travaglini@arm.com # it is easier to also evaluate SDR memories like WideIO. 9913481Sgiacomo.travaglini@arm.com # This parameter has to account for bus width and burst length. 10013481Sgiacomo.travaglini@arm.com # Adjustment also necessary if cache line size is greater than 10113481Sgiacomo.travaglini@arm.com # data size read/written by one full burst. 10213481Sgiacomo.travaglini@arm.com tBURST = Param.Latency("4ns", 10313481Sgiacomo.travaglini@arm.com "Burst duration (for DDR burst length / 2 cycles)") 10413481Sgiacomo.travaglini@arm.com 10513481Sgiacomo.travaglini@arm.com # time taken to complete one refresh cycle (N rows in all banks) 10613481Sgiacomo.travaglini@arm.com tRFC = Param.Latency("300ns", "Refresh cycle time") 10713481Sgiacomo.travaglini@arm.com 10813481Sgiacomo.travaglini@arm.com # refresh command interval, how often a "ref" command needs 10913481Sgiacomo.travaglini@arm.com # to be sent. It is 7.8 us for a 64ms refresh requirement 11013481Sgiacomo.travaglini@arm.com tREFI = Param.Latency("7.8us", "Refresh command interval") 11113481Sgiacomo.travaglini@arm.com 11213481Sgiacomo.travaglini@arm.com # write-to-read turn around penalty, assumed same as read-to-write 11313481Sgiacomo.travaglini@arm.com tWTR = Param.Latency("1ns", "Write to read switching time") 11413481Sgiacomo.travaglini@arm.com 11513481Sgiacomo.travaglini@arm.com # time window in which a maximum number of activates are allowed 11613481Sgiacomo.travaglini@arm.com # to take place, set to 0 to disable 11713481Sgiacomo.travaglini@arm.com tXAW = Param.Latency("0ns", "X activation window") 11813481Sgiacomo.travaglini@arm.com activation_limit = Param.Unsigned(4, "Max number of activates in window") 11913481Sgiacomo.travaglini@arm.com 12013481Sgiacomo.travaglini@arm.com # Currently rolled into other params 12113481Sgiacomo.travaglini@arm.com ###################################################################### 12213481Sgiacomo.travaglini@arm.com 12313481Sgiacomo.travaglini@arm.com # the minimum amount of time between a row being activated, and 12413481Sgiacomo.travaglini@arm.com # precharged (de-activated) 12513481Sgiacomo.travaglini@arm.com # tRAS - assumed to be 3 * tRP 12613481Sgiacomo.travaglini@arm.com 12713481Sgiacomo.travaglini@arm.com # tRC - assumed to be 4 * tRP 12813481Sgiacomo.travaglini@arm.com 12913481Sgiacomo.travaglini@arm.com # burst length for an access derived from peerBlockSize 13013481Sgiacomo.travaglini@arm.com