DRAMCtrl.py revision 14038
112706Swendy.elsasser@arm.com# Copyright (c) 2012-2018 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 1410864Sjungma@eit.uni-kl.de# Copyright (c) 2015 University of Kaiserslautern 1511186Serfan.azarkhish@unibo.it# Copyright (c) 2015 The University of Bologna 169831SN/A# All rights reserved. 179831SN/A# 189243SN/A# Redistribution and use in source and binary forms, with or without 199243SN/A# modification, are permitted provided that the following conditions are 209243SN/A# met: redistributions of source code must retain the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer; 229243SN/A# redistributions in binary form must reproduce the above copyright 239243SN/A# notice, this list of conditions and the following disclaimer in the 249243SN/A# documentation and/or other materials provided with the distribution; 259243SN/A# neither the name of the copyright holders nor the names of its 269243SN/A# contributors may be used to endorse or promote products derived from 279243SN/A# this software without specific prior written permission. 289243SN/A# 299243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 309243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 319243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 329243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 339243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409243SN/A# 419243SN/A# Authors: Andreas Hansson 429243SN/A# Ani Udipi 4310864Sjungma@eit.uni-kl.de# Omar Naji 4410864Sjungma@eit.uni-kl.de# Matthias Jung 4511186Serfan.azarkhish@unibo.it# Erfan Azarkhish 469243SN/A 479243SN/Afrom m5.params import * 4812706Swendy.elsasser@arm.comfrom m5.proxy import * 4913665Sandreas.sandberg@arm.comfrom m5.objects.AbstractMemory import * 5013665Sandreas.sandberg@arm.comfrom m5.objects.QoSMemCtrl import * 519243SN/A 529243SN/A# Enum for memory scheduling algorithms, currently First-Come 539243SN/A# First-Served and a First-Row Hit then First-Come First-Served 549243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 559243SN/A 5610136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5710136SN/A# channel, rank, bank, row and column, respectively, and going from 5810136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5910136SN/A# suitable for an open-page policy, optimising for sequential accesses 6010136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 6110136SN/A# maximises parallelism. 6210136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 639243SN/A 6410144SN/A# Enum for the page policy, either open, open_adaptive, close, or 6510144SN/A# close_adaptive. 6610144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6710144SN/A 'close_adaptive'] 689243SN/A 6910146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 709243SN/A# that aims to model the most important system-level performance 719243SN/A# effects of a DRAM without getting into too much detail of the DRAM 729243SN/A# itself. 7312969SMatteo.Andreozzi@arm.comclass DRAMCtrl(QoSMemCtrl): 7410146Sandreas.hansson@arm.com type = 'DRAMCtrl' 7510146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 769243SN/A 779243SN/A # single-ported on the system interface side, instantiate with a 789243SN/A # bus in front of the controller for multiple ports 799243SN/A port = SlavePort("Slave port") 809243SN/A 8110536Sandreas.hansson@arm.com # the basic configuration of the controller architecture, note 8210536Sandreas.hansson@arm.com # that each entry corresponds to a burst for the specific DRAM 8310536Sandreas.hansson@arm.com # configuration (e.g. x32 with burst length 8 is 32 bytes) and not 8410536Sandreas.hansson@arm.com # the cacheline size or request/packet size 8510145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 869972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 879243SN/A 8810140SN/A # threshold in percent for when to forcefully trigger writes and 8910140SN/A # start emptying the write buffer 9010140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 919972SN/A 9210140SN/A # threshold in percentage for when to start writes if the read 9310140SN/A # queue is empty 9410140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 9510140SN/A 9610140SN/A # minimum write bursts to schedule before switching back to reads 9710140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 9810140SN/A "switching to reads") 999243SN/A 1009243SN/A # scheduler, address map and page policy 1019489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 10210675Sandreas.hansson@arm.com addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy") 10310145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 1049243SN/A 10510141SN/A # enforce a limit on the number of accesses per row 10610141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 10710141SN/A "closing"); 10810141SN/A 10910489SOmar.Naji@arm.com # size of DRAM Chip in Bytes 11010489SOmar.Naji@arm.com device_size = Param.MemorySize("Size of DRAM chip") 11110489SOmar.Naji@arm.com 1129726SN/A # pipeline latency of the controller and PHY, split into a 1139726SN/A # frontend part and a backend part, with reads and writes serviced 1149726SN/A # by the queues only seeing the frontend contribution, and reads 1159726SN/A # serviced by the memory seeing the sum of the two 1169726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1179726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1189726SN/A 1199489SN/A # the physical organisation of the DRAM 1209831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1219831SN/A "device/chip") 1229831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1239831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1249831SN/A "device/chip") 1259831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1269489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 12710394Swendy.elsasser@arm.com 12810394Swendy.elsasser@arm.com # default to 0 bank groups per rank, indicating bank group architecture 12910394Swendy.elsasser@arm.com # is not used 13010394Swendy.elsasser@arm.com # update per memory class when bank group architecture is supported 13110394Swendy.elsasser@arm.com bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1329489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1339566SN/A # only used for the address mapping as the controller by 1349566SN/A # construction is a single channel and multiple controllers have 1359566SN/A # to be instantiated for a multi-channel configuration 1369566SN/A channels = Param.Unsigned(1, "Number of channels") 1379489SN/A 13814038Smatthew.poremba@amd.com # Enable DRAM powerdown states if True. This is False by default due to 13914038Smatthew.poremba@amd.com # performance being lower when enabled 14014038Smatthew.poremba@amd.com enable_dram_powerdown = Param.Bool(False, "Enable powerdown states") 14114038Smatthew.poremba@amd.com 14210430SOmar.Naji@arm.com # For power modelling we need to know if the DRAM has a DLL or not 14310430SOmar.Naji@arm.com dll = Param.Bool(True, "DRAM has DLL or not") 14410430SOmar.Naji@arm.com 14510430SOmar.Naji@arm.com # DRAMPower provides in addition to the core power, the possibility to 14610430SOmar.Naji@arm.com # include RD/WR termination and IO power. This calculation assumes some 14710430SOmar.Naji@arm.com # default values. The integration of DRAMPower with gem5 does not include 14810430SOmar.Naji@arm.com # IO and RD/WR termination power by default. This might be added as an 14910430SOmar.Naji@arm.com # additional feature in the future. 15010430SOmar.Naji@arm.com 1519243SN/A # timing behaviour and constraints - all in nanoseconds 1529243SN/A 15310216Sandreas.hansson@arm.com # the base clock period of the DRAM 15410216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 15510216Sandreas.hansson@arm.com 1569243SN/A # the amount of time in nanoseconds from issuing an activate command 1579243SN/A # to the data being available in the row buffer for a read/write 1589489SN/A tRCD = Param.Latency("RAS to CAS delay") 1599243SN/A 1609243SN/A # the time from issuing a read/write command to seeing the actual data 1619489SN/A tCL = Param.Latency("CAS latency") 1629243SN/A 1639243SN/A # minimum time between a precharge and subsequent activate 1649489SN/A tRP = Param.Latency("Row precharge time") 1659243SN/A 1669963SN/A # minimum time between an activate and a precharge to the same row 1679963SN/A tRAS = Param.Latency("ACT to PRE delay") 1689963SN/A 16910210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 17010210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 17110210Sandreas.hansson@arm.com 17210212Sandreas.hansson@arm.com # minimum time between a read and precharge command 17310212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 17410212Sandreas.hansson@arm.com 1759243SN/A # time to complete a burst transfer, typically the burst length 1769243SN/A # divided by two due to the DDR bus, but by making it a parameter 1779243SN/A # it is easier to also evaluate SDR memories like WideIO. 1789831SN/A # This parameter has to account for burst length. 1799831SN/A # Read/Write requests with data size larger than one full burst are broken 18010146Sandreas.hansson@arm.com # down into multiple requests in the controller 18110394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 18210394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 18310394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 1849489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1859243SN/A 18610394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 18710394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 18810394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 18910394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 19010394Swendy.elsasser@arm.com tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 19110394Swendy.elsasser@arm.com 19212706Swendy.elsasser@arm.com # Write-to-Write delay for bursts to the same bank group 19312706Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 19412706Swendy.elsasser@arm.com # This will be used to enable different same bank group delays 19512706Swendy.elsasser@arm.com # for writes versus reads 19612706Swendy.elsasser@arm.com tCCD_L_WR = Param.Latency(Self.tCCD_L, 19712706Swendy.elsasser@arm.com "Same bank group Write to Write delay") 19812706Swendy.elsasser@arm.com 1999243SN/A # time taken to complete one refresh cycle (N rows in all banks) 2009489SN/A tRFC = Param.Latency("Refresh cycle time") 2019243SN/A 2029243SN/A # refresh command interval, how often a "ref" command needs 2039243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 2049489SN/A tREFI = Param.Latency("Refresh command interval") 2059243SN/A 20610393Swendy.elsasser@arm.com # write-to-read, same rank turnaround penalty 20710393Swendy.elsasser@arm.com tWTR = Param.Latency("Write to read, same rank switching time") 2089243SN/A 20910393Swendy.elsasser@arm.com # read-to-write, same rank turnaround penalty 21010393Swendy.elsasser@arm.com tRTW = Param.Latency("Read to write, same rank switching time") 21110393Swendy.elsasser@arm.com 21210393Swendy.elsasser@arm.com # rank-to-rank bus delay penalty 21310393Swendy.elsasser@arm.com # this does not correlate to a memory timing parameter and encompasses: 21410393Swendy.elsasser@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 21510393Swendy.elsasser@arm.com # different rank bus delay 21610393Swendy.elsasser@arm.com tCS = Param.Latency("Rank to rank switching time") 21710206Sandreas.hansson@arm.com 2189971SN/A # minimum row activate to row activate delay time 2199971SN/A tRRD = Param.Latency("ACT to ACT delay") 2209971SN/A 22110394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 22210394Swendy.elsasser@arm.com tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 22310394Swendy.elsasser@arm.com 2249488SN/A # time window in which a maximum number of activates are allowed 2259488SN/A # to take place, set to 0 to disable 2269489SN/A tXAW = Param.Latency("X activation window") 2279489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 2289488SN/A 22910430SOmar.Naji@arm.com # time to exit power-down mode 23010430SOmar.Naji@arm.com # Exit power-down to next valid command delay 23110430SOmar.Naji@arm.com tXP = Param.Latency("0ns", "Power-up Delay") 23210430SOmar.Naji@arm.com 23310430SOmar.Naji@arm.com # Exit Powerdown to commands requiring a locked DLL 23410430SOmar.Naji@arm.com tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL") 23510430SOmar.Naji@arm.com 23610430SOmar.Naji@arm.com # time to exit self-refresh mode 23710430SOmar.Naji@arm.com tXS = Param.Latency("0ns", "Self-refresh exit latency") 23810430SOmar.Naji@arm.com 23910430SOmar.Naji@arm.com # time to exit self-refresh mode with locked DLL 24010430SOmar.Naji@arm.com tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL") 24110430SOmar.Naji@arm.com 2429488SN/A # Currently rolled into other params 2439243SN/A ###################################################################### 2449243SN/A 2459963SN/A # tRC - assumed to be tRAS + tRP 2469243SN/A 24710430SOmar.Naji@arm.com # Power Behaviour and Constraints 24810430SOmar.Naji@arm.com # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are 24910430SOmar.Naji@arm.com # defined as VDD and VDD2. Each current is defined for each voltage domain 25010430SOmar.Naji@arm.com # separately. For example, current IDD0 is active-precharge current for 25110430SOmar.Naji@arm.com # voltage domain VDD and current IDD02 is active-precharge current for 25210430SOmar.Naji@arm.com # voltage domain VDD2. 25310430SOmar.Naji@arm.com # By default all currents are set to 0mA. Users who are only interested in 25410430SOmar.Naji@arm.com # the performance of DRAMs can leave them at 0. 25510430SOmar.Naji@arm.com 25610430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current 25710430SOmar.Naji@arm.com IDD0 = Param.Current("0mA", "Active precharge current") 25810430SOmar.Naji@arm.com 25910430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current multiple voltage Range 26010430SOmar.Naji@arm.com IDD02 = Param.Current("0mA", "Active precharge current VDD2") 26110430SOmar.Naji@arm.com 26210430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit 26310430SOmar.Naji@arm.com IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow") 26410430SOmar.Naji@arm.com 26510430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit multiple voltage Range 26610430SOmar.Naji@arm.com IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2") 26710430SOmar.Naji@arm.com 26810430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit 26910430SOmar.Naji@arm.com IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast") 27010430SOmar.Naji@arm.com 27110430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit multiple voltage Range 27210430SOmar.Naji@arm.com IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2") 27310430SOmar.Naji@arm.com 27410430SOmar.Naji@arm.com # Precharge Standby current 27510430SOmar.Naji@arm.com IDD2N = Param.Current("0mA", "Precharge Standby current") 27610430SOmar.Naji@arm.com 27710430SOmar.Naji@arm.com # Precharge Standby current multiple voltage range 27810430SOmar.Naji@arm.com IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2") 27910430SOmar.Naji@arm.com 28010430SOmar.Naji@arm.com # Active Power-down current: slow exit 28110430SOmar.Naji@arm.com IDD3P0 = Param.Current("0mA", "Active Powerdown slow") 28210430SOmar.Naji@arm.com 28310430SOmar.Naji@arm.com # Active Power-down current: slow exit multiple voltage range 28410430SOmar.Naji@arm.com IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2") 28510430SOmar.Naji@arm.com 28610430SOmar.Naji@arm.com # Active Power-down current : fast exit 28710430SOmar.Naji@arm.com IDD3P1 = Param.Current("0mA", "Active Powerdown fast") 28810430SOmar.Naji@arm.com 28910430SOmar.Naji@arm.com # Active Power-down current : fast exit multiple voltage range 29010430SOmar.Naji@arm.com IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2") 29110430SOmar.Naji@arm.com 29210430SOmar.Naji@arm.com # Active Standby current 29310430SOmar.Naji@arm.com IDD3N = Param.Current("0mA", "Active Standby current") 29410430SOmar.Naji@arm.com 29510430SOmar.Naji@arm.com # Active Standby current multiple voltage range 29610430SOmar.Naji@arm.com IDD3N2 = Param.Current("0mA", "Active Standby current VDD2") 29710430SOmar.Naji@arm.com 29810430SOmar.Naji@arm.com # Burst Read Operating Current 29910430SOmar.Naji@arm.com IDD4R = Param.Current("0mA", "READ current") 30010430SOmar.Naji@arm.com 30110430SOmar.Naji@arm.com # Burst Read Operating Current multiple voltage range 30210430SOmar.Naji@arm.com IDD4R2 = Param.Current("0mA", "READ current VDD2") 30310430SOmar.Naji@arm.com 30410430SOmar.Naji@arm.com # Burst Write Operating Current 30510430SOmar.Naji@arm.com IDD4W = Param.Current("0mA", "WRITE current") 30610430SOmar.Naji@arm.com 30710430SOmar.Naji@arm.com # Burst Write Operating Current multiple voltage range 30810430SOmar.Naji@arm.com IDD4W2 = Param.Current("0mA", "WRITE current VDD2") 30910430SOmar.Naji@arm.com 31010430SOmar.Naji@arm.com # Refresh Current 31110430SOmar.Naji@arm.com IDD5 = Param.Current("0mA", "Refresh current") 31210430SOmar.Naji@arm.com 31310430SOmar.Naji@arm.com # Refresh Current multiple voltage range 31410430SOmar.Naji@arm.com IDD52 = Param.Current("0mA", "Refresh current VDD2") 31510430SOmar.Naji@arm.com 31610430SOmar.Naji@arm.com # Self-Refresh Current 31710430SOmar.Naji@arm.com IDD6 = Param.Current("0mA", "Self-refresh Current") 31810430SOmar.Naji@arm.com 31910430SOmar.Naji@arm.com # Self-Refresh Current multiple voltage range 32010430SOmar.Naji@arm.com IDD62 = Param.Current("0mA", "Self-refresh Current VDD2") 32110430SOmar.Naji@arm.com 32210430SOmar.Naji@arm.com # Main voltage range of the DRAM 32310430SOmar.Naji@arm.com VDD = Param.Voltage("0V", "Main Voltage Range") 32410430SOmar.Naji@arm.com 32510430SOmar.Naji@arm.com # Second voltage range defined by some DRAMs 32610430SOmar.Naji@arm.com VDD2 = Param.Voltage("0V", "2nd Voltage Range") 32710430SOmar.Naji@arm.com 32810217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 32910217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 33010430SOmar.Naji@arm.com# an 8x8 configuration. 33111837Swendy.elsasser@arm.comclass DDR3_1600_8x8(DRAMCtrl): 33210489SOmar.Naji@arm.com # size of device in bytes 33310489SOmar.Naji@arm.com device_size = '512MB' 33410489SOmar.Naji@arm.com 3359831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 3369831SN/A device_bus_width = 8 3379831SN/A 3389831SN/A # DDR3 is a BL8 device 3399831SN/A burst_length = 8 3409831SN/A 34110217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 3429831SN/A device_rowbuffer_size = '1kB' 3439831SN/A 3449831SN/A # 8x8 configuration, so 8 devices 3459831SN/A devices_per_rank = 8 3469489SN/A 3479489SN/A # Use two ranks 3489489SN/A ranks_per_channel = 2 3499489SN/A 3509489SN/A # DDR3 has 8 banks in all configurations 3519489SN/A banks_per_rank = 8 3529489SN/A 35310216Sandreas.hansson@arm.com # 800 MHz 35410216Sandreas.hansson@arm.com tCK = '1.25ns' 35510216Sandreas.hansson@arm.com 35610217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 35710217Sandreas.hansson@arm.com tBURST = '5ns' 35810217Sandreas.hansson@arm.com 35910217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 3609489SN/A tRCD = '13.75ns' 3619489SN/A tCL = '13.75ns' 3629489SN/A tRP = '13.75ns' 3639970SN/A tRAS = '35ns' 36410217Sandreas.hansson@arm.com tRRD = '6ns' 36510217Sandreas.hansson@arm.com tXAW = '30ns' 36610217Sandreas.hansson@arm.com activation_limit = 4 36710217Sandreas.hansson@arm.com tRFC = '260ns' 36810217Sandreas.hansson@arm.com 36910210Sandreas.hansson@arm.com tWR = '15ns' 37010217Sandreas.hansson@arm.com 37110217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 37210217Sandreas.hansson@arm.com tWTR = '7.5ns' 37310217Sandreas.hansson@arm.com 37410217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 37510212Sandreas.hansson@arm.com tRTP = '7.5ns' 3769489SN/A 37710393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 37810206Sandreas.hansson@arm.com tRTW = '2.5ns' 37910206Sandreas.hansson@arm.com 38010393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 38110393Swendy.elsasser@arm.com tCS = '2.5ns' 38210393Swendy.elsasser@arm.com 38310217Sandreas.hansson@arm.com # <=85C, half for >85C 38410217Sandreas.hansson@arm.com tREFI = '7.8us' 3859971SN/A 38611673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 38711673SOmar.Naji@arm.com tXP = '6ns' 38811673SOmar.Naji@arm.com 38911673SOmar.Naji@arm.com # self refresh exit time 39011673SOmar.Naji@arm.com tXS = '270ns' 39111673SOmar.Naji@arm.com 39211674SOmar.Naji@arm.com # Current values from datasheet Die Rev E,J 39311674SOmar.Naji@arm.com IDD0 = '55mA' 39411674SOmar.Naji@arm.com IDD2N = '32mA' 39511674SOmar.Naji@arm.com IDD3N = '38mA' 39611674SOmar.Naji@arm.com IDD4W = '125mA' 39711674SOmar.Naji@arm.com IDD4R = '157mA' 39811674SOmar.Naji@arm.com IDD5 = '235mA' 39911679SOmar.Naji@arm.com IDD3P1 = '38mA' 40011679SOmar.Naji@arm.com IDD2P1 = '32mA' 40111679SOmar.Naji@arm.com IDD6 = '20mA' 40210430SOmar.Naji@arm.com VDD = '1.5V' 40310430SOmar.Naji@arm.com 40410864Sjungma@eit.uni-kl.de# A single HMC-2500 x32 model based on: 40510864Sjungma@eit.uni-kl.de# [1] DRAMSpec: a high-level DRAM bank modelling tool 40610864Sjungma@eit.uni-kl.de# developed at the University of Kaiserslautern. This high level tool 40710864Sjungma@eit.uni-kl.de# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to 40810864Sjungma@eit.uni-kl.de# estimate the DRAM bank latency and power numbers. 40911186Serfan.azarkhish@unibo.it# [2] High performance AXI-4.0 based interconnect for extensible smart memory 41011186Serfan.azarkhish@unibo.it# cubes (E. Azarkhish et. al) 41110864Sjungma@eit.uni-kl.de# Assumed for the HMC model is a 30 nm technology node. 41210864Sjungma@eit.uni-kl.de# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4 41310864Sjungma@eit.uni-kl.de# layers). 41410864Sjungma@eit.uni-kl.de# Each layer has 16 vaults and each vault consists of 2 banks per layer. 41510864Sjungma@eit.uni-kl.de# In order to be able to use the same controller used for 2D DRAM generations 41610864Sjungma@eit.uni-kl.de# for HMC, the following analogy is done: 41710864Sjungma@eit.uni-kl.de# Channel (DDR) => Vault (HMC) 41810864Sjungma@eit.uni-kl.de# device_size (DDR) => size of a single layer in a vault 41910864Sjungma@eit.uni-kl.de# ranks per channel (DDR) => number of layers 42010864Sjungma@eit.uni-kl.de# banks per rank (DDR) => banks per layer 42110864Sjungma@eit.uni-kl.de# devices per rank (DDR) => devices per layer ( 1 for HMC). 42210864Sjungma@eit.uni-kl.de# The parameters for which no input is available are inherited from the DDR3 42310864Sjungma@eit.uni-kl.de# configuration. 42411186Serfan.azarkhish@unibo.it# This configuration includes the latencies from the DRAM to the logic layer 42511186Serfan.azarkhish@unibo.it# of the HMC 42611837Swendy.elsasser@arm.comclass HMC_2500_1x32(DDR3_1600_8x8): 42710864Sjungma@eit.uni-kl.de # size of device 42810864Sjungma@eit.uni-kl.de # two banks per device with each bank 4MB [2] 42910864Sjungma@eit.uni-kl.de device_size = '8MB' 43010864Sjungma@eit.uni-kl.de 43110864Sjungma@eit.uni-kl.de # 1x32 configuration, 1 device with 32 TSVs [2] 43210864Sjungma@eit.uni-kl.de device_bus_width = 32 43310864Sjungma@eit.uni-kl.de 43410864Sjungma@eit.uni-kl.de # HMC is a BL8 device [2] 43510864Sjungma@eit.uni-kl.de burst_length = 8 43610864Sjungma@eit.uni-kl.de 43710864Sjungma@eit.uni-kl.de # Each device has a page (row buffer) size of 256 bytes [2] 43810864Sjungma@eit.uni-kl.de device_rowbuffer_size = '256B' 43910864Sjungma@eit.uni-kl.de 44010864Sjungma@eit.uni-kl.de # 1x32 configuration, so 1 device [2] 44110864Sjungma@eit.uni-kl.de devices_per_rank = 1 44210864Sjungma@eit.uni-kl.de 44310864Sjungma@eit.uni-kl.de # 4 layers so 4 ranks [2] 44410864Sjungma@eit.uni-kl.de ranks_per_channel = 4 44510864Sjungma@eit.uni-kl.de 44610864Sjungma@eit.uni-kl.de # HMC has 2 banks per layer [2] 44710864Sjungma@eit.uni-kl.de # Each layer represents a rank. With 4 layers and 8 banks in total, each 44810864Sjungma@eit.uni-kl.de # layer has 2 banks; thus 2 banks per rank. 44910864Sjungma@eit.uni-kl.de banks_per_rank = 2 45010864Sjungma@eit.uni-kl.de 45110864Sjungma@eit.uni-kl.de # 1250 MHz [2] 45210864Sjungma@eit.uni-kl.de tCK = '0.8ns' 45310864Sjungma@eit.uni-kl.de 45410864Sjungma@eit.uni-kl.de # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz 45510864Sjungma@eit.uni-kl.de tBURST = '3.2ns' 45610864Sjungma@eit.uni-kl.de 45710864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 45810864Sjungma@eit.uni-kl.de tRCD = '10.2ns' 45910864Sjungma@eit.uni-kl.de tCL = '9.9ns' 46010864Sjungma@eit.uni-kl.de tRP = '7.7ns' 46110864Sjungma@eit.uni-kl.de tRAS = '21.6ns' 46210864Sjungma@eit.uni-kl.de 46310864Sjungma@eit.uni-kl.de # tRRD depends on the power supply network for each vendor. 46410864Sjungma@eit.uni-kl.de # We assume a tRRD of a double bank approach to be equal to 4 clock 46510864Sjungma@eit.uni-kl.de # cycles (Assumption) 46610864Sjungma@eit.uni-kl.de tRRD = '3.2ns' 46710864Sjungma@eit.uni-kl.de 46811186Serfan.azarkhish@unibo.it # activation limit is set to 0 since there are only 2 banks per vault 46911186Serfan.azarkhish@unibo.it # layer. 47010864Sjungma@eit.uni-kl.de activation_limit = 0 47110864Sjungma@eit.uni-kl.de 47210864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 47310864Sjungma@eit.uni-kl.de tRFC = '59ns' 47410864Sjungma@eit.uni-kl.de tWR = '8ns' 47510864Sjungma@eit.uni-kl.de tRTP = '4.9ns' 47610864Sjungma@eit.uni-kl.de 47711186Serfan.azarkhish@unibo.it # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 47811186Serfan.azarkhish@unibo.it # 0.8 ns (Assumption) 47910864Sjungma@eit.uni-kl.de tCS = '0.8ns' 48010864Sjungma@eit.uni-kl.de 48110864Sjungma@eit.uni-kl.de # Value using DRAMSpec HMC model [1] 48210864Sjungma@eit.uni-kl.de tREFI = '3.9us' 48310864Sjungma@eit.uni-kl.de 48411186Serfan.azarkhish@unibo.it # The default page policy in the vault controllers is simple closed page 48511186Serfan.azarkhish@unibo.it # [2] nevertheless 'close' policy opens and closes the row multiple times 48611186Serfan.azarkhish@unibo.it # for bursts largers than 32Bytes. For this reason we use 'close_adaptive' 48711186Serfan.azarkhish@unibo.it page_policy = 'close_adaptive' 48811186Serfan.azarkhish@unibo.it 48911186Serfan.azarkhish@unibo.it # RoCoRaBaCh resembles the default address mapping in HMC 49010864Sjungma@eit.uni-kl.de addr_mapping = 'RoCoRaBaCh' 49110864Sjungma@eit.uni-kl.de min_writes_per_switch = 8 49210864Sjungma@eit.uni-kl.de 49311186Serfan.azarkhish@unibo.it # These parameters do not directly correlate with buffer_size in real 49411186Serfan.azarkhish@unibo.it # hardware. Nevertheless, their value has been tuned to achieve a 49511186Serfan.azarkhish@unibo.it # bandwidth similar to the cycle-accurate model in [2] 49611186Serfan.azarkhish@unibo.it write_buffer_size = 32 49711186Serfan.azarkhish@unibo.it read_buffer_size = 32 49811186Serfan.azarkhish@unibo.it 49911186Serfan.azarkhish@unibo.it # The static latency of the vault controllers is estimated to be smaller 50011186Serfan.azarkhish@unibo.it # than a full DRAM channel controller 50111186Serfan.azarkhish@unibo.it static_backend_latency='4ns' 50211186Serfan.azarkhish@unibo.it static_frontend_latency='4ns' 50311186Serfan.azarkhish@unibo.it 50410217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 50510217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 50610217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 50710217Sandreas.hansson@arm.com# consistent across the two configurations. 50811837Swendy.elsasser@arm.comclass DDR3_2133_8x8(DDR3_1600_8x8): 50910217Sandreas.hansson@arm.com # 1066 MHz 51010217Sandreas.hansson@arm.com tCK = '0.938ns' 51110217Sandreas.hansson@arm.com 51210217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 51310217Sandreas.hansson@arm.com tBURST = '3.752ns' 51410217Sandreas.hansson@arm.com 51510217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 51610217Sandreas.hansson@arm.com tRCD = '13.09ns' 51710217Sandreas.hansson@arm.com tCL = '13.09ns' 51810217Sandreas.hansson@arm.com tRP = '13.09ns' 51910217Sandreas.hansson@arm.com tRAS = '33ns' 52010217Sandreas.hansson@arm.com tRRD = '5ns' 52110217Sandreas.hansson@arm.com tXAW = '25ns' 52210217Sandreas.hansson@arm.com 52310430SOmar.Naji@arm.com # Current values from datasheet 52410430SOmar.Naji@arm.com IDD0 = '70mA' 52510430SOmar.Naji@arm.com IDD2N = '37mA' 52610430SOmar.Naji@arm.com IDD3N = '44mA' 52710430SOmar.Naji@arm.com IDD4W = '157mA' 52810430SOmar.Naji@arm.com IDD4R = '191mA' 52910430SOmar.Naji@arm.com IDD5 = '250mA' 53011679SOmar.Naji@arm.com IDD3P1 = '44mA' 53111679SOmar.Naji@arm.com IDD2P1 = '43mA' 53211679SOmar.Naji@arm.com IDD6 ='20mA' 53310430SOmar.Naji@arm.com VDD = '1.5V' 53410430SOmar.Naji@arm.com 53510217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 53611837Swendy.elsasser@arm.com# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4) 53711837Swendy.elsasser@arm.com# in an 16x4 configuration. 53811837Swendy.elsasser@arm.com# Total channel capacity is 32GB 53911837Swendy.elsasser@arm.com# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel 54011837Swendy.elsasser@arm.comclass DDR4_2400_16x4(DRAMCtrl): 54110489SOmar.Naji@arm.com # size of device 54211837Swendy.elsasser@arm.com device_size = '1GB' 54310489SOmar.Naji@arm.com 54411837Swendy.elsasser@arm.com # 16x4 configuration, 16 devices each with a 4-bit interface 54511837Swendy.elsasser@arm.com device_bus_width = 4 54610217Sandreas.hansson@arm.com 54710217Sandreas.hansson@arm.com # DDR4 is a BL8 device 54810217Sandreas.hansson@arm.com burst_length = 8 54910217Sandreas.hansson@arm.com 55011837Swendy.elsasser@arm.com # Each device has a page (row buffer) size of 512 byte (1K columns x4) 55111837Swendy.elsasser@arm.com device_rowbuffer_size = '512B' 55210217Sandreas.hansson@arm.com 55311837Swendy.elsasser@arm.com # 16x4 configuration, so 16 devices 55411837Swendy.elsasser@arm.com devices_per_rank = 16 55510217Sandreas.hansson@arm.com 55610430SOmar.Naji@arm.com # Match our DDR3 configurations which is dual rank 55710430SOmar.Naji@arm.com ranks_per_channel = 2 55810217Sandreas.hansson@arm.com 55910394Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 56011837Swendy.elsasser@arm.com # Set to 4 for x4 case 56111837Swendy.elsasser@arm.com bank_groups_per_rank = 4 56210394Swendy.elsasser@arm.com 56311672SOmar.Naji@arm.com # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 56411672SOmar.Naji@arm.com # configurations). Currently we do not capture the additional 56510217Sandreas.hansson@arm.com # constraints incurred by the bank groups 56611837Swendy.elsasser@arm.com banks_per_rank = 16 56710217Sandreas.hansson@arm.com 56810891Sandreas.hansson@arm.com # override the default buffer sizes and go for something larger to 56910891Sandreas.hansson@arm.com # accommodate the larger bank count 57010891Sandreas.hansson@arm.com write_buffer_size = 128 57110891Sandreas.hansson@arm.com read_buffer_size = 64 57210891Sandreas.hansson@arm.com 57310217Sandreas.hansson@arm.com # 1200 MHz 57410217Sandreas.hansson@arm.com tCK = '0.833ns' 57510217Sandreas.hansson@arm.com 57610217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 57710394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 57810394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 57910394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 58011837Swendy.elsasser@arm.com tBURST = '3.332ns' 58110217Sandreas.hansson@arm.com 58210394Swendy.elsasser@arm.com # @2400 data rate, tCCD_L is 6 CK 58310394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 58410394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 58510394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 58610394Swendy.elsasser@arm.com tCCD_L = '5ns'; 58710394Swendy.elsasser@arm.com 58811837Swendy.elsasser@arm.com # DDR4-2400 17-17-17 58911837Swendy.elsasser@arm.com tRCD = '14.16ns' 59011837Swendy.elsasser@arm.com tCL = '14.16ns' 59111837Swendy.elsasser@arm.com tRP = '14.16ns' 59211837Swendy.elsasser@arm.com tRAS = '32ns' 59310217Sandreas.hansson@arm.com 59411837Swendy.elsasser@arm.com # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns) 59511837Swendy.elsasser@arm.com tRRD = '3.332ns' 59610394Swendy.elsasser@arm.com 59711837Swendy.elsasser@arm.com # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns) 59811837Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 59910394Swendy.elsasser@arm.com 60011837Swendy.elsasser@arm.com # tFAW for 512B page is MAX(16 CK, 13ns) 60111837Swendy.elsasser@arm.com tXAW = '13.328ns' 6029489SN/A activation_limit = 4 60311837Swendy.elsasser@arm.com # tRFC is 350ns 60411837Swendy.elsasser@arm.com tRFC = '350ns' 6059489SN/A 60610217Sandreas.hansson@arm.com tWR = '15ns' 60710217Sandreas.hansson@arm.com 60810217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 60910217Sandreas.hansson@arm.com tWTR = '5ns' 61010217Sandreas.hansson@arm.com 61110217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 61210217Sandreas.hansson@arm.com tRTP = '7.5ns' 61310217Sandreas.hansson@arm.com 61410393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 61510217Sandreas.hansson@arm.com tRTW = '1.666ns' 61610217Sandreas.hansson@arm.com 61710393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 61810393Swendy.elsasser@arm.com tCS = '1.666ns' 61910393Swendy.elsasser@arm.com 62010217Sandreas.hansson@arm.com # <=85C, half for >85C 62110217Sandreas.hansson@arm.com tREFI = '7.8us' 6229489SN/A 62311673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 62411673SOmar.Naji@arm.com tXP = '6ns' 62511673SOmar.Naji@arm.com 62611673SOmar.Naji@arm.com # self refresh exit time 62711837Swendy.elsasser@arm.com # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is: 62811837Swendy.elsasser@arm.com # tRFC + 10ns = 340ns 62911837Swendy.elsasser@arm.com tXS = '340ns' 63011673SOmar.Naji@arm.com 63110430SOmar.Naji@arm.com # Current values from datasheet 63211837Swendy.elsasser@arm.com IDD0 = '43mA' 63311837Swendy.elsasser@arm.com IDD02 = '3mA' 63411837Swendy.elsasser@arm.com IDD2N = '34mA' 63511837Swendy.elsasser@arm.com IDD3N = '38mA' 63610430SOmar.Naji@arm.com IDD3N2 = '3mA' 63711837Swendy.elsasser@arm.com IDD4W = '103mA' 63811837Swendy.elsasser@arm.com IDD4R = '110mA' 63911837Swendy.elsasser@arm.com IDD5 = '250mA' 64011837Swendy.elsasser@arm.com IDD3P1 = '32mA' 64111837Swendy.elsasser@arm.com IDD2P1 = '25mA' 64211837Swendy.elsasser@arm.com IDD6 = '30mA' 64310430SOmar.Naji@arm.com VDD = '1.2V' 64410430SOmar.Naji@arm.com VDD2 = '2.5V' 64510430SOmar.Naji@arm.com 64611837Swendy.elsasser@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 64711837Swendy.elsasser@arm.com# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8) 64811837Swendy.elsasser@arm.com# in an 8x8 configuration. 64911837Swendy.elsasser@arm.com# Total channel capacity is 16GB 65011837Swendy.elsasser@arm.com# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel 65111837Swendy.elsasser@arm.comclass DDR4_2400_8x8(DDR4_2400_16x4): 65211837Swendy.elsasser@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 65311837Swendy.elsasser@arm.com device_bus_width = 8 65411837Swendy.elsasser@arm.com 65511837Swendy.elsasser@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 65611837Swendy.elsasser@arm.com device_rowbuffer_size = '1kB' 65711837Swendy.elsasser@arm.com 65812516Swendy.elsasser@arm.com # 8x8 configuration, so 8 devices 65912516Swendy.elsasser@arm.com devices_per_rank = 8 66012516Swendy.elsasser@arm.com 66111837Swendy.elsasser@arm.com # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 66211837Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 66311837Swendy.elsasser@arm.com 66411837Swendy.elsasser@arm.com tXAW = '21ns' 66511837Swendy.elsasser@arm.com 66611837Swendy.elsasser@arm.com # Current values from datasheet 66711837Swendy.elsasser@arm.com IDD0 = '48mA' 66811837Swendy.elsasser@arm.com IDD3N = '43mA' 66911837Swendy.elsasser@arm.com IDD4W = '123mA' 67011837Swendy.elsasser@arm.com IDD4R = '135mA' 67111837Swendy.elsasser@arm.com IDD3P1 = '37mA' 67211837Swendy.elsasser@arm.com 67311837Swendy.elsasser@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 67411837Swendy.elsasser@arm.com# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16) 67511837Swendy.elsasser@arm.com# in an 4x16 configuration. 67611837Swendy.elsasser@arm.com# Total channel capacity is 4GB 67711837Swendy.elsasser@arm.com# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel 67811837Swendy.elsasser@arm.comclass DDR4_2400_4x16(DDR4_2400_16x4): 67911837Swendy.elsasser@arm.com # 4x16 configuration, 4 devices each with an 16-bit interface 68011837Swendy.elsasser@arm.com device_bus_width = 16 68111837Swendy.elsasser@arm.com 68211837Swendy.elsasser@arm.com # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16) 68311837Swendy.elsasser@arm.com device_rowbuffer_size = '2kB' 68411837Swendy.elsasser@arm.com 68511837Swendy.elsasser@arm.com # 4x16 configuration, so 4 devices 68611837Swendy.elsasser@arm.com devices_per_rank = 4 68711837Swendy.elsasser@arm.com 68811837Swendy.elsasser@arm.com # Single rank for x16 68911837Swendy.elsasser@arm.com ranks_per_channel = 1 69011837Swendy.elsasser@arm.com 69111837Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 69211837Swendy.elsasser@arm.com # Set to 2 for x16 case 69311837Swendy.elsasser@arm.com bank_groups_per_rank = 2 69411837Swendy.elsasser@arm.com 69511837Swendy.elsasser@arm.com # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 69611837Swendy.elsasser@arm.com # configurations). Currently we do not capture the additional 69711837Swendy.elsasser@arm.com # constraints incurred by the bank groups 69811837Swendy.elsasser@arm.com banks_per_rank = 8 69911837Swendy.elsasser@arm.com 70011837Swendy.elsasser@arm.com # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns) 70111837Swendy.elsasser@arm.com tRRD = '5.3ns' 70211837Swendy.elsasser@arm.com 70311837Swendy.elsasser@arm.com # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns) 70411837Swendy.elsasser@arm.com tRRD_L = '6.4ns'; 70511837Swendy.elsasser@arm.com 70611837Swendy.elsasser@arm.com tXAW = '30ns' 70711837Swendy.elsasser@arm.com 70811837Swendy.elsasser@arm.com # Current values from datasheet 70911837Swendy.elsasser@arm.com IDD0 = '80mA' 71011837Swendy.elsasser@arm.com IDD02 = '4mA' 71111837Swendy.elsasser@arm.com IDD2N = '34mA' 71211837Swendy.elsasser@arm.com IDD3N = '47mA' 71311837Swendy.elsasser@arm.com IDD4W = '228mA' 71411837Swendy.elsasser@arm.com IDD4R = '243mA' 71511837Swendy.elsasser@arm.com IDD5 = '280mA' 71611837Swendy.elsasser@arm.com IDD3P1 = '41mA' 71711837Swendy.elsasser@arm.com 7189728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 71910430SOmar.Naji@arm.com# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 72010430SOmar.Naji@arm.com# in a 1x32 configuration. 72111837Swendy.elsasser@arm.comclass LPDDR2_S4_1066_1x32(DRAMCtrl): 72210430SOmar.Naji@arm.com # No DLL in LPDDR2 72310430SOmar.Naji@arm.com dll = False 72410430SOmar.Naji@arm.com 72510489SOmar.Naji@arm.com # size of device 72610489SOmar.Naji@arm.com device_size = '512MB' 72710489SOmar.Naji@arm.com 7289831SN/A # 1x32 configuration, 1 device with a 32-bit interface 7299831SN/A device_bus_width = 32 7309831SN/A 7319831SN/A # LPDDR2_S4 is a BL4 and BL8 device 7329831SN/A burst_length = 8 7339831SN/A 7349831SN/A # Each device has a page (row buffer) size of 1KB 7359831SN/A # (this depends on the memory density) 7369831SN/A device_rowbuffer_size = '1kB' 7379831SN/A 7389831SN/A # 1x32 configuration, so 1 device 7399831SN/A devices_per_rank = 1 7409489SN/A 7419708SN/A # Use a single rank 7429708SN/A ranks_per_channel = 1 7439489SN/A 7449489SN/A # LPDDR2-S4 has 8 banks in all configurations 7459489SN/A banks_per_rank = 8 7469489SN/A 74710216Sandreas.hansson@arm.com # 533 MHz 74810216Sandreas.hansson@arm.com tCK = '1.876ns' 74910216Sandreas.hansson@arm.com 7509489SN/A # Fixed at 15 ns 7519489SN/A tRCD = '15ns' 7529489SN/A 7539489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 7549489SN/A tCL = '15ns' 7559489SN/A 7569728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 7579728SN/A tRP = '15ns' 7589489SN/A 7599970SN/A tRAS = '42ns' 76010210Sandreas.hansson@arm.com tWR = '15ns' 7619963SN/A 76210430SOmar.Naji@arm.com tRTP = '7.5ns' 76310212Sandreas.hansson@arm.com 7649831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 7659831SN/A # Note this is a BL8 DDR device. 7669831SN/A # Requests larger than 32 bytes are broken down into multiple requests 76710146Sandreas.hansson@arm.com # in the controller 7689831SN/A tBURST = '7.5ns' 7699489SN/A 7709708SN/A # LPDDR2-S4, 4 Gbit 7719489SN/A tRFC = '130ns' 7729489SN/A tREFI = '3.9us' 7739489SN/A 77411673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 77511673SOmar.Naji@arm.com tXP = '7.5ns' 77611673SOmar.Naji@arm.com 77711673SOmar.Naji@arm.com # self refresh exit time 77811673SOmar.Naji@arm.com tXS = '140ns' 77911673SOmar.Naji@arm.com 7809489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 7819489SN/A tWTR = '7.5ns' 7829489SN/A 78310393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 78410206Sandreas.hansson@arm.com tRTW = '3.75ns' 78510206Sandreas.hansson@arm.com 78610393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 78710393Swendy.elsasser@arm.com tCS = '3.75ns' 78810393Swendy.elsasser@arm.com 7899971SN/A # Activate to activate irrespective of density and speed grade 7909971SN/A tRRD = '10.0ns' 7919971SN/A 7929708SN/A # Irrespective of density, tFAW is 50 ns 7939489SN/A tXAW = '50ns' 7949489SN/A activation_limit = 4 7959664SN/A 79610430SOmar.Naji@arm.com # Current values from datasheet 79710430SOmar.Naji@arm.com IDD0 = '15mA' 79810430SOmar.Naji@arm.com IDD02 = '70mA' 79910430SOmar.Naji@arm.com IDD2N = '2mA' 80010430SOmar.Naji@arm.com IDD2N2 = '30mA' 80110430SOmar.Naji@arm.com IDD3N = '2.5mA' 80210430SOmar.Naji@arm.com IDD3N2 = '30mA' 80310430SOmar.Naji@arm.com IDD4W = '10mA' 80410430SOmar.Naji@arm.com IDD4W2 = '190mA' 80510430SOmar.Naji@arm.com IDD4R = '3mA' 80610430SOmar.Naji@arm.com IDD4R2 = '220mA' 80710430SOmar.Naji@arm.com IDD5 = '40mA' 80810430SOmar.Naji@arm.com IDD52 = '150mA' 80911679SOmar.Naji@arm.com IDD3P1 = '1.2mA' 81011679SOmar.Naji@arm.com IDD3P12 = '8mA' 81111679SOmar.Naji@arm.com IDD2P1 = '0.6mA' 81211679SOmar.Naji@arm.com IDD2P12 = '0.8mA' 81311679SOmar.Naji@arm.com IDD6 = '1mA' 81411679SOmar.Naji@arm.com IDD62 = '3.2mA' 81510430SOmar.Naji@arm.com VDD = '1.8V' 81610430SOmar.Naji@arm.com VDD2 = '1.2V' 81710430SOmar.Naji@arm.com 8189728SN/A# A single WideIO x128 interface (one command and address bus), with 8199728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 82011837Swendy.elsasser@arm.comclass WideIO_200_1x128(DRAMCtrl): 82110430SOmar.Naji@arm.com # No DLL for WideIO 82210430SOmar.Naji@arm.com dll = False 82310430SOmar.Naji@arm.com 82410489SOmar.Naji@arm.com # size of device 82510489SOmar.Naji@arm.com device_size = '1024MB' 82610489SOmar.Naji@arm.com 8279831SN/A # 1x128 configuration, 1 device with a 128-bit interface 8289831SN/A device_bus_width = 128 8299831SN/A 8309831SN/A # This is a BL4 device 8319831SN/A burst_length = 4 8329831SN/A 8339831SN/A # Each device has a page (row buffer) size of 4KB 8349831SN/A # (this depends on the memory density) 8359831SN/A device_rowbuffer_size = '4kB' 8369831SN/A 8379831SN/A # 1x128 configuration, so 1 device 8389831SN/A devices_per_rank = 1 8399664SN/A 8409664SN/A # Use one rank for a one-high die stack 8419664SN/A ranks_per_channel = 1 8429664SN/A 8439664SN/A # WideIO has 4 banks in all configurations 8449664SN/A banks_per_rank = 4 8459664SN/A 84610216Sandreas.hansson@arm.com # 200 MHz 84710216Sandreas.hansson@arm.com tCK = '5ns' 84810216Sandreas.hansson@arm.com 8499664SN/A # WIO-200 8509664SN/A tRCD = '18ns' 8519664SN/A tCL = '18ns' 8529664SN/A tRP = '18ns' 8539970SN/A tRAS = '42ns' 85410210Sandreas.hansson@arm.com tWR = '15ns' 85510212Sandreas.hansson@arm.com # Read to precharge is same as the burst 85610212Sandreas.hansson@arm.com tRTP = '20ns' 8579664SN/A 8589831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 8599831SN/A # Note this is a BL4 SDR device. 8609664SN/A tBURST = '20ns' 8619664SN/A 8629664SN/A # WIO 8 Gb 8639664SN/A tRFC = '210ns' 8649664SN/A 8659664SN/A # WIO 8 Gb, <=85C, half for >85C 8669664SN/A tREFI = '3.9us' 8679664SN/A 8689664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 8699664SN/A tWTR = '15ns' 8709664SN/A 87110393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 87210206Sandreas.hansson@arm.com tRTW = '10ns' 87310206Sandreas.hansson@arm.com 87410393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 87510393Swendy.elsasser@arm.com tCS = '10ns' 87610393Swendy.elsasser@arm.com 8779971SN/A # Activate to activate irrespective of density and speed grade 8789971SN/A tRRD = '10.0ns' 8799971SN/A 8809664SN/A # Two instead of four activation window 8819664SN/A tXAW = '50ns' 8829664SN/A activation_limit = 2 8839709SN/A 88410430SOmar.Naji@arm.com # The WideIO specification does not provide current information 88510430SOmar.Naji@arm.com 8869728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 88710430SOmar.Naji@arm.com# default timings based on a LPDDR3-1600 4 Gbit part (Micron 88810430SOmar.Naji@arm.com# EDF8132A1MC) in a 1x32 configuration. 88911837Swendy.elsasser@arm.comclass LPDDR3_1600_1x32(DRAMCtrl): 89010430SOmar.Naji@arm.com # No DLL for LPDDR3 89110430SOmar.Naji@arm.com dll = False 89210430SOmar.Naji@arm.com 89310489SOmar.Naji@arm.com # size of device 89410489SOmar.Naji@arm.com device_size = '512MB' 89510489SOmar.Naji@arm.com 8969831SN/A # 1x32 configuration, 1 device with a 32-bit interface 8979831SN/A device_bus_width = 32 8989831SN/A 8999831SN/A # LPDDR3 is a BL8 device 9009831SN/A burst_length = 8 9019831SN/A 9029976SN/A # Each device has a page (row buffer) size of 4KB 9039976SN/A device_rowbuffer_size = '4kB' 9049831SN/A 9059831SN/A # 1x32 configuration, so 1 device 9069831SN/A devices_per_rank = 1 9079709SN/A 90810430SOmar.Naji@arm.com # Technically the datasheet is a dual-rank package, but for 90910430SOmar.Naji@arm.com # comparison with the LPDDR2 config we stick to a single rank 9109709SN/A ranks_per_channel = 1 9119709SN/A 9129709SN/A # LPDDR3 has 8 banks in all configurations 9139709SN/A banks_per_rank = 8 9149709SN/A 91510216Sandreas.hansson@arm.com # 800 MHz 91610216Sandreas.hansson@arm.com tCK = '1.25ns' 91710216Sandreas.hansson@arm.com 91810430SOmar.Naji@arm.com tRCD = '18ns' 9199709SN/A 9209709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 9219709SN/A tCL = '15ns' 9229709SN/A 9239970SN/A tRAS = '42ns' 92410210Sandreas.hansson@arm.com tWR = '15ns' 9259963SN/A 92610212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 92710212Sandreas.hansson@arm.com tRTP = '7.5ns' 92810212Sandreas.hansson@arm.com 92910430SOmar.Naji@arm.com # Pre-charge one bank 18 ns (all banks 21 ns) 93010430SOmar.Naji@arm.com tRP = '18ns' 9319709SN/A 9329831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 9339831SN/A # Note this is a BL8 DDR device. 9349831SN/A # Requests larger than 32 bytes are broken down into multiple requests 93510146Sandreas.hansson@arm.com # in the controller 9369831SN/A tBURST = '5ns' 9379709SN/A 9389709SN/A # LPDDR3, 4 Gb 9399709SN/A tRFC = '130ns' 9409709SN/A tREFI = '3.9us' 9419709SN/A 94211673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 94311673SOmar.Naji@arm.com tXP = '7.5ns' 94411673SOmar.Naji@arm.com 94511673SOmar.Naji@arm.com # self refresh exit time 94611673SOmar.Naji@arm.com tXS = '140ns' 94711673SOmar.Naji@arm.com 9489709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 9499709SN/A tWTR = '7.5ns' 9509709SN/A 95110393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 95210206Sandreas.hansson@arm.com tRTW = '2.5ns' 95310206Sandreas.hansson@arm.com 95410393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 95510393Swendy.elsasser@arm.com tCS = '2.5ns' 95610393Swendy.elsasser@arm.com 9579971SN/A # Activate to activate irrespective of density and speed grade 9589971SN/A tRRD = '10.0ns' 9599971SN/A 9609709SN/A # Irrespective of size, tFAW is 50 ns 9619709SN/A tXAW = '50ns' 9629709SN/A activation_limit = 4 96310430SOmar.Naji@arm.com 96410430SOmar.Naji@arm.com # Current values from datasheet 96510430SOmar.Naji@arm.com IDD0 = '8mA' 96610430SOmar.Naji@arm.com IDD02 = '60mA' 96710430SOmar.Naji@arm.com IDD2N = '0.8mA' 96810430SOmar.Naji@arm.com IDD2N2 = '26mA' 96910430SOmar.Naji@arm.com IDD3N = '2mA' 97010430SOmar.Naji@arm.com IDD3N2 = '34mA' 97110430SOmar.Naji@arm.com IDD4W = '2mA' 97210430SOmar.Naji@arm.com IDD4W2 = '190mA' 97310430SOmar.Naji@arm.com IDD4R = '2mA' 97410430SOmar.Naji@arm.com IDD4R2 = '230mA' 97510430SOmar.Naji@arm.com IDD5 = '28mA' 97610430SOmar.Naji@arm.com IDD52 = '150mA' 97711679SOmar.Naji@arm.com IDD3P1 = '1.4mA' 97811679SOmar.Naji@arm.com IDD3P12 = '11mA' 97911679SOmar.Naji@arm.com IDD2P1 = '0.8mA' 98011679SOmar.Naji@arm.com IDD2P12 = '1.8mA' 98111679SOmar.Naji@arm.com IDD6 = '0.5mA' 98211679SOmar.Naji@arm.com IDD62 = '1.8mA' 98310430SOmar.Naji@arm.com VDD = '1.8V' 98410430SOmar.Naji@arm.com VDD2 = '1.2V' 98510561SOmar.Naji@arm.com 98610561SOmar.Naji@arm.com# A single GDDR5 x64 interface, with 98710561SOmar.Naji@arm.com# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix 98810561SOmar.Naji@arm.com# H5GQ1H24AFR) in a 2x32 configuration. 98911837Swendy.elsasser@arm.comclass GDDR5_4000_2x32(DRAMCtrl): 99010561SOmar.Naji@arm.com # size of device 99110561SOmar.Naji@arm.com device_size = '128MB' 99210561SOmar.Naji@arm.com 99310561SOmar.Naji@arm.com # 2x32 configuration, 1 device with a 32-bit interface 99410561SOmar.Naji@arm.com device_bus_width = 32 99510561SOmar.Naji@arm.com 99610561SOmar.Naji@arm.com # GDDR5 is a BL8 device 99710561SOmar.Naji@arm.com burst_length = 8 99810561SOmar.Naji@arm.com 99910561SOmar.Naji@arm.com # Each device has a page (row buffer) size of 2Kbits (256Bytes) 100010561SOmar.Naji@arm.com device_rowbuffer_size = '256B' 100110561SOmar.Naji@arm.com 100210561SOmar.Naji@arm.com # 2x32 configuration, so 2 devices 100310561SOmar.Naji@arm.com devices_per_rank = 2 100410561SOmar.Naji@arm.com 100510561SOmar.Naji@arm.com # assume single rank 100610561SOmar.Naji@arm.com ranks_per_channel = 1 100710561SOmar.Naji@arm.com 100810561SOmar.Naji@arm.com # GDDR5 has 4 bank groups 100910561SOmar.Naji@arm.com bank_groups_per_rank = 4 101010561SOmar.Naji@arm.com 101110561SOmar.Naji@arm.com # GDDR5 has 16 banks with 4 bank groups 101210561SOmar.Naji@arm.com banks_per_rank = 16 101310561SOmar.Naji@arm.com 101410561SOmar.Naji@arm.com # 1000 MHz 101510561SOmar.Naji@arm.com tCK = '1ns' 101610561SOmar.Naji@arm.com 101710561SOmar.Naji@arm.com # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz 101810561SOmar.Naji@arm.com # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz ) 101910561SOmar.Naji@arm.com # 8 beats at 4000 MHz = 2 beats at 1000 MHz 102010561SOmar.Naji@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 102110561SOmar.Naji@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 102210561SOmar.Naji@arm.com # delay for bursts to different bank groups (tCCD_S) 102310561SOmar.Naji@arm.com tBURST = '2ns' 102410561SOmar.Naji@arm.com 102510561SOmar.Naji@arm.com # @1000MHz data rate, tCCD_L is 3 CK 102610561SOmar.Naji@arm.com # CAS-to-CAS delay for bursts to the same bank group 102710561SOmar.Naji@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 102810561SOmar.Naji@arm.com # for CAS-to-CAS delay for bursts to different bank groups 102910561SOmar.Naji@arm.com tCCD_L = '3ns'; 103010561SOmar.Naji@arm.com 103110561SOmar.Naji@arm.com tRCD = '12ns' 103210561SOmar.Naji@arm.com 103310561SOmar.Naji@arm.com # tCL is not directly found in datasheet and assumed equal tRCD 103410561SOmar.Naji@arm.com tCL = '12ns' 103510561SOmar.Naji@arm.com 103610561SOmar.Naji@arm.com tRP = '12ns' 103710561SOmar.Naji@arm.com tRAS = '28ns' 103810561SOmar.Naji@arm.com 103910561SOmar.Naji@arm.com # RRD_S (different bank group) 104010561SOmar.Naji@arm.com # RRD_S is 5.5 ns in datasheet. 104110561SOmar.Naji@arm.com # rounded to the next multiple of tCK 104210561SOmar.Naji@arm.com tRRD = '6ns' 104310561SOmar.Naji@arm.com 104410561SOmar.Naji@arm.com # RRD_L (same bank group) 104510561SOmar.Naji@arm.com # RRD_L is 5.5 ns in datasheet. 104610561SOmar.Naji@arm.com # rounded to the next multiple of tCK 104710561SOmar.Naji@arm.com tRRD_L = '6ns' 104810561SOmar.Naji@arm.com 104910561SOmar.Naji@arm.com tXAW = '23ns' 105010561SOmar.Naji@arm.com 105110561SOmar.Naji@arm.com # tXAW < 4 x tRRD. 105210561SOmar.Naji@arm.com # Therefore, activation limit is set to 0 105310561SOmar.Naji@arm.com activation_limit = 0 105410561SOmar.Naji@arm.com 105510561SOmar.Naji@arm.com tRFC = '65ns' 105610561SOmar.Naji@arm.com tWR = '12ns' 105710561SOmar.Naji@arm.com 105810561SOmar.Naji@arm.com # Here using the average of WTR_S and WTR_L 105910561SOmar.Naji@arm.com tWTR = '5ns' 106010561SOmar.Naji@arm.com 106110561SOmar.Naji@arm.com # Read-to-Precharge 2 CK 106210561SOmar.Naji@arm.com tRTP = '2ns' 106310561SOmar.Naji@arm.com 106410561SOmar.Naji@arm.com # Assume 2 cycles 106510561SOmar.Naji@arm.com tRTW = '2ns' 106610561SOmar.Naji@arm.com 106711120Swendy.elsasser@arm.com# A single HBM x128 interface (one command and address bus), with 106811120Swendy.elsasser@arm.com# default timings based on data publically released 106911120Swendy.elsasser@arm.com# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014), 107011120Swendy.elsasser@arm.com# IDD measurement values, and by extrapolating data from other classes. 107111120Swendy.elsasser@arm.com# Architecture values based on published HBM spec 107211120Swendy.elsasser@arm.com# A 4H stack is defined, 2Gb per die for a total of 1GB of memory. 107311837Swendy.elsasser@arm.comclass HBM_1000_4H_1x128(DRAMCtrl): 107411120Swendy.elsasser@arm.com # HBM gen1 supports up to 8 128-bit physical channels 107511120Swendy.elsasser@arm.com # Configuration defines a single channel, with the capacity 107611120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 8) based on 2Gb dies 107711120Swendy.elsasser@arm.com # To use all 8 channels, set 'channels' parameter to 8 in 107811120Swendy.elsasser@arm.com # system configuration 107911120Swendy.elsasser@arm.com 108011120Swendy.elsasser@arm.com # 128-bit interface legacy mode 108111120Swendy.elsasser@arm.com device_bus_width = 128 108211120Swendy.elsasser@arm.com 108311120Swendy.elsasser@arm.com # HBM supports BL4 and BL2 (legacy mode only) 108411120Swendy.elsasser@arm.com burst_length = 4 108511120Swendy.elsasser@arm.com 108611120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack; 108711120Swendy.elsasser@arm.com # with 8 channels, 128MB per channel 108811120Swendy.elsasser@arm.com device_size = '128MB' 108911120Swendy.elsasser@arm.com 109011120Swendy.elsasser@arm.com device_rowbuffer_size = '2kB' 109111120Swendy.elsasser@arm.com 109211120Swendy.elsasser@arm.com # 1x128 configuration 109311120Swendy.elsasser@arm.com devices_per_rank = 1 109411120Swendy.elsasser@arm.com 109511120Swendy.elsasser@arm.com # HBM does not have a CS pin; set rank to 1 109611120Swendy.elsasser@arm.com ranks_per_channel = 1 109711120Swendy.elsasser@arm.com 109811120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 109911120Swendy.elsasser@arm.com # 2Gb dies have 8 banks 110011120Swendy.elsasser@arm.com banks_per_rank = 8 110111120Swendy.elsasser@arm.com 110211120Swendy.elsasser@arm.com # depending on frequency, bank groups may be required 110311120Swendy.elsasser@arm.com # will always have 4 bank groups when enabled 110411120Swendy.elsasser@arm.com # current specifications do not define the minimum frequency for 110511120Swendy.elsasser@arm.com # bank group architecture 110611120Swendy.elsasser@arm.com # setting bank_groups_per_rank to 0 to disable until range is defined 110711120Swendy.elsasser@arm.com bank_groups_per_rank = 0 110811120Swendy.elsasser@arm.com 110911120Swendy.elsasser@arm.com # 500 MHz for 1Gbps DDR data rate 111011120Swendy.elsasser@arm.com tCK = '2ns' 111111120Swendy.elsasser@arm.com 111211120Swendy.elsasser@arm.com # use values from IDD measurement in JEDEC spec 111311120Swendy.elsasser@arm.com # use tRP value for tRCD and tCL similar to other classes 111411120Swendy.elsasser@arm.com tRP = '15ns' 111511120Swendy.elsasser@arm.com tRCD = '15ns' 111611120Swendy.elsasser@arm.com tCL = '15ns' 111711120Swendy.elsasser@arm.com tRAS = '33ns' 111811120Swendy.elsasser@arm.com 111911120Swendy.elsasser@arm.com # BL2 and BL4 supported, default to BL4 112011120Swendy.elsasser@arm.com # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns 112111120Swendy.elsasser@arm.com tBURST = '4ns' 112211120Swendy.elsasser@arm.com 112311120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 112411120Swendy.elsasser@arm.com tRFC = '160ns' 112511120Swendy.elsasser@arm.com 112611120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 112711120Swendy.elsasser@arm.com tREFI = '3.9us' 112811120Swendy.elsasser@arm.com 112911120Swendy.elsasser@arm.com # extrapolate the following from LPDDR configs, using ns values 113011120Swendy.elsasser@arm.com # to minimize burst length, prefetch differences 113111120Swendy.elsasser@arm.com tWR = '18ns' 113211120Swendy.elsasser@arm.com tRTP = '7.5ns' 113311120Swendy.elsasser@arm.com tWTR = '10ns' 113411120Swendy.elsasser@arm.com 113511120Swendy.elsasser@arm.com # start with 2 cycles turnaround, similar to other memory classes 113611120Swendy.elsasser@arm.com # could be more with variations across the stack 113711120Swendy.elsasser@arm.com tRTW = '4ns' 113811120Swendy.elsasser@arm.com 113911120Swendy.elsasser@arm.com # single rank device, set to 0 114011120Swendy.elsasser@arm.com tCS = '0ns' 114111120Swendy.elsasser@arm.com 114211120Swendy.elsasser@arm.com # from MemCon example, tRRD is 4ns with 2ns tCK 114311120Swendy.elsasser@arm.com tRRD = '4ns' 114411120Swendy.elsasser@arm.com 114511120Swendy.elsasser@arm.com # from MemCon example, tFAW is 30ns with 2ns tCK 114611120Swendy.elsasser@arm.com tXAW = '30ns' 114711120Swendy.elsasser@arm.com activation_limit = 4 114811120Swendy.elsasser@arm.com 114911120Swendy.elsasser@arm.com # 4tCK 115011120Swendy.elsasser@arm.com tXP = '8ns' 115111120Swendy.elsasser@arm.com 115211120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 115311120Swendy.elsasser@arm.com tXS = '168ns' 115411120Swendy.elsasser@arm.com 115511120Swendy.elsasser@arm.com# A single HBM x64 interface (one command and address bus), with 115611120Swendy.elsasser@arm.com# default timings based on HBM gen1 and data publically released 115711120Swendy.elsasser@arm.com# A 4H stack is defined, 8Gb per die for a total of 4GB of memory. 115811120Swendy.elsasser@arm.com# Note: This defines a pseudo-channel with a unique controller 115911120Swendy.elsasser@arm.com# instantiated per pseudo-channel 116011120Swendy.elsasser@arm.com# Stay at same IO rate (1Gbps) to maintain timing relationship with 116111120Swendy.elsasser@arm.com# HBM gen1 class (HBM_1000_4H_x128) where possible 116211837Swendy.elsasser@arm.comclass HBM_1000_4H_1x64(HBM_1000_4H_1x128): 116311120Swendy.elsasser@arm.com # For HBM gen2 with pseudo-channel mode, configure 2X channels. 116411120Swendy.elsasser@arm.com # Configuration defines a single pseudo channel, with the capacity 116511120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 16) based on 8Gb dies 116611120Swendy.elsasser@arm.com # To use all 16 pseudo channels, set 'channels' parameter to 16 in 116711120Swendy.elsasser@arm.com # system configuration 116811120Swendy.elsasser@arm.com 116911120Swendy.elsasser@arm.com # 64-bit pseudo-channle interface 117011120Swendy.elsasser@arm.com device_bus_width = 64 117111120Swendy.elsasser@arm.com 117211120Swendy.elsasser@arm.com # HBM pseudo-channel only supports BL4 117311120Swendy.elsasser@arm.com burst_length = 4 117411120Swendy.elsasser@arm.com 117511120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack; 117611120Swendy.elsasser@arm.com # with 16 channels, 256MB per channel 117711120Swendy.elsasser@arm.com device_size = '256MB' 117811120Swendy.elsasser@arm.com 117911120Swendy.elsasser@arm.com # page size is halved with pseudo-channel; maintaining the same same number 118011120Swendy.elsasser@arm.com # of rows per pseudo-channel with 2X banks across 2 channels 118111120Swendy.elsasser@arm.com device_rowbuffer_size = '1kB' 118211120Swendy.elsasser@arm.com 118311120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 118411120Swendy.elsasser@arm.com # Starting with 4Gb dies, 16 banks are defined 118511120Swendy.elsasser@arm.com banks_per_rank = 16 118611120Swendy.elsasser@arm.com 118711120Swendy.elsasser@arm.com # reset tRFC for larger, 8Gb device 118811120Swendy.elsasser@arm.com # use HBM1 4Gb value as a starting point 118911120Swendy.elsasser@arm.com tRFC = '260ns' 119011120Swendy.elsasser@arm.com 119111120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 119211120Swendy.elsasser@arm.com tXS = '268ns' 119310561SOmar.Naji@arm.com # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns 119410561SOmar.Naji@arm.com tCS = '2ns' 119510561SOmar.Naji@arm.com tREFI = '3.9us' 119611673SOmar.Naji@arm.com 119711673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 119811673SOmar.Naji@arm.com tXP = '10ns' 119911673SOmar.Naji@arm.com 120011673SOmar.Naji@arm.com # self refresh exit time 120111673SOmar.Naji@arm.com tXS = '65ns' 1202