DRAMCtrl.py revision 11837
111674SOmar.Naji@arm.com# Copyright (c) 2012-2016 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 1410864Sjungma@eit.uni-kl.de# Copyright (c) 2015 University of Kaiserslautern 1511186Serfan.azarkhish@unibo.it# Copyright (c) 2015 The University of Bologna 169831SN/A# All rights reserved. 179831SN/A# 189243SN/A# Redistribution and use in source and binary forms, with or without 199243SN/A# modification, are permitted provided that the following conditions are 209243SN/A# met: redistributions of source code must retain the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer; 229243SN/A# redistributions in binary form must reproduce the above copyright 239243SN/A# notice, this list of conditions and the following disclaimer in the 249243SN/A# documentation and/or other materials provided with the distribution; 259243SN/A# neither the name of the copyright holders nor the names of its 269243SN/A# contributors may be used to endorse or promote products derived from 279243SN/A# this software without specific prior written permission. 289243SN/A# 299243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 309243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 319243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 329243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 339243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409243SN/A# 419243SN/A# Authors: Andreas Hansson 429243SN/A# Ani Udipi 4310864Sjungma@eit.uni-kl.de# Omar Naji 4410864Sjungma@eit.uni-kl.de# Matthias Jung 4511186Serfan.azarkhish@unibo.it# Erfan Azarkhish 469243SN/A 479243SN/Afrom m5.params import * 489243SN/Afrom AbstractMemory import * 499243SN/A 509243SN/A# Enum for memory scheduling algorithms, currently First-Come 519243SN/A# First-Served and a First-Row Hit then First-Come First-Served 529243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 539243SN/A 5410136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5510136SN/A# channel, rank, bank, row and column, respectively, and going from 5610136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5710136SN/A# suitable for an open-page policy, optimising for sequential accesses 5810136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5910136SN/A# maximises parallelism. 6010136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 619243SN/A 6210144SN/A# Enum for the page policy, either open, open_adaptive, close, or 6310144SN/A# close_adaptive. 6410144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6510144SN/A 'close_adaptive'] 669243SN/A 6710146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 689243SN/A# that aims to model the most important system-level performance 699243SN/A# effects of a DRAM without getting into too much detail of the DRAM 709243SN/A# itself. 7110146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 7210146Sandreas.hansson@arm.com type = 'DRAMCtrl' 7310146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 749243SN/A 759243SN/A # single-ported on the system interface side, instantiate with a 769243SN/A # bus in front of the controller for multiple ports 779243SN/A port = SlavePort("Slave port") 789243SN/A 7910536Sandreas.hansson@arm.com # the basic configuration of the controller architecture, note 8010536Sandreas.hansson@arm.com # that each entry corresponds to a burst for the specific DRAM 8110536Sandreas.hansson@arm.com # configuration (e.g. x32 with burst length 8 is 32 bytes) and not 8210536Sandreas.hansson@arm.com # the cacheline size or request/packet size 8310145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 849972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 859243SN/A 8610140SN/A # threshold in percent for when to forcefully trigger writes and 8710140SN/A # start emptying the write buffer 8810140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 899972SN/A 9010140SN/A # threshold in percentage for when to start writes if the read 9110140SN/A # queue is empty 9210140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 9310140SN/A 9410140SN/A # minimum write bursts to schedule before switching back to reads 9510140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 9610140SN/A "switching to reads") 979243SN/A 989243SN/A # scheduler, address map and page policy 999489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 10010675Sandreas.hansson@arm.com addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy") 10110145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 1029243SN/A 10310141SN/A # enforce a limit on the number of accesses per row 10410141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 10510141SN/A "closing"); 10610141SN/A 10710489SOmar.Naji@arm.com # size of DRAM Chip in Bytes 10810489SOmar.Naji@arm.com device_size = Param.MemorySize("Size of DRAM chip") 10910489SOmar.Naji@arm.com 1109726SN/A # pipeline latency of the controller and PHY, split into a 1119726SN/A # frontend part and a backend part, with reads and writes serviced 1129726SN/A # by the queues only seeing the frontend contribution, and reads 1139726SN/A # serviced by the memory seeing the sum of the two 1149726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1159726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1169726SN/A 1179489SN/A # the physical organisation of the DRAM 1189831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1199831SN/A "device/chip") 1209831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1219831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1229831SN/A "device/chip") 1239831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1249489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 12510394Swendy.elsasser@arm.com 12610394Swendy.elsasser@arm.com # default to 0 bank groups per rank, indicating bank group architecture 12710394Swendy.elsasser@arm.com # is not used 12810394Swendy.elsasser@arm.com # update per memory class when bank group architecture is supported 12910394Swendy.elsasser@arm.com bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1309489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1319566SN/A # only used for the address mapping as the controller by 1329566SN/A # construction is a single channel and multiple controllers have 1339566SN/A # to be instantiated for a multi-channel configuration 1349566SN/A channels = Param.Unsigned(1, "Number of channels") 1359489SN/A 13610430SOmar.Naji@arm.com # For power modelling we need to know if the DRAM has a DLL or not 13710430SOmar.Naji@arm.com dll = Param.Bool(True, "DRAM has DLL or not") 13810430SOmar.Naji@arm.com 13910430SOmar.Naji@arm.com # DRAMPower provides in addition to the core power, the possibility to 14010430SOmar.Naji@arm.com # include RD/WR termination and IO power. This calculation assumes some 14110430SOmar.Naji@arm.com # default values. The integration of DRAMPower with gem5 does not include 14210430SOmar.Naji@arm.com # IO and RD/WR termination power by default. This might be added as an 14310430SOmar.Naji@arm.com # additional feature in the future. 14410430SOmar.Naji@arm.com 1459243SN/A # timing behaviour and constraints - all in nanoseconds 1469243SN/A 14710216Sandreas.hansson@arm.com # the base clock period of the DRAM 14810216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 14910216Sandreas.hansson@arm.com 1509243SN/A # the amount of time in nanoseconds from issuing an activate command 1519243SN/A # to the data being available in the row buffer for a read/write 1529489SN/A tRCD = Param.Latency("RAS to CAS delay") 1539243SN/A 1549243SN/A # the time from issuing a read/write command to seeing the actual data 1559489SN/A tCL = Param.Latency("CAS latency") 1569243SN/A 1579243SN/A # minimum time between a precharge and subsequent activate 1589489SN/A tRP = Param.Latency("Row precharge time") 1599243SN/A 1609963SN/A # minimum time between an activate and a precharge to the same row 1619963SN/A tRAS = Param.Latency("ACT to PRE delay") 1629963SN/A 16310210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 16410210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 16510210Sandreas.hansson@arm.com 16610212Sandreas.hansson@arm.com # minimum time between a read and precharge command 16710212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 16810212Sandreas.hansson@arm.com 1699243SN/A # time to complete a burst transfer, typically the burst length 1709243SN/A # divided by two due to the DDR bus, but by making it a parameter 1719243SN/A # it is easier to also evaluate SDR memories like WideIO. 1729831SN/A # This parameter has to account for burst length. 1739831SN/A # Read/Write requests with data size larger than one full burst are broken 17410146Sandreas.hansson@arm.com # down into multiple requests in the controller 17510394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 17610394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 17710394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 1789489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1799243SN/A 18010394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 18110394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 18210394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 18310394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 18410394Swendy.elsasser@arm.com tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 18510394Swendy.elsasser@arm.com 1869243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1879489SN/A tRFC = Param.Latency("Refresh cycle time") 1889243SN/A 1899243SN/A # refresh command interval, how often a "ref" command needs 1909243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1919489SN/A tREFI = Param.Latency("Refresh command interval") 1929243SN/A 19310393Swendy.elsasser@arm.com # write-to-read, same rank turnaround penalty 19410393Swendy.elsasser@arm.com tWTR = Param.Latency("Write to read, same rank switching time") 1959243SN/A 19610393Swendy.elsasser@arm.com # read-to-write, same rank turnaround penalty 19710393Swendy.elsasser@arm.com tRTW = Param.Latency("Read to write, same rank switching time") 19810393Swendy.elsasser@arm.com 19910393Swendy.elsasser@arm.com # rank-to-rank bus delay penalty 20010393Swendy.elsasser@arm.com # this does not correlate to a memory timing parameter and encompasses: 20110393Swendy.elsasser@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 20210393Swendy.elsasser@arm.com # different rank bus delay 20310393Swendy.elsasser@arm.com tCS = Param.Latency("Rank to rank switching time") 20410206Sandreas.hansson@arm.com 2059971SN/A # minimum row activate to row activate delay time 2069971SN/A tRRD = Param.Latency("ACT to ACT delay") 2079971SN/A 20810394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 20910394Swendy.elsasser@arm.com tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 21010394Swendy.elsasser@arm.com 2119488SN/A # time window in which a maximum number of activates are allowed 2129488SN/A # to take place, set to 0 to disable 2139489SN/A tXAW = Param.Latency("X activation window") 2149489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 2159488SN/A 21610430SOmar.Naji@arm.com # time to exit power-down mode 21710430SOmar.Naji@arm.com # Exit power-down to next valid command delay 21810430SOmar.Naji@arm.com tXP = Param.Latency("0ns", "Power-up Delay") 21910430SOmar.Naji@arm.com 22010430SOmar.Naji@arm.com # Exit Powerdown to commands requiring a locked DLL 22110430SOmar.Naji@arm.com tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL") 22210430SOmar.Naji@arm.com 22310430SOmar.Naji@arm.com # time to exit self-refresh mode 22410430SOmar.Naji@arm.com tXS = Param.Latency("0ns", "Self-refresh exit latency") 22510430SOmar.Naji@arm.com 22610430SOmar.Naji@arm.com # time to exit self-refresh mode with locked DLL 22710430SOmar.Naji@arm.com tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL") 22810430SOmar.Naji@arm.com 2299488SN/A # Currently rolled into other params 2309243SN/A ###################################################################### 2319243SN/A 2329963SN/A # tRC - assumed to be tRAS + tRP 2339243SN/A 23410430SOmar.Naji@arm.com # Power Behaviour and Constraints 23510430SOmar.Naji@arm.com # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are 23610430SOmar.Naji@arm.com # defined as VDD and VDD2. Each current is defined for each voltage domain 23710430SOmar.Naji@arm.com # separately. For example, current IDD0 is active-precharge current for 23810430SOmar.Naji@arm.com # voltage domain VDD and current IDD02 is active-precharge current for 23910430SOmar.Naji@arm.com # voltage domain VDD2. 24010430SOmar.Naji@arm.com # By default all currents are set to 0mA. Users who are only interested in 24110430SOmar.Naji@arm.com # the performance of DRAMs can leave them at 0. 24210430SOmar.Naji@arm.com 24310430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current 24410430SOmar.Naji@arm.com IDD0 = Param.Current("0mA", "Active precharge current") 24510430SOmar.Naji@arm.com 24610430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current multiple voltage Range 24710430SOmar.Naji@arm.com IDD02 = Param.Current("0mA", "Active precharge current VDD2") 24810430SOmar.Naji@arm.com 24910430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit 25010430SOmar.Naji@arm.com IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow") 25110430SOmar.Naji@arm.com 25210430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit multiple voltage Range 25310430SOmar.Naji@arm.com IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2") 25410430SOmar.Naji@arm.com 25510430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit 25610430SOmar.Naji@arm.com IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast") 25710430SOmar.Naji@arm.com 25810430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit multiple voltage Range 25910430SOmar.Naji@arm.com IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2") 26010430SOmar.Naji@arm.com 26110430SOmar.Naji@arm.com # Precharge Standby current 26210430SOmar.Naji@arm.com IDD2N = Param.Current("0mA", "Precharge Standby current") 26310430SOmar.Naji@arm.com 26410430SOmar.Naji@arm.com # Precharge Standby current multiple voltage range 26510430SOmar.Naji@arm.com IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2") 26610430SOmar.Naji@arm.com 26710430SOmar.Naji@arm.com # Active Power-down current: slow exit 26810430SOmar.Naji@arm.com IDD3P0 = Param.Current("0mA", "Active Powerdown slow") 26910430SOmar.Naji@arm.com 27010430SOmar.Naji@arm.com # Active Power-down current: slow exit multiple voltage range 27110430SOmar.Naji@arm.com IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2") 27210430SOmar.Naji@arm.com 27310430SOmar.Naji@arm.com # Active Power-down current : fast exit 27410430SOmar.Naji@arm.com IDD3P1 = Param.Current("0mA", "Active Powerdown fast") 27510430SOmar.Naji@arm.com 27610430SOmar.Naji@arm.com # Active Power-down current : fast exit multiple voltage range 27710430SOmar.Naji@arm.com IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2") 27810430SOmar.Naji@arm.com 27910430SOmar.Naji@arm.com # Active Standby current 28010430SOmar.Naji@arm.com IDD3N = Param.Current("0mA", "Active Standby current") 28110430SOmar.Naji@arm.com 28210430SOmar.Naji@arm.com # Active Standby current multiple voltage range 28310430SOmar.Naji@arm.com IDD3N2 = Param.Current("0mA", "Active Standby current VDD2") 28410430SOmar.Naji@arm.com 28510430SOmar.Naji@arm.com # Burst Read Operating Current 28610430SOmar.Naji@arm.com IDD4R = Param.Current("0mA", "READ current") 28710430SOmar.Naji@arm.com 28810430SOmar.Naji@arm.com # Burst Read Operating Current multiple voltage range 28910430SOmar.Naji@arm.com IDD4R2 = Param.Current("0mA", "READ current VDD2") 29010430SOmar.Naji@arm.com 29110430SOmar.Naji@arm.com # Burst Write Operating Current 29210430SOmar.Naji@arm.com IDD4W = Param.Current("0mA", "WRITE current") 29310430SOmar.Naji@arm.com 29410430SOmar.Naji@arm.com # Burst Write Operating Current multiple voltage range 29510430SOmar.Naji@arm.com IDD4W2 = Param.Current("0mA", "WRITE current VDD2") 29610430SOmar.Naji@arm.com 29710430SOmar.Naji@arm.com # Refresh Current 29810430SOmar.Naji@arm.com IDD5 = Param.Current("0mA", "Refresh current") 29910430SOmar.Naji@arm.com 30010430SOmar.Naji@arm.com # Refresh Current multiple voltage range 30110430SOmar.Naji@arm.com IDD52 = Param.Current("0mA", "Refresh current VDD2") 30210430SOmar.Naji@arm.com 30310430SOmar.Naji@arm.com # Self-Refresh Current 30410430SOmar.Naji@arm.com IDD6 = Param.Current("0mA", "Self-refresh Current") 30510430SOmar.Naji@arm.com 30610430SOmar.Naji@arm.com # Self-Refresh Current multiple voltage range 30710430SOmar.Naji@arm.com IDD62 = Param.Current("0mA", "Self-refresh Current VDD2") 30810430SOmar.Naji@arm.com 30910430SOmar.Naji@arm.com # Main voltage range of the DRAM 31010430SOmar.Naji@arm.com VDD = Param.Voltage("0V", "Main Voltage Range") 31110430SOmar.Naji@arm.com 31210430SOmar.Naji@arm.com # Second voltage range defined by some DRAMs 31310430SOmar.Naji@arm.com VDD2 = Param.Voltage("0V", "2nd Voltage Range") 31410430SOmar.Naji@arm.com 31510217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 31610217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 31710430SOmar.Naji@arm.com# an 8x8 configuration. 31811837Swendy.elsasser@arm.comclass DDR3_1600_8x8(DRAMCtrl): 31910489SOmar.Naji@arm.com # size of device in bytes 32010489SOmar.Naji@arm.com device_size = '512MB' 32110489SOmar.Naji@arm.com 3229831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 3239831SN/A device_bus_width = 8 3249831SN/A 3259831SN/A # DDR3 is a BL8 device 3269831SN/A burst_length = 8 3279831SN/A 32810217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 3299831SN/A device_rowbuffer_size = '1kB' 3309831SN/A 3319831SN/A # 8x8 configuration, so 8 devices 3329831SN/A devices_per_rank = 8 3339489SN/A 3349489SN/A # Use two ranks 3359489SN/A ranks_per_channel = 2 3369489SN/A 3379489SN/A # DDR3 has 8 banks in all configurations 3389489SN/A banks_per_rank = 8 3399489SN/A 34010216Sandreas.hansson@arm.com # 800 MHz 34110216Sandreas.hansson@arm.com tCK = '1.25ns' 34210216Sandreas.hansson@arm.com 34310217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 34410217Sandreas.hansson@arm.com tBURST = '5ns' 34510217Sandreas.hansson@arm.com 34610217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 3479489SN/A tRCD = '13.75ns' 3489489SN/A tCL = '13.75ns' 3499489SN/A tRP = '13.75ns' 3509970SN/A tRAS = '35ns' 35110217Sandreas.hansson@arm.com tRRD = '6ns' 35210217Sandreas.hansson@arm.com tXAW = '30ns' 35310217Sandreas.hansson@arm.com activation_limit = 4 35410217Sandreas.hansson@arm.com tRFC = '260ns' 35510217Sandreas.hansson@arm.com 35610210Sandreas.hansson@arm.com tWR = '15ns' 35710217Sandreas.hansson@arm.com 35810217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 35910217Sandreas.hansson@arm.com tWTR = '7.5ns' 36010217Sandreas.hansson@arm.com 36110217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 36210212Sandreas.hansson@arm.com tRTP = '7.5ns' 3639489SN/A 36410393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 36510206Sandreas.hansson@arm.com tRTW = '2.5ns' 36610206Sandreas.hansson@arm.com 36710393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 36810393Swendy.elsasser@arm.com tCS = '2.5ns' 36910393Swendy.elsasser@arm.com 37010217Sandreas.hansson@arm.com # <=85C, half for >85C 37110217Sandreas.hansson@arm.com tREFI = '7.8us' 3729971SN/A 37311673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 37411673SOmar.Naji@arm.com tXP = '6ns' 37511673SOmar.Naji@arm.com 37611673SOmar.Naji@arm.com # self refresh exit time 37711673SOmar.Naji@arm.com tXS = '270ns' 37811673SOmar.Naji@arm.com 37911674SOmar.Naji@arm.com # Current values from datasheet Die Rev E,J 38011674SOmar.Naji@arm.com IDD0 = '55mA' 38111674SOmar.Naji@arm.com IDD2N = '32mA' 38211674SOmar.Naji@arm.com IDD3N = '38mA' 38311674SOmar.Naji@arm.com IDD4W = '125mA' 38411674SOmar.Naji@arm.com IDD4R = '157mA' 38511674SOmar.Naji@arm.com IDD5 = '235mA' 38611679SOmar.Naji@arm.com IDD3P1 = '38mA' 38711679SOmar.Naji@arm.com IDD2P1 = '32mA' 38811679SOmar.Naji@arm.com IDD6 = '20mA' 38910430SOmar.Naji@arm.com VDD = '1.5V' 39010430SOmar.Naji@arm.com 39110864Sjungma@eit.uni-kl.de# A single HMC-2500 x32 model based on: 39210864Sjungma@eit.uni-kl.de# [1] DRAMSpec: a high-level DRAM bank modelling tool 39310864Sjungma@eit.uni-kl.de# developed at the University of Kaiserslautern. This high level tool 39410864Sjungma@eit.uni-kl.de# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to 39510864Sjungma@eit.uni-kl.de# estimate the DRAM bank latency and power numbers. 39611186Serfan.azarkhish@unibo.it# [2] High performance AXI-4.0 based interconnect for extensible smart memory 39711186Serfan.azarkhish@unibo.it# cubes (E. Azarkhish et. al) 39810864Sjungma@eit.uni-kl.de# Assumed for the HMC model is a 30 nm technology node. 39910864Sjungma@eit.uni-kl.de# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4 40010864Sjungma@eit.uni-kl.de# layers). 40110864Sjungma@eit.uni-kl.de# Each layer has 16 vaults and each vault consists of 2 banks per layer. 40210864Sjungma@eit.uni-kl.de# In order to be able to use the same controller used for 2D DRAM generations 40310864Sjungma@eit.uni-kl.de# for HMC, the following analogy is done: 40410864Sjungma@eit.uni-kl.de# Channel (DDR) => Vault (HMC) 40510864Sjungma@eit.uni-kl.de# device_size (DDR) => size of a single layer in a vault 40610864Sjungma@eit.uni-kl.de# ranks per channel (DDR) => number of layers 40710864Sjungma@eit.uni-kl.de# banks per rank (DDR) => banks per layer 40810864Sjungma@eit.uni-kl.de# devices per rank (DDR) => devices per layer ( 1 for HMC). 40910864Sjungma@eit.uni-kl.de# The parameters for which no input is available are inherited from the DDR3 41010864Sjungma@eit.uni-kl.de# configuration. 41111186Serfan.azarkhish@unibo.it# This configuration includes the latencies from the DRAM to the logic layer 41211186Serfan.azarkhish@unibo.it# of the HMC 41311837Swendy.elsasser@arm.comclass HMC_2500_1x32(DDR3_1600_8x8): 41410864Sjungma@eit.uni-kl.de # size of device 41510864Sjungma@eit.uni-kl.de # two banks per device with each bank 4MB [2] 41610864Sjungma@eit.uni-kl.de device_size = '8MB' 41710864Sjungma@eit.uni-kl.de 41810864Sjungma@eit.uni-kl.de # 1x32 configuration, 1 device with 32 TSVs [2] 41910864Sjungma@eit.uni-kl.de device_bus_width = 32 42010864Sjungma@eit.uni-kl.de 42110864Sjungma@eit.uni-kl.de # HMC is a BL8 device [2] 42210864Sjungma@eit.uni-kl.de burst_length = 8 42310864Sjungma@eit.uni-kl.de 42410864Sjungma@eit.uni-kl.de # Each device has a page (row buffer) size of 256 bytes [2] 42510864Sjungma@eit.uni-kl.de device_rowbuffer_size = '256B' 42610864Sjungma@eit.uni-kl.de 42710864Sjungma@eit.uni-kl.de # 1x32 configuration, so 1 device [2] 42810864Sjungma@eit.uni-kl.de devices_per_rank = 1 42910864Sjungma@eit.uni-kl.de 43010864Sjungma@eit.uni-kl.de # 4 layers so 4 ranks [2] 43110864Sjungma@eit.uni-kl.de ranks_per_channel = 4 43210864Sjungma@eit.uni-kl.de 43310864Sjungma@eit.uni-kl.de # HMC has 2 banks per layer [2] 43410864Sjungma@eit.uni-kl.de # Each layer represents a rank. With 4 layers and 8 banks in total, each 43510864Sjungma@eit.uni-kl.de # layer has 2 banks; thus 2 banks per rank. 43610864Sjungma@eit.uni-kl.de banks_per_rank = 2 43710864Sjungma@eit.uni-kl.de 43810864Sjungma@eit.uni-kl.de # 1250 MHz [2] 43910864Sjungma@eit.uni-kl.de tCK = '0.8ns' 44010864Sjungma@eit.uni-kl.de 44110864Sjungma@eit.uni-kl.de # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz 44210864Sjungma@eit.uni-kl.de tBURST = '3.2ns' 44310864Sjungma@eit.uni-kl.de 44410864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 44510864Sjungma@eit.uni-kl.de tRCD = '10.2ns' 44610864Sjungma@eit.uni-kl.de tCL = '9.9ns' 44710864Sjungma@eit.uni-kl.de tRP = '7.7ns' 44810864Sjungma@eit.uni-kl.de tRAS = '21.6ns' 44910864Sjungma@eit.uni-kl.de 45010864Sjungma@eit.uni-kl.de # tRRD depends on the power supply network for each vendor. 45110864Sjungma@eit.uni-kl.de # We assume a tRRD of a double bank approach to be equal to 4 clock 45210864Sjungma@eit.uni-kl.de # cycles (Assumption) 45310864Sjungma@eit.uni-kl.de tRRD = '3.2ns' 45410864Sjungma@eit.uni-kl.de 45511186Serfan.azarkhish@unibo.it # activation limit is set to 0 since there are only 2 banks per vault 45611186Serfan.azarkhish@unibo.it # layer. 45710864Sjungma@eit.uni-kl.de activation_limit = 0 45810864Sjungma@eit.uni-kl.de 45910864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 46010864Sjungma@eit.uni-kl.de tRFC = '59ns' 46110864Sjungma@eit.uni-kl.de tWR = '8ns' 46210864Sjungma@eit.uni-kl.de tRTP = '4.9ns' 46310864Sjungma@eit.uni-kl.de 46411186Serfan.azarkhish@unibo.it # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 46511186Serfan.azarkhish@unibo.it # 0.8 ns (Assumption) 46610864Sjungma@eit.uni-kl.de tCS = '0.8ns' 46710864Sjungma@eit.uni-kl.de 46810864Sjungma@eit.uni-kl.de # Value using DRAMSpec HMC model [1] 46910864Sjungma@eit.uni-kl.de tREFI = '3.9us' 47010864Sjungma@eit.uni-kl.de 47111186Serfan.azarkhish@unibo.it # The default page policy in the vault controllers is simple closed page 47211186Serfan.azarkhish@unibo.it # [2] nevertheless 'close' policy opens and closes the row multiple times 47311186Serfan.azarkhish@unibo.it # for bursts largers than 32Bytes. For this reason we use 'close_adaptive' 47411186Serfan.azarkhish@unibo.it page_policy = 'close_adaptive' 47511186Serfan.azarkhish@unibo.it 47611186Serfan.azarkhish@unibo.it # RoCoRaBaCh resembles the default address mapping in HMC 47710864Sjungma@eit.uni-kl.de addr_mapping = 'RoCoRaBaCh' 47810864Sjungma@eit.uni-kl.de min_writes_per_switch = 8 47910864Sjungma@eit.uni-kl.de 48011186Serfan.azarkhish@unibo.it # These parameters do not directly correlate with buffer_size in real 48111186Serfan.azarkhish@unibo.it # hardware. Nevertheless, their value has been tuned to achieve a 48211186Serfan.azarkhish@unibo.it # bandwidth similar to the cycle-accurate model in [2] 48311186Serfan.azarkhish@unibo.it write_buffer_size = 32 48411186Serfan.azarkhish@unibo.it read_buffer_size = 32 48511186Serfan.azarkhish@unibo.it 48611186Serfan.azarkhish@unibo.it # The static latency of the vault controllers is estimated to be smaller 48711186Serfan.azarkhish@unibo.it # than a full DRAM channel controller 48811186Serfan.azarkhish@unibo.it static_backend_latency='4ns' 48911186Serfan.azarkhish@unibo.it static_frontend_latency='4ns' 49011186Serfan.azarkhish@unibo.it 49110217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 49210217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 49310217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 49410217Sandreas.hansson@arm.com# consistent across the two configurations. 49511837Swendy.elsasser@arm.comclass DDR3_2133_8x8(DDR3_1600_8x8): 49610217Sandreas.hansson@arm.com # 1066 MHz 49710217Sandreas.hansson@arm.com tCK = '0.938ns' 49810217Sandreas.hansson@arm.com 49910217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 50010217Sandreas.hansson@arm.com tBURST = '3.752ns' 50110217Sandreas.hansson@arm.com 50210217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 50310217Sandreas.hansson@arm.com tRCD = '13.09ns' 50410217Sandreas.hansson@arm.com tCL = '13.09ns' 50510217Sandreas.hansson@arm.com tRP = '13.09ns' 50610217Sandreas.hansson@arm.com tRAS = '33ns' 50710217Sandreas.hansson@arm.com tRRD = '5ns' 50810217Sandreas.hansson@arm.com tXAW = '25ns' 50910217Sandreas.hansson@arm.com 51010430SOmar.Naji@arm.com # Current values from datasheet 51110430SOmar.Naji@arm.com IDD0 = '70mA' 51210430SOmar.Naji@arm.com IDD2N = '37mA' 51310430SOmar.Naji@arm.com IDD3N = '44mA' 51410430SOmar.Naji@arm.com IDD4W = '157mA' 51510430SOmar.Naji@arm.com IDD4R = '191mA' 51610430SOmar.Naji@arm.com IDD5 = '250mA' 51711679SOmar.Naji@arm.com IDD3P1 = '44mA' 51811679SOmar.Naji@arm.com IDD2P1 = '43mA' 51911679SOmar.Naji@arm.com IDD6 ='20mA' 52010430SOmar.Naji@arm.com VDD = '1.5V' 52110430SOmar.Naji@arm.com 52210217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 52311837Swendy.elsasser@arm.com# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A2G4) 52411837Swendy.elsasser@arm.com# in an 16x4 configuration. 52511837Swendy.elsasser@arm.com# Total channel capacity is 32GB 52611837Swendy.elsasser@arm.com# 16 devices/rank * 2 ranks/channel * 1GB/device = 32GB/channel 52711837Swendy.elsasser@arm.comclass DDR4_2400_16x4(DRAMCtrl): 52810489SOmar.Naji@arm.com # size of device 52911837Swendy.elsasser@arm.com device_size = '1GB' 53010489SOmar.Naji@arm.com 53111837Swendy.elsasser@arm.com # 16x4 configuration, 16 devices each with a 4-bit interface 53211837Swendy.elsasser@arm.com device_bus_width = 4 53310217Sandreas.hansson@arm.com 53410217Sandreas.hansson@arm.com # DDR4 is a BL8 device 53510217Sandreas.hansson@arm.com burst_length = 8 53610217Sandreas.hansson@arm.com 53711837Swendy.elsasser@arm.com # Each device has a page (row buffer) size of 512 byte (1K columns x4) 53811837Swendy.elsasser@arm.com device_rowbuffer_size = '512B' 53910217Sandreas.hansson@arm.com 54011837Swendy.elsasser@arm.com # 16x4 configuration, so 16 devices 54111837Swendy.elsasser@arm.com devices_per_rank = 16 54210217Sandreas.hansson@arm.com 54310430SOmar.Naji@arm.com # Match our DDR3 configurations which is dual rank 54410430SOmar.Naji@arm.com ranks_per_channel = 2 54510217Sandreas.hansson@arm.com 54610394Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 54711837Swendy.elsasser@arm.com # Set to 4 for x4 case 54811837Swendy.elsasser@arm.com bank_groups_per_rank = 4 54910394Swendy.elsasser@arm.com 55011672SOmar.Naji@arm.com # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 55111672SOmar.Naji@arm.com # configurations). Currently we do not capture the additional 55210217Sandreas.hansson@arm.com # constraints incurred by the bank groups 55311837Swendy.elsasser@arm.com banks_per_rank = 16 55410217Sandreas.hansson@arm.com 55510891Sandreas.hansson@arm.com # override the default buffer sizes and go for something larger to 55610891Sandreas.hansson@arm.com # accommodate the larger bank count 55710891Sandreas.hansson@arm.com write_buffer_size = 128 55810891Sandreas.hansson@arm.com read_buffer_size = 64 55910891Sandreas.hansson@arm.com 56010217Sandreas.hansson@arm.com # 1200 MHz 56110217Sandreas.hansson@arm.com tCK = '0.833ns' 56210217Sandreas.hansson@arm.com 56310217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 56410394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 56510394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 56610394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 56711837Swendy.elsasser@arm.com tBURST = '3.332ns' 56810217Sandreas.hansson@arm.com 56910394Swendy.elsasser@arm.com # @2400 data rate, tCCD_L is 6 CK 57010394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 57110394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 57210394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 57310394Swendy.elsasser@arm.com tCCD_L = '5ns'; 57410394Swendy.elsasser@arm.com 57511837Swendy.elsasser@arm.com # DDR4-2400 17-17-17 57611837Swendy.elsasser@arm.com tRCD = '14.16ns' 57711837Swendy.elsasser@arm.com tCL = '14.16ns' 57811837Swendy.elsasser@arm.com tRP = '14.16ns' 57911837Swendy.elsasser@arm.com tRAS = '32ns' 58010217Sandreas.hansson@arm.com 58111837Swendy.elsasser@arm.com # RRD_S (different bank group) for 512B page is MAX(4 CK, 3.3ns) 58211837Swendy.elsasser@arm.com tRRD = '3.332ns' 58310394Swendy.elsasser@arm.com 58411837Swendy.elsasser@arm.com # RRD_L (same bank group) for 512B page is MAX(4 CK, 4.9ns) 58511837Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 58610394Swendy.elsasser@arm.com 58711837Swendy.elsasser@arm.com # tFAW for 512B page is MAX(16 CK, 13ns) 58811837Swendy.elsasser@arm.com tXAW = '13.328ns' 5899489SN/A activation_limit = 4 59011837Swendy.elsasser@arm.com # tRFC is 350ns 59111837Swendy.elsasser@arm.com tRFC = '350ns' 5929489SN/A 59310217Sandreas.hansson@arm.com tWR = '15ns' 59410217Sandreas.hansson@arm.com 59510217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 59610217Sandreas.hansson@arm.com tWTR = '5ns' 59710217Sandreas.hansson@arm.com 59810217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 59910217Sandreas.hansson@arm.com tRTP = '7.5ns' 60010217Sandreas.hansson@arm.com 60110393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 60210217Sandreas.hansson@arm.com tRTW = '1.666ns' 60310217Sandreas.hansson@arm.com 60410393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 60510393Swendy.elsasser@arm.com tCS = '1.666ns' 60610393Swendy.elsasser@arm.com 60710217Sandreas.hansson@arm.com # <=85C, half for >85C 60810217Sandreas.hansson@arm.com tREFI = '7.8us' 6099489SN/A 61011673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 61111673SOmar.Naji@arm.com tXP = '6ns' 61211673SOmar.Naji@arm.com 61311673SOmar.Naji@arm.com # self refresh exit time 61411837Swendy.elsasser@arm.com # exit delay to ACT, PRE, PREALL, REF, SREF Enter, and PD Enter is: 61511837Swendy.elsasser@arm.com # tRFC + 10ns = 340ns 61611837Swendy.elsasser@arm.com tXS = '340ns' 61711673SOmar.Naji@arm.com 61810430SOmar.Naji@arm.com # Current values from datasheet 61911837Swendy.elsasser@arm.com IDD0 = '43mA' 62011837Swendy.elsasser@arm.com IDD02 = '3mA' 62111837Swendy.elsasser@arm.com IDD2N = '34mA' 62211837Swendy.elsasser@arm.com IDD3N = '38mA' 62310430SOmar.Naji@arm.com IDD3N2 = '3mA' 62411837Swendy.elsasser@arm.com IDD4W = '103mA' 62511837Swendy.elsasser@arm.com IDD4R = '110mA' 62611837Swendy.elsasser@arm.com IDD5 = '250mA' 62711837Swendy.elsasser@arm.com IDD3P1 = '32mA' 62811837Swendy.elsasser@arm.com IDD2P1 = '25mA' 62911837Swendy.elsasser@arm.com IDD6 = '30mA' 63010430SOmar.Naji@arm.com VDD = '1.2V' 63110430SOmar.Naji@arm.com VDD2 = '2.5V' 63210430SOmar.Naji@arm.com 63311837Swendy.elsasser@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 63411837Swendy.elsasser@arm.com# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A1G8) 63511837Swendy.elsasser@arm.com# in an 8x8 configuration. 63611837Swendy.elsasser@arm.com# Total channel capacity is 16GB 63711837Swendy.elsasser@arm.com# 8 devices/rank * 2 ranks/channel * 1GB/device = 16GB/channel 63811837Swendy.elsasser@arm.comclass DDR4_2400_8x8(DDR4_2400_16x4): 63911837Swendy.elsasser@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 64011837Swendy.elsasser@arm.com device_bus_width = 8 64111837Swendy.elsasser@arm.com 64211837Swendy.elsasser@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 64311837Swendy.elsasser@arm.com device_rowbuffer_size = '1kB' 64411837Swendy.elsasser@arm.com 64511837Swendy.elsasser@arm.com # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 64611837Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 64711837Swendy.elsasser@arm.com 64811837Swendy.elsasser@arm.com tXAW = '21ns' 64911837Swendy.elsasser@arm.com 65011837Swendy.elsasser@arm.com # Current values from datasheet 65111837Swendy.elsasser@arm.com IDD0 = '48mA' 65211837Swendy.elsasser@arm.com IDD3N = '43mA' 65311837Swendy.elsasser@arm.com IDD4W = '123mA' 65411837Swendy.elsasser@arm.com IDD4R = '135mA' 65511837Swendy.elsasser@arm.com IDD3P1 = '37mA' 65611837Swendy.elsasser@arm.com 65711837Swendy.elsasser@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 65811837Swendy.elsasser@arm.com# timings based on a DDR4-2400 8 Gbit datasheet (Micron MT40A512M16) 65911837Swendy.elsasser@arm.com# in an 4x16 configuration. 66011837Swendy.elsasser@arm.com# Total channel capacity is 4GB 66111837Swendy.elsasser@arm.com# 4 devices/rank * 1 ranks/channel * 1GB/device = 4GB/channel 66211837Swendy.elsasser@arm.comclass DDR4_2400_4x16(DDR4_2400_16x4): 66311837Swendy.elsasser@arm.com # 4x16 configuration, 4 devices each with an 16-bit interface 66411837Swendy.elsasser@arm.com device_bus_width = 16 66511837Swendy.elsasser@arm.com 66611837Swendy.elsasser@arm.com # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16) 66711837Swendy.elsasser@arm.com device_rowbuffer_size = '2kB' 66811837Swendy.elsasser@arm.com 66911837Swendy.elsasser@arm.com # 4x16 configuration, so 4 devices 67011837Swendy.elsasser@arm.com devices_per_rank = 4 67111837Swendy.elsasser@arm.com 67211837Swendy.elsasser@arm.com # Single rank for x16 67311837Swendy.elsasser@arm.com ranks_per_channel = 1 67411837Swendy.elsasser@arm.com 67511837Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 67611837Swendy.elsasser@arm.com # Set to 2 for x16 case 67711837Swendy.elsasser@arm.com bank_groups_per_rank = 2 67811837Swendy.elsasser@arm.com 67911837Swendy.elsasser@arm.com # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 68011837Swendy.elsasser@arm.com # configurations). Currently we do not capture the additional 68111837Swendy.elsasser@arm.com # constraints incurred by the bank groups 68211837Swendy.elsasser@arm.com banks_per_rank = 8 68311837Swendy.elsasser@arm.com 68411837Swendy.elsasser@arm.com # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns) 68511837Swendy.elsasser@arm.com tRRD = '5.3ns' 68611837Swendy.elsasser@arm.com 68711837Swendy.elsasser@arm.com # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns) 68811837Swendy.elsasser@arm.com tRRD_L = '6.4ns'; 68911837Swendy.elsasser@arm.com 69011837Swendy.elsasser@arm.com tXAW = '30ns' 69111837Swendy.elsasser@arm.com 69211837Swendy.elsasser@arm.com # Current values from datasheet 69311837Swendy.elsasser@arm.com IDD0 = '80mA' 69411837Swendy.elsasser@arm.com IDD02 = '4mA' 69511837Swendy.elsasser@arm.com IDD2N = '34mA' 69611837Swendy.elsasser@arm.com IDD3N = '47mA' 69711837Swendy.elsasser@arm.com IDD4W = '228mA' 69811837Swendy.elsasser@arm.com IDD4R = '243mA' 69911837Swendy.elsasser@arm.com IDD5 = '280mA' 70011837Swendy.elsasser@arm.com IDD3P1 = '41mA' 70111837Swendy.elsasser@arm.com 7029728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 70310430SOmar.Naji@arm.com# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 70410430SOmar.Naji@arm.com# in a 1x32 configuration. 70511837Swendy.elsasser@arm.comclass LPDDR2_S4_1066_1x32(DRAMCtrl): 70610430SOmar.Naji@arm.com # No DLL in LPDDR2 70710430SOmar.Naji@arm.com dll = False 70810430SOmar.Naji@arm.com 70910489SOmar.Naji@arm.com # size of device 71010489SOmar.Naji@arm.com device_size = '512MB' 71110489SOmar.Naji@arm.com 7129831SN/A # 1x32 configuration, 1 device with a 32-bit interface 7139831SN/A device_bus_width = 32 7149831SN/A 7159831SN/A # LPDDR2_S4 is a BL4 and BL8 device 7169831SN/A burst_length = 8 7179831SN/A 7189831SN/A # Each device has a page (row buffer) size of 1KB 7199831SN/A # (this depends on the memory density) 7209831SN/A device_rowbuffer_size = '1kB' 7219831SN/A 7229831SN/A # 1x32 configuration, so 1 device 7239831SN/A devices_per_rank = 1 7249489SN/A 7259708SN/A # Use a single rank 7269708SN/A ranks_per_channel = 1 7279489SN/A 7289489SN/A # LPDDR2-S4 has 8 banks in all configurations 7299489SN/A banks_per_rank = 8 7309489SN/A 73110216Sandreas.hansson@arm.com # 533 MHz 73210216Sandreas.hansson@arm.com tCK = '1.876ns' 73310216Sandreas.hansson@arm.com 7349489SN/A # Fixed at 15 ns 7359489SN/A tRCD = '15ns' 7369489SN/A 7379489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 7389489SN/A tCL = '15ns' 7399489SN/A 7409728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 7419728SN/A tRP = '15ns' 7429489SN/A 7439970SN/A tRAS = '42ns' 74410210Sandreas.hansson@arm.com tWR = '15ns' 7459963SN/A 74610430SOmar.Naji@arm.com tRTP = '7.5ns' 74710212Sandreas.hansson@arm.com 7489831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 7499831SN/A # Note this is a BL8 DDR device. 7509831SN/A # Requests larger than 32 bytes are broken down into multiple requests 75110146Sandreas.hansson@arm.com # in the controller 7529831SN/A tBURST = '7.5ns' 7539489SN/A 7549708SN/A # LPDDR2-S4, 4 Gbit 7559489SN/A tRFC = '130ns' 7569489SN/A tREFI = '3.9us' 7579489SN/A 75811673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 75911673SOmar.Naji@arm.com tXP = '7.5ns' 76011673SOmar.Naji@arm.com 76111673SOmar.Naji@arm.com # self refresh exit time 76211673SOmar.Naji@arm.com tXS = '140ns' 76311673SOmar.Naji@arm.com 7649489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 7659489SN/A tWTR = '7.5ns' 7669489SN/A 76710393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 76810206Sandreas.hansson@arm.com tRTW = '3.75ns' 76910206Sandreas.hansson@arm.com 77010393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 77110393Swendy.elsasser@arm.com tCS = '3.75ns' 77210393Swendy.elsasser@arm.com 7739971SN/A # Activate to activate irrespective of density and speed grade 7749971SN/A tRRD = '10.0ns' 7759971SN/A 7769708SN/A # Irrespective of density, tFAW is 50 ns 7779489SN/A tXAW = '50ns' 7789489SN/A activation_limit = 4 7799664SN/A 78010430SOmar.Naji@arm.com # Current values from datasheet 78110430SOmar.Naji@arm.com IDD0 = '15mA' 78210430SOmar.Naji@arm.com IDD02 = '70mA' 78310430SOmar.Naji@arm.com IDD2N = '2mA' 78410430SOmar.Naji@arm.com IDD2N2 = '30mA' 78510430SOmar.Naji@arm.com IDD3N = '2.5mA' 78610430SOmar.Naji@arm.com IDD3N2 = '30mA' 78710430SOmar.Naji@arm.com IDD4W = '10mA' 78810430SOmar.Naji@arm.com IDD4W2 = '190mA' 78910430SOmar.Naji@arm.com IDD4R = '3mA' 79010430SOmar.Naji@arm.com IDD4R2 = '220mA' 79110430SOmar.Naji@arm.com IDD5 = '40mA' 79210430SOmar.Naji@arm.com IDD52 = '150mA' 79311679SOmar.Naji@arm.com IDD3P1 = '1.2mA' 79411679SOmar.Naji@arm.com IDD3P12 = '8mA' 79511679SOmar.Naji@arm.com IDD2P1 = '0.6mA' 79611679SOmar.Naji@arm.com IDD2P12 = '0.8mA' 79711679SOmar.Naji@arm.com IDD6 = '1mA' 79811679SOmar.Naji@arm.com IDD62 = '3.2mA' 79910430SOmar.Naji@arm.com VDD = '1.8V' 80010430SOmar.Naji@arm.com VDD2 = '1.2V' 80110430SOmar.Naji@arm.com 8029728SN/A# A single WideIO x128 interface (one command and address bus), with 8039728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 80411837Swendy.elsasser@arm.comclass WideIO_200_1x128(DRAMCtrl): 80510430SOmar.Naji@arm.com # No DLL for WideIO 80610430SOmar.Naji@arm.com dll = False 80710430SOmar.Naji@arm.com 80810489SOmar.Naji@arm.com # size of device 80910489SOmar.Naji@arm.com device_size = '1024MB' 81010489SOmar.Naji@arm.com 8119831SN/A # 1x128 configuration, 1 device with a 128-bit interface 8129831SN/A device_bus_width = 128 8139831SN/A 8149831SN/A # This is a BL4 device 8159831SN/A burst_length = 4 8169831SN/A 8179831SN/A # Each device has a page (row buffer) size of 4KB 8189831SN/A # (this depends on the memory density) 8199831SN/A device_rowbuffer_size = '4kB' 8209831SN/A 8219831SN/A # 1x128 configuration, so 1 device 8229831SN/A devices_per_rank = 1 8239664SN/A 8249664SN/A # Use one rank for a one-high die stack 8259664SN/A ranks_per_channel = 1 8269664SN/A 8279664SN/A # WideIO has 4 banks in all configurations 8289664SN/A banks_per_rank = 4 8299664SN/A 83010216Sandreas.hansson@arm.com # 200 MHz 83110216Sandreas.hansson@arm.com tCK = '5ns' 83210216Sandreas.hansson@arm.com 8339664SN/A # WIO-200 8349664SN/A tRCD = '18ns' 8359664SN/A tCL = '18ns' 8369664SN/A tRP = '18ns' 8379970SN/A tRAS = '42ns' 83810210Sandreas.hansson@arm.com tWR = '15ns' 83910212Sandreas.hansson@arm.com # Read to precharge is same as the burst 84010212Sandreas.hansson@arm.com tRTP = '20ns' 8419664SN/A 8429831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 8439831SN/A # Note this is a BL4 SDR device. 8449664SN/A tBURST = '20ns' 8459664SN/A 8469664SN/A # WIO 8 Gb 8479664SN/A tRFC = '210ns' 8489664SN/A 8499664SN/A # WIO 8 Gb, <=85C, half for >85C 8509664SN/A tREFI = '3.9us' 8519664SN/A 8529664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 8539664SN/A tWTR = '15ns' 8549664SN/A 85510393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 85610206Sandreas.hansson@arm.com tRTW = '10ns' 85710206Sandreas.hansson@arm.com 85810393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 85910393Swendy.elsasser@arm.com tCS = '10ns' 86010393Swendy.elsasser@arm.com 8619971SN/A # Activate to activate irrespective of density and speed grade 8629971SN/A tRRD = '10.0ns' 8639971SN/A 8649664SN/A # Two instead of four activation window 8659664SN/A tXAW = '50ns' 8669664SN/A activation_limit = 2 8679709SN/A 86810430SOmar.Naji@arm.com # The WideIO specification does not provide current information 86910430SOmar.Naji@arm.com 8709728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 87110430SOmar.Naji@arm.com# default timings based on a LPDDR3-1600 4 Gbit part (Micron 87210430SOmar.Naji@arm.com# EDF8132A1MC) in a 1x32 configuration. 87311837Swendy.elsasser@arm.comclass LPDDR3_1600_1x32(DRAMCtrl): 87410430SOmar.Naji@arm.com # No DLL for LPDDR3 87510430SOmar.Naji@arm.com dll = False 87610430SOmar.Naji@arm.com 87710489SOmar.Naji@arm.com # size of device 87810489SOmar.Naji@arm.com device_size = '512MB' 87910489SOmar.Naji@arm.com 8809831SN/A # 1x32 configuration, 1 device with a 32-bit interface 8819831SN/A device_bus_width = 32 8829831SN/A 8839831SN/A # LPDDR3 is a BL8 device 8849831SN/A burst_length = 8 8859831SN/A 8869976SN/A # Each device has a page (row buffer) size of 4KB 8879976SN/A device_rowbuffer_size = '4kB' 8889831SN/A 8899831SN/A # 1x32 configuration, so 1 device 8909831SN/A devices_per_rank = 1 8919709SN/A 89210430SOmar.Naji@arm.com # Technically the datasheet is a dual-rank package, but for 89310430SOmar.Naji@arm.com # comparison with the LPDDR2 config we stick to a single rank 8949709SN/A ranks_per_channel = 1 8959709SN/A 8969709SN/A # LPDDR3 has 8 banks in all configurations 8979709SN/A banks_per_rank = 8 8989709SN/A 89910216Sandreas.hansson@arm.com # 800 MHz 90010216Sandreas.hansson@arm.com tCK = '1.25ns' 90110216Sandreas.hansson@arm.com 90210430SOmar.Naji@arm.com tRCD = '18ns' 9039709SN/A 9049709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 9059709SN/A tCL = '15ns' 9069709SN/A 9079970SN/A tRAS = '42ns' 90810210Sandreas.hansson@arm.com tWR = '15ns' 9099963SN/A 91010212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 91110212Sandreas.hansson@arm.com tRTP = '7.5ns' 91210212Sandreas.hansson@arm.com 91310430SOmar.Naji@arm.com # Pre-charge one bank 18 ns (all banks 21 ns) 91410430SOmar.Naji@arm.com tRP = '18ns' 9159709SN/A 9169831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 9179831SN/A # Note this is a BL8 DDR device. 9189831SN/A # Requests larger than 32 bytes are broken down into multiple requests 91910146Sandreas.hansson@arm.com # in the controller 9209831SN/A tBURST = '5ns' 9219709SN/A 9229709SN/A # LPDDR3, 4 Gb 9239709SN/A tRFC = '130ns' 9249709SN/A tREFI = '3.9us' 9259709SN/A 92611673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 92711673SOmar.Naji@arm.com tXP = '7.5ns' 92811673SOmar.Naji@arm.com 92911673SOmar.Naji@arm.com # self refresh exit time 93011673SOmar.Naji@arm.com tXS = '140ns' 93111673SOmar.Naji@arm.com 9329709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 9339709SN/A tWTR = '7.5ns' 9349709SN/A 93510393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 93610206Sandreas.hansson@arm.com tRTW = '2.5ns' 93710206Sandreas.hansson@arm.com 93810393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 93910393Swendy.elsasser@arm.com tCS = '2.5ns' 94010393Swendy.elsasser@arm.com 9419971SN/A # Activate to activate irrespective of density and speed grade 9429971SN/A tRRD = '10.0ns' 9439971SN/A 9449709SN/A # Irrespective of size, tFAW is 50 ns 9459709SN/A tXAW = '50ns' 9469709SN/A activation_limit = 4 94710430SOmar.Naji@arm.com 94810430SOmar.Naji@arm.com # Current values from datasheet 94910430SOmar.Naji@arm.com IDD0 = '8mA' 95010430SOmar.Naji@arm.com IDD02 = '60mA' 95110430SOmar.Naji@arm.com IDD2N = '0.8mA' 95210430SOmar.Naji@arm.com IDD2N2 = '26mA' 95310430SOmar.Naji@arm.com IDD3N = '2mA' 95410430SOmar.Naji@arm.com IDD3N2 = '34mA' 95510430SOmar.Naji@arm.com IDD4W = '2mA' 95610430SOmar.Naji@arm.com IDD4W2 = '190mA' 95710430SOmar.Naji@arm.com IDD4R = '2mA' 95810430SOmar.Naji@arm.com IDD4R2 = '230mA' 95910430SOmar.Naji@arm.com IDD5 = '28mA' 96010430SOmar.Naji@arm.com IDD52 = '150mA' 96111679SOmar.Naji@arm.com IDD3P1 = '1.4mA' 96211679SOmar.Naji@arm.com IDD3P12 = '11mA' 96311679SOmar.Naji@arm.com IDD2P1 = '0.8mA' 96411679SOmar.Naji@arm.com IDD2P12 = '1.8mA' 96511679SOmar.Naji@arm.com IDD6 = '0.5mA' 96611679SOmar.Naji@arm.com IDD62 = '1.8mA' 96710430SOmar.Naji@arm.com VDD = '1.8V' 96810430SOmar.Naji@arm.com VDD2 = '1.2V' 96910561SOmar.Naji@arm.com 97010561SOmar.Naji@arm.com# A single GDDR5 x64 interface, with 97110561SOmar.Naji@arm.com# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix 97210561SOmar.Naji@arm.com# H5GQ1H24AFR) in a 2x32 configuration. 97311837Swendy.elsasser@arm.comclass GDDR5_4000_2x32(DRAMCtrl): 97410561SOmar.Naji@arm.com # size of device 97510561SOmar.Naji@arm.com device_size = '128MB' 97610561SOmar.Naji@arm.com 97710561SOmar.Naji@arm.com # 2x32 configuration, 1 device with a 32-bit interface 97810561SOmar.Naji@arm.com device_bus_width = 32 97910561SOmar.Naji@arm.com 98010561SOmar.Naji@arm.com # GDDR5 is a BL8 device 98110561SOmar.Naji@arm.com burst_length = 8 98210561SOmar.Naji@arm.com 98310561SOmar.Naji@arm.com # Each device has a page (row buffer) size of 2Kbits (256Bytes) 98410561SOmar.Naji@arm.com device_rowbuffer_size = '256B' 98510561SOmar.Naji@arm.com 98610561SOmar.Naji@arm.com # 2x32 configuration, so 2 devices 98710561SOmar.Naji@arm.com devices_per_rank = 2 98810561SOmar.Naji@arm.com 98910561SOmar.Naji@arm.com # assume single rank 99010561SOmar.Naji@arm.com ranks_per_channel = 1 99110561SOmar.Naji@arm.com 99210561SOmar.Naji@arm.com # GDDR5 has 4 bank groups 99310561SOmar.Naji@arm.com bank_groups_per_rank = 4 99410561SOmar.Naji@arm.com 99510561SOmar.Naji@arm.com # GDDR5 has 16 banks with 4 bank groups 99610561SOmar.Naji@arm.com banks_per_rank = 16 99710561SOmar.Naji@arm.com 99810561SOmar.Naji@arm.com # 1000 MHz 99910561SOmar.Naji@arm.com tCK = '1ns' 100010561SOmar.Naji@arm.com 100110561SOmar.Naji@arm.com # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz 100210561SOmar.Naji@arm.com # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz ) 100310561SOmar.Naji@arm.com # 8 beats at 4000 MHz = 2 beats at 1000 MHz 100410561SOmar.Naji@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 100510561SOmar.Naji@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 100610561SOmar.Naji@arm.com # delay for bursts to different bank groups (tCCD_S) 100710561SOmar.Naji@arm.com tBURST = '2ns' 100810561SOmar.Naji@arm.com 100910561SOmar.Naji@arm.com # @1000MHz data rate, tCCD_L is 3 CK 101010561SOmar.Naji@arm.com # CAS-to-CAS delay for bursts to the same bank group 101110561SOmar.Naji@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 101210561SOmar.Naji@arm.com # for CAS-to-CAS delay for bursts to different bank groups 101310561SOmar.Naji@arm.com tCCD_L = '3ns'; 101410561SOmar.Naji@arm.com 101510561SOmar.Naji@arm.com tRCD = '12ns' 101610561SOmar.Naji@arm.com 101710561SOmar.Naji@arm.com # tCL is not directly found in datasheet and assumed equal tRCD 101810561SOmar.Naji@arm.com tCL = '12ns' 101910561SOmar.Naji@arm.com 102010561SOmar.Naji@arm.com tRP = '12ns' 102110561SOmar.Naji@arm.com tRAS = '28ns' 102210561SOmar.Naji@arm.com 102310561SOmar.Naji@arm.com # RRD_S (different bank group) 102410561SOmar.Naji@arm.com # RRD_S is 5.5 ns in datasheet. 102510561SOmar.Naji@arm.com # rounded to the next multiple of tCK 102610561SOmar.Naji@arm.com tRRD = '6ns' 102710561SOmar.Naji@arm.com 102810561SOmar.Naji@arm.com # RRD_L (same bank group) 102910561SOmar.Naji@arm.com # RRD_L is 5.5 ns in datasheet. 103010561SOmar.Naji@arm.com # rounded to the next multiple of tCK 103110561SOmar.Naji@arm.com tRRD_L = '6ns' 103210561SOmar.Naji@arm.com 103310561SOmar.Naji@arm.com tXAW = '23ns' 103410561SOmar.Naji@arm.com 103510561SOmar.Naji@arm.com # tXAW < 4 x tRRD. 103610561SOmar.Naji@arm.com # Therefore, activation limit is set to 0 103710561SOmar.Naji@arm.com activation_limit = 0 103810561SOmar.Naji@arm.com 103910561SOmar.Naji@arm.com tRFC = '65ns' 104010561SOmar.Naji@arm.com tWR = '12ns' 104110561SOmar.Naji@arm.com 104210561SOmar.Naji@arm.com # Here using the average of WTR_S and WTR_L 104310561SOmar.Naji@arm.com tWTR = '5ns' 104410561SOmar.Naji@arm.com 104510561SOmar.Naji@arm.com # Read-to-Precharge 2 CK 104610561SOmar.Naji@arm.com tRTP = '2ns' 104710561SOmar.Naji@arm.com 104810561SOmar.Naji@arm.com # Assume 2 cycles 104910561SOmar.Naji@arm.com tRTW = '2ns' 105010561SOmar.Naji@arm.com 105111120Swendy.elsasser@arm.com# A single HBM x128 interface (one command and address bus), with 105211120Swendy.elsasser@arm.com# default timings based on data publically released 105311120Swendy.elsasser@arm.com# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014), 105411120Swendy.elsasser@arm.com# IDD measurement values, and by extrapolating data from other classes. 105511120Swendy.elsasser@arm.com# Architecture values based on published HBM spec 105611120Swendy.elsasser@arm.com# A 4H stack is defined, 2Gb per die for a total of 1GB of memory. 105711837Swendy.elsasser@arm.comclass HBM_1000_4H_1x128(DRAMCtrl): 105811120Swendy.elsasser@arm.com # HBM gen1 supports up to 8 128-bit physical channels 105911120Swendy.elsasser@arm.com # Configuration defines a single channel, with the capacity 106011120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 8) based on 2Gb dies 106111120Swendy.elsasser@arm.com # To use all 8 channels, set 'channels' parameter to 8 in 106211120Swendy.elsasser@arm.com # system configuration 106311120Swendy.elsasser@arm.com 106411120Swendy.elsasser@arm.com # 128-bit interface legacy mode 106511120Swendy.elsasser@arm.com device_bus_width = 128 106611120Swendy.elsasser@arm.com 106711120Swendy.elsasser@arm.com # HBM supports BL4 and BL2 (legacy mode only) 106811120Swendy.elsasser@arm.com burst_length = 4 106911120Swendy.elsasser@arm.com 107011120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack; 107111120Swendy.elsasser@arm.com # with 8 channels, 128MB per channel 107211120Swendy.elsasser@arm.com device_size = '128MB' 107311120Swendy.elsasser@arm.com 107411120Swendy.elsasser@arm.com device_rowbuffer_size = '2kB' 107511120Swendy.elsasser@arm.com 107611120Swendy.elsasser@arm.com # 1x128 configuration 107711120Swendy.elsasser@arm.com devices_per_rank = 1 107811120Swendy.elsasser@arm.com 107911120Swendy.elsasser@arm.com # HBM does not have a CS pin; set rank to 1 108011120Swendy.elsasser@arm.com ranks_per_channel = 1 108111120Swendy.elsasser@arm.com 108211120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 108311120Swendy.elsasser@arm.com # 2Gb dies have 8 banks 108411120Swendy.elsasser@arm.com banks_per_rank = 8 108511120Swendy.elsasser@arm.com 108611120Swendy.elsasser@arm.com # depending on frequency, bank groups may be required 108711120Swendy.elsasser@arm.com # will always have 4 bank groups when enabled 108811120Swendy.elsasser@arm.com # current specifications do not define the minimum frequency for 108911120Swendy.elsasser@arm.com # bank group architecture 109011120Swendy.elsasser@arm.com # setting bank_groups_per_rank to 0 to disable until range is defined 109111120Swendy.elsasser@arm.com bank_groups_per_rank = 0 109211120Swendy.elsasser@arm.com 109311120Swendy.elsasser@arm.com # 500 MHz for 1Gbps DDR data rate 109411120Swendy.elsasser@arm.com tCK = '2ns' 109511120Swendy.elsasser@arm.com 109611120Swendy.elsasser@arm.com # use values from IDD measurement in JEDEC spec 109711120Swendy.elsasser@arm.com # use tRP value for tRCD and tCL similar to other classes 109811120Swendy.elsasser@arm.com tRP = '15ns' 109911120Swendy.elsasser@arm.com tRCD = '15ns' 110011120Swendy.elsasser@arm.com tCL = '15ns' 110111120Swendy.elsasser@arm.com tRAS = '33ns' 110211120Swendy.elsasser@arm.com 110311120Swendy.elsasser@arm.com # BL2 and BL4 supported, default to BL4 110411120Swendy.elsasser@arm.com # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns 110511120Swendy.elsasser@arm.com tBURST = '4ns' 110611120Swendy.elsasser@arm.com 110711120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 110811120Swendy.elsasser@arm.com tRFC = '160ns' 110911120Swendy.elsasser@arm.com 111011120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 111111120Swendy.elsasser@arm.com tREFI = '3.9us' 111211120Swendy.elsasser@arm.com 111311120Swendy.elsasser@arm.com # extrapolate the following from LPDDR configs, using ns values 111411120Swendy.elsasser@arm.com # to minimize burst length, prefetch differences 111511120Swendy.elsasser@arm.com tWR = '18ns' 111611120Swendy.elsasser@arm.com tRTP = '7.5ns' 111711120Swendy.elsasser@arm.com tWTR = '10ns' 111811120Swendy.elsasser@arm.com 111911120Swendy.elsasser@arm.com # start with 2 cycles turnaround, similar to other memory classes 112011120Swendy.elsasser@arm.com # could be more with variations across the stack 112111120Swendy.elsasser@arm.com tRTW = '4ns' 112211120Swendy.elsasser@arm.com 112311120Swendy.elsasser@arm.com # single rank device, set to 0 112411120Swendy.elsasser@arm.com tCS = '0ns' 112511120Swendy.elsasser@arm.com 112611120Swendy.elsasser@arm.com # from MemCon example, tRRD is 4ns with 2ns tCK 112711120Swendy.elsasser@arm.com tRRD = '4ns' 112811120Swendy.elsasser@arm.com 112911120Swendy.elsasser@arm.com # from MemCon example, tFAW is 30ns with 2ns tCK 113011120Swendy.elsasser@arm.com tXAW = '30ns' 113111120Swendy.elsasser@arm.com activation_limit = 4 113211120Swendy.elsasser@arm.com 113311120Swendy.elsasser@arm.com # 4tCK 113411120Swendy.elsasser@arm.com tXP = '8ns' 113511120Swendy.elsasser@arm.com 113611120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 113711120Swendy.elsasser@arm.com tXS = '168ns' 113811120Swendy.elsasser@arm.com 113911120Swendy.elsasser@arm.com# A single HBM x64 interface (one command and address bus), with 114011120Swendy.elsasser@arm.com# default timings based on HBM gen1 and data publically released 114111120Swendy.elsasser@arm.com# A 4H stack is defined, 8Gb per die for a total of 4GB of memory. 114211120Swendy.elsasser@arm.com# Note: This defines a pseudo-channel with a unique controller 114311120Swendy.elsasser@arm.com# instantiated per pseudo-channel 114411120Swendy.elsasser@arm.com# Stay at same IO rate (1Gbps) to maintain timing relationship with 114511120Swendy.elsasser@arm.com# HBM gen1 class (HBM_1000_4H_x128) where possible 114611837Swendy.elsasser@arm.comclass HBM_1000_4H_1x64(HBM_1000_4H_1x128): 114711120Swendy.elsasser@arm.com # For HBM gen2 with pseudo-channel mode, configure 2X channels. 114811120Swendy.elsasser@arm.com # Configuration defines a single pseudo channel, with the capacity 114911120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 16) based on 8Gb dies 115011120Swendy.elsasser@arm.com # To use all 16 pseudo channels, set 'channels' parameter to 16 in 115111120Swendy.elsasser@arm.com # system configuration 115211120Swendy.elsasser@arm.com 115311120Swendy.elsasser@arm.com # 64-bit pseudo-channle interface 115411120Swendy.elsasser@arm.com device_bus_width = 64 115511120Swendy.elsasser@arm.com 115611120Swendy.elsasser@arm.com # HBM pseudo-channel only supports BL4 115711120Swendy.elsasser@arm.com burst_length = 4 115811120Swendy.elsasser@arm.com 115911120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack; 116011120Swendy.elsasser@arm.com # with 16 channels, 256MB per channel 116111120Swendy.elsasser@arm.com device_size = '256MB' 116211120Swendy.elsasser@arm.com 116311120Swendy.elsasser@arm.com # page size is halved with pseudo-channel; maintaining the same same number 116411120Swendy.elsasser@arm.com # of rows per pseudo-channel with 2X banks across 2 channels 116511120Swendy.elsasser@arm.com device_rowbuffer_size = '1kB' 116611120Swendy.elsasser@arm.com 116711120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 116811120Swendy.elsasser@arm.com # Starting with 4Gb dies, 16 banks are defined 116911120Swendy.elsasser@arm.com banks_per_rank = 16 117011120Swendy.elsasser@arm.com 117111120Swendy.elsasser@arm.com # reset tRFC for larger, 8Gb device 117211120Swendy.elsasser@arm.com # use HBM1 4Gb value as a starting point 117311120Swendy.elsasser@arm.com tRFC = '260ns' 117411120Swendy.elsasser@arm.com 117511120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 117611120Swendy.elsasser@arm.com tXS = '268ns' 117710561SOmar.Naji@arm.com # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns 117810561SOmar.Naji@arm.com tCS = '2ns' 117910561SOmar.Naji@arm.com tREFI = '3.9us' 118011673SOmar.Naji@arm.com 118111673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 118211673SOmar.Naji@arm.com tXP = '10ns' 118311673SOmar.Naji@arm.com 118411673SOmar.Naji@arm.com # self refresh exit time 118511673SOmar.Naji@arm.com tXS = '65ns' 1186