DRAMCtrl.py revision 11674
111674SOmar.Naji@arm.com# Copyright (c) 2012-2016 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 1410864Sjungma@eit.uni-kl.de# Copyright (c) 2015 University of Kaiserslautern 1511186Serfan.azarkhish@unibo.it# Copyright (c) 2015 The University of Bologna 169831SN/A# All rights reserved. 179831SN/A# 189243SN/A# Redistribution and use in source and binary forms, with or without 199243SN/A# modification, are permitted provided that the following conditions are 209243SN/A# met: redistributions of source code must retain the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer; 229243SN/A# redistributions in binary form must reproduce the above copyright 239243SN/A# notice, this list of conditions and the following disclaimer in the 249243SN/A# documentation and/or other materials provided with the distribution; 259243SN/A# neither the name of the copyright holders nor the names of its 269243SN/A# contributors may be used to endorse or promote products derived from 279243SN/A# this software without specific prior written permission. 289243SN/A# 299243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 309243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 319243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 329243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 339243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 349243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 359243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 369243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 379243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 389243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 399243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 409243SN/A# 419243SN/A# Authors: Andreas Hansson 429243SN/A# Ani Udipi 4310864Sjungma@eit.uni-kl.de# Omar Naji 4410864Sjungma@eit.uni-kl.de# Matthias Jung 4511186Serfan.azarkhish@unibo.it# Erfan Azarkhish 469243SN/A 479243SN/Afrom m5.params import * 489243SN/Afrom AbstractMemory import * 499243SN/A 509243SN/A# Enum for memory scheduling algorithms, currently First-Come 519243SN/A# First-Served and a First-Row Hit then First-Come First-Served 529243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 539243SN/A 5410136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5510136SN/A# channel, rank, bank, row and column, respectively, and going from 5610136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5710136SN/A# suitable for an open-page policy, optimising for sequential accesses 5810136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5910136SN/A# maximises parallelism. 6010136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 619243SN/A 6210144SN/A# Enum for the page policy, either open, open_adaptive, close, or 6310144SN/A# close_adaptive. 6410144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6510144SN/A 'close_adaptive'] 669243SN/A 6710146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 689243SN/A# that aims to model the most important system-level performance 699243SN/A# effects of a DRAM without getting into too much detail of the DRAM 709243SN/A# itself. 7110146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 7210146Sandreas.hansson@arm.com type = 'DRAMCtrl' 7310146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 749243SN/A 759243SN/A # single-ported on the system interface side, instantiate with a 769243SN/A # bus in front of the controller for multiple ports 779243SN/A port = SlavePort("Slave port") 789243SN/A 7910536Sandreas.hansson@arm.com # the basic configuration of the controller architecture, note 8010536Sandreas.hansson@arm.com # that each entry corresponds to a burst for the specific DRAM 8110536Sandreas.hansson@arm.com # configuration (e.g. x32 with burst length 8 is 32 bytes) and not 8210536Sandreas.hansson@arm.com # the cacheline size or request/packet size 8310145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 849972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 859243SN/A 8610140SN/A # threshold in percent for when to forcefully trigger writes and 8710140SN/A # start emptying the write buffer 8810140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 899972SN/A 9010140SN/A # threshold in percentage for when to start writes if the read 9110140SN/A # queue is empty 9210140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 9310140SN/A 9410140SN/A # minimum write bursts to schedule before switching back to reads 9510140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 9610140SN/A "switching to reads") 979243SN/A 989243SN/A # scheduler, address map and page policy 999489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 10010675Sandreas.hansson@arm.com addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy") 10110145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 1029243SN/A 10310141SN/A # enforce a limit on the number of accesses per row 10410141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 10510141SN/A "closing"); 10610141SN/A 10710489SOmar.Naji@arm.com # size of DRAM Chip in Bytes 10810489SOmar.Naji@arm.com device_size = Param.MemorySize("Size of DRAM chip") 10910489SOmar.Naji@arm.com 1109726SN/A # pipeline latency of the controller and PHY, split into a 1119726SN/A # frontend part and a backend part, with reads and writes serviced 1129726SN/A # by the queues only seeing the frontend contribution, and reads 1139726SN/A # serviced by the memory seeing the sum of the two 1149726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1159726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1169726SN/A 1179489SN/A # the physical organisation of the DRAM 1189831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1199831SN/A "device/chip") 1209831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1219831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1229831SN/A "device/chip") 1239831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1249489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 12510394Swendy.elsasser@arm.com 12610394Swendy.elsasser@arm.com # default to 0 bank groups per rank, indicating bank group architecture 12710394Swendy.elsasser@arm.com # is not used 12810394Swendy.elsasser@arm.com # update per memory class when bank group architecture is supported 12910394Swendy.elsasser@arm.com bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1309489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1319566SN/A # only used for the address mapping as the controller by 1329566SN/A # construction is a single channel and multiple controllers have 1339566SN/A # to be instantiated for a multi-channel configuration 1349566SN/A channels = Param.Unsigned(1, "Number of channels") 1359489SN/A 13610430SOmar.Naji@arm.com # For power modelling we need to know if the DRAM has a DLL or not 13710430SOmar.Naji@arm.com dll = Param.Bool(True, "DRAM has DLL or not") 13810430SOmar.Naji@arm.com 13910430SOmar.Naji@arm.com # DRAMPower provides in addition to the core power, the possibility to 14010430SOmar.Naji@arm.com # include RD/WR termination and IO power. This calculation assumes some 14110430SOmar.Naji@arm.com # default values. The integration of DRAMPower with gem5 does not include 14210430SOmar.Naji@arm.com # IO and RD/WR termination power by default. This might be added as an 14310430SOmar.Naji@arm.com # additional feature in the future. 14410430SOmar.Naji@arm.com 1459243SN/A # timing behaviour and constraints - all in nanoseconds 1469243SN/A 14710216Sandreas.hansson@arm.com # the base clock period of the DRAM 14810216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 14910216Sandreas.hansson@arm.com 1509243SN/A # the amount of time in nanoseconds from issuing an activate command 1519243SN/A # to the data being available in the row buffer for a read/write 1529489SN/A tRCD = Param.Latency("RAS to CAS delay") 1539243SN/A 1549243SN/A # the time from issuing a read/write command to seeing the actual data 1559489SN/A tCL = Param.Latency("CAS latency") 1569243SN/A 1579243SN/A # minimum time between a precharge and subsequent activate 1589489SN/A tRP = Param.Latency("Row precharge time") 1599243SN/A 1609963SN/A # minimum time between an activate and a precharge to the same row 1619963SN/A tRAS = Param.Latency("ACT to PRE delay") 1629963SN/A 16310210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 16410210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 16510210Sandreas.hansson@arm.com 16610212Sandreas.hansson@arm.com # minimum time between a read and precharge command 16710212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 16810212Sandreas.hansson@arm.com 1699243SN/A # time to complete a burst transfer, typically the burst length 1709243SN/A # divided by two due to the DDR bus, but by making it a parameter 1719243SN/A # it is easier to also evaluate SDR memories like WideIO. 1729831SN/A # This parameter has to account for burst length. 1739831SN/A # Read/Write requests with data size larger than one full burst are broken 17410146Sandreas.hansson@arm.com # down into multiple requests in the controller 17510394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 17610394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 17710394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 1789489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1799243SN/A 18010394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 18110394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 18210394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 18310394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 18410394Swendy.elsasser@arm.com tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 18510394Swendy.elsasser@arm.com 1869243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1879489SN/A tRFC = Param.Latency("Refresh cycle time") 1889243SN/A 1899243SN/A # refresh command interval, how often a "ref" command needs 1909243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1919489SN/A tREFI = Param.Latency("Refresh command interval") 1929243SN/A 19310393Swendy.elsasser@arm.com # write-to-read, same rank turnaround penalty 19410393Swendy.elsasser@arm.com tWTR = Param.Latency("Write to read, same rank switching time") 1959243SN/A 19610393Swendy.elsasser@arm.com # read-to-write, same rank turnaround penalty 19710393Swendy.elsasser@arm.com tRTW = Param.Latency("Read to write, same rank switching time") 19810393Swendy.elsasser@arm.com 19910393Swendy.elsasser@arm.com # rank-to-rank bus delay penalty 20010393Swendy.elsasser@arm.com # this does not correlate to a memory timing parameter and encompasses: 20110393Swendy.elsasser@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 20210393Swendy.elsasser@arm.com # different rank bus delay 20310393Swendy.elsasser@arm.com tCS = Param.Latency("Rank to rank switching time") 20410206Sandreas.hansson@arm.com 2059971SN/A # minimum row activate to row activate delay time 2069971SN/A tRRD = Param.Latency("ACT to ACT delay") 2079971SN/A 20810394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 20910394Swendy.elsasser@arm.com tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 21010394Swendy.elsasser@arm.com 2119488SN/A # time window in which a maximum number of activates are allowed 2129488SN/A # to take place, set to 0 to disable 2139489SN/A tXAW = Param.Latency("X activation window") 2149489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 2159488SN/A 21610430SOmar.Naji@arm.com # time to exit power-down mode 21710430SOmar.Naji@arm.com # Exit power-down to next valid command delay 21810430SOmar.Naji@arm.com tXP = Param.Latency("0ns", "Power-up Delay") 21910430SOmar.Naji@arm.com 22010430SOmar.Naji@arm.com # Exit Powerdown to commands requiring a locked DLL 22110430SOmar.Naji@arm.com tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL") 22210430SOmar.Naji@arm.com 22310430SOmar.Naji@arm.com # time to exit self-refresh mode 22410430SOmar.Naji@arm.com tXS = Param.Latency("0ns", "Self-refresh exit latency") 22510430SOmar.Naji@arm.com 22610430SOmar.Naji@arm.com # time to exit self-refresh mode with locked DLL 22710430SOmar.Naji@arm.com tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL") 22810430SOmar.Naji@arm.com 2299488SN/A # Currently rolled into other params 2309243SN/A ###################################################################### 2319243SN/A 2329963SN/A # tRC - assumed to be tRAS + tRP 2339243SN/A 23410430SOmar.Naji@arm.com # Power Behaviour and Constraints 23510430SOmar.Naji@arm.com # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are 23610430SOmar.Naji@arm.com # defined as VDD and VDD2. Each current is defined for each voltage domain 23710430SOmar.Naji@arm.com # separately. For example, current IDD0 is active-precharge current for 23810430SOmar.Naji@arm.com # voltage domain VDD and current IDD02 is active-precharge current for 23910430SOmar.Naji@arm.com # voltage domain VDD2. 24010430SOmar.Naji@arm.com # By default all currents are set to 0mA. Users who are only interested in 24110430SOmar.Naji@arm.com # the performance of DRAMs can leave them at 0. 24210430SOmar.Naji@arm.com 24310430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current 24410430SOmar.Naji@arm.com IDD0 = Param.Current("0mA", "Active precharge current") 24510430SOmar.Naji@arm.com 24610430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current multiple voltage Range 24710430SOmar.Naji@arm.com IDD02 = Param.Current("0mA", "Active precharge current VDD2") 24810430SOmar.Naji@arm.com 24910430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit 25010430SOmar.Naji@arm.com IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow") 25110430SOmar.Naji@arm.com 25210430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit multiple voltage Range 25310430SOmar.Naji@arm.com IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2") 25410430SOmar.Naji@arm.com 25510430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit 25610430SOmar.Naji@arm.com IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast") 25710430SOmar.Naji@arm.com 25810430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit multiple voltage Range 25910430SOmar.Naji@arm.com IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2") 26010430SOmar.Naji@arm.com 26110430SOmar.Naji@arm.com # Precharge Standby current 26210430SOmar.Naji@arm.com IDD2N = Param.Current("0mA", "Precharge Standby current") 26310430SOmar.Naji@arm.com 26410430SOmar.Naji@arm.com # Precharge Standby current multiple voltage range 26510430SOmar.Naji@arm.com IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2") 26610430SOmar.Naji@arm.com 26710430SOmar.Naji@arm.com # Active Power-down current: slow exit 26810430SOmar.Naji@arm.com IDD3P0 = Param.Current("0mA", "Active Powerdown slow") 26910430SOmar.Naji@arm.com 27010430SOmar.Naji@arm.com # Active Power-down current: slow exit multiple voltage range 27110430SOmar.Naji@arm.com IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2") 27210430SOmar.Naji@arm.com 27310430SOmar.Naji@arm.com # Active Power-down current : fast exit 27410430SOmar.Naji@arm.com IDD3P1 = Param.Current("0mA", "Active Powerdown fast") 27510430SOmar.Naji@arm.com 27610430SOmar.Naji@arm.com # Active Power-down current : fast exit multiple voltage range 27710430SOmar.Naji@arm.com IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2") 27810430SOmar.Naji@arm.com 27910430SOmar.Naji@arm.com # Active Standby current 28010430SOmar.Naji@arm.com IDD3N = Param.Current("0mA", "Active Standby current") 28110430SOmar.Naji@arm.com 28210430SOmar.Naji@arm.com # Active Standby current multiple voltage range 28310430SOmar.Naji@arm.com IDD3N2 = Param.Current("0mA", "Active Standby current VDD2") 28410430SOmar.Naji@arm.com 28510430SOmar.Naji@arm.com # Burst Read Operating Current 28610430SOmar.Naji@arm.com IDD4R = Param.Current("0mA", "READ current") 28710430SOmar.Naji@arm.com 28810430SOmar.Naji@arm.com # Burst Read Operating Current multiple voltage range 28910430SOmar.Naji@arm.com IDD4R2 = Param.Current("0mA", "READ current VDD2") 29010430SOmar.Naji@arm.com 29110430SOmar.Naji@arm.com # Burst Write Operating Current 29210430SOmar.Naji@arm.com IDD4W = Param.Current("0mA", "WRITE current") 29310430SOmar.Naji@arm.com 29410430SOmar.Naji@arm.com # Burst Write Operating Current multiple voltage range 29510430SOmar.Naji@arm.com IDD4W2 = Param.Current("0mA", "WRITE current VDD2") 29610430SOmar.Naji@arm.com 29710430SOmar.Naji@arm.com # Refresh Current 29810430SOmar.Naji@arm.com IDD5 = Param.Current("0mA", "Refresh current") 29910430SOmar.Naji@arm.com 30010430SOmar.Naji@arm.com # Refresh Current multiple voltage range 30110430SOmar.Naji@arm.com IDD52 = Param.Current("0mA", "Refresh current VDD2") 30210430SOmar.Naji@arm.com 30310430SOmar.Naji@arm.com # Self-Refresh Current 30410430SOmar.Naji@arm.com IDD6 = Param.Current("0mA", "Self-refresh Current") 30510430SOmar.Naji@arm.com 30610430SOmar.Naji@arm.com # Self-Refresh Current multiple voltage range 30710430SOmar.Naji@arm.com IDD62 = Param.Current("0mA", "Self-refresh Current VDD2") 30810430SOmar.Naji@arm.com 30910430SOmar.Naji@arm.com # Main voltage range of the DRAM 31010430SOmar.Naji@arm.com VDD = Param.Voltage("0V", "Main Voltage Range") 31110430SOmar.Naji@arm.com 31210430SOmar.Naji@arm.com # Second voltage range defined by some DRAMs 31310430SOmar.Naji@arm.com VDD2 = Param.Voltage("0V", "2nd Voltage Range") 31410430SOmar.Naji@arm.com 31510217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 31610217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 31710430SOmar.Naji@arm.com# an 8x8 configuration. 31810146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 31910489SOmar.Naji@arm.com # size of device in bytes 32010489SOmar.Naji@arm.com device_size = '512MB' 32110489SOmar.Naji@arm.com 3229831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 3239831SN/A device_bus_width = 8 3249831SN/A 3259831SN/A # DDR3 is a BL8 device 3269831SN/A burst_length = 8 3279831SN/A 32810217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 3299831SN/A device_rowbuffer_size = '1kB' 3309831SN/A 3319831SN/A # 8x8 configuration, so 8 devices 3329831SN/A devices_per_rank = 8 3339489SN/A 3349489SN/A # Use two ranks 3359489SN/A ranks_per_channel = 2 3369489SN/A 3379489SN/A # DDR3 has 8 banks in all configurations 3389489SN/A banks_per_rank = 8 3399489SN/A 34010216Sandreas.hansson@arm.com # 800 MHz 34110216Sandreas.hansson@arm.com tCK = '1.25ns' 34210216Sandreas.hansson@arm.com 34310217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 34410217Sandreas.hansson@arm.com tBURST = '5ns' 34510217Sandreas.hansson@arm.com 34610217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 3479489SN/A tRCD = '13.75ns' 3489489SN/A tCL = '13.75ns' 3499489SN/A tRP = '13.75ns' 3509970SN/A tRAS = '35ns' 35110217Sandreas.hansson@arm.com tRRD = '6ns' 35210217Sandreas.hansson@arm.com tXAW = '30ns' 35310217Sandreas.hansson@arm.com activation_limit = 4 35410217Sandreas.hansson@arm.com tRFC = '260ns' 35510217Sandreas.hansson@arm.com 35610210Sandreas.hansson@arm.com tWR = '15ns' 35710217Sandreas.hansson@arm.com 35810217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 35910217Sandreas.hansson@arm.com tWTR = '7.5ns' 36010217Sandreas.hansson@arm.com 36110217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 36210212Sandreas.hansson@arm.com tRTP = '7.5ns' 3639489SN/A 36410393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 36510206Sandreas.hansson@arm.com tRTW = '2.5ns' 36610206Sandreas.hansson@arm.com 36710393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 36810393Swendy.elsasser@arm.com tCS = '2.5ns' 36910393Swendy.elsasser@arm.com 37010217Sandreas.hansson@arm.com # <=85C, half for >85C 37110217Sandreas.hansson@arm.com tREFI = '7.8us' 3729971SN/A 37311673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 37411673SOmar.Naji@arm.com tXP = '6ns' 37511673SOmar.Naji@arm.com 37611673SOmar.Naji@arm.com # self refresh exit time 37711673SOmar.Naji@arm.com tXS = '270ns' 37811673SOmar.Naji@arm.com 37911674SOmar.Naji@arm.com # Current values from datasheet Die Rev E,J 38011674SOmar.Naji@arm.com IDD0 = '55mA' 38111674SOmar.Naji@arm.com IDD2N = '32mA' 38211674SOmar.Naji@arm.com IDD3N = '38mA' 38311674SOmar.Naji@arm.com IDD4W = '125mA' 38411674SOmar.Naji@arm.com IDD4R = '157mA' 38511674SOmar.Naji@arm.com IDD5 = '235mA' 38610430SOmar.Naji@arm.com VDD = '1.5V' 38710430SOmar.Naji@arm.com 38810864Sjungma@eit.uni-kl.de# A single HMC-2500 x32 model based on: 38910864Sjungma@eit.uni-kl.de# [1] DRAMSpec: a high-level DRAM bank modelling tool 39010864Sjungma@eit.uni-kl.de# developed at the University of Kaiserslautern. This high level tool 39110864Sjungma@eit.uni-kl.de# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to 39210864Sjungma@eit.uni-kl.de# estimate the DRAM bank latency and power numbers. 39311186Serfan.azarkhish@unibo.it# [2] High performance AXI-4.0 based interconnect for extensible smart memory 39411186Serfan.azarkhish@unibo.it# cubes (E. Azarkhish et. al) 39510864Sjungma@eit.uni-kl.de# Assumed for the HMC model is a 30 nm technology node. 39610864Sjungma@eit.uni-kl.de# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4 39710864Sjungma@eit.uni-kl.de# layers). 39810864Sjungma@eit.uni-kl.de# Each layer has 16 vaults and each vault consists of 2 banks per layer. 39910864Sjungma@eit.uni-kl.de# In order to be able to use the same controller used for 2D DRAM generations 40010864Sjungma@eit.uni-kl.de# for HMC, the following analogy is done: 40110864Sjungma@eit.uni-kl.de# Channel (DDR) => Vault (HMC) 40210864Sjungma@eit.uni-kl.de# device_size (DDR) => size of a single layer in a vault 40310864Sjungma@eit.uni-kl.de# ranks per channel (DDR) => number of layers 40410864Sjungma@eit.uni-kl.de# banks per rank (DDR) => banks per layer 40510864Sjungma@eit.uni-kl.de# devices per rank (DDR) => devices per layer ( 1 for HMC). 40610864Sjungma@eit.uni-kl.de# The parameters for which no input is available are inherited from the DDR3 40710864Sjungma@eit.uni-kl.de# configuration. 40811186Serfan.azarkhish@unibo.it# This configuration includes the latencies from the DRAM to the logic layer 40911186Serfan.azarkhish@unibo.it# of the HMC 41010864Sjungma@eit.uni-kl.declass HMC_2500_x32(DDR3_1600_x64): 41110864Sjungma@eit.uni-kl.de # size of device 41210864Sjungma@eit.uni-kl.de # two banks per device with each bank 4MB [2] 41310864Sjungma@eit.uni-kl.de device_size = '8MB' 41410864Sjungma@eit.uni-kl.de 41510864Sjungma@eit.uni-kl.de # 1x32 configuration, 1 device with 32 TSVs [2] 41610864Sjungma@eit.uni-kl.de device_bus_width = 32 41710864Sjungma@eit.uni-kl.de 41810864Sjungma@eit.uni-kl.de # HMC is a BL8 device [2] 41910864Sjungma@eit.uni-kl.de burst_length = 8 42010864Sjungma@eit.uni-kl.de 42110864Sjungma@eit.uni-kl.de # Each device has a page (row buffer) size of 256 bytes [2] 42210864Sjungma@eit.uni-kl.de device_rowbuffer_size = '256B' 42310864Sjungma@eit.uni-kl.de 42410864Sjungma@eit.uni-kl.de # 1x32 configuration, so 1 device [2] 42510864Sjungma@eit.uni-kl.de devices_per_rank = 1 42610864Sjungma@eit.uni-kl.de 42710864Sjungma@eit.uni-kl.de # 4 layers so 4 ranks [2] 42810864Sjungma@eit.uni-kl.de ranks_per_channel = 4 42910864Sjungma@eit.uni-kl.de 43010864Sjungma@eit.uni-kl.de # HMC has 2 banks per layer [2] 43110864Sjungma@eit.uni-kl.de # Each layer represents a rank. With 4 layers and 8 banks in total, each 43210864Sjungma@eit.uni-kl.de # layer has 2 banks; thus 2 banks per rank. 43310864Sjungma@eit.uni-kl.de banks_per_rank = 2 43410864Sjungma@eit.uni-kl.de 43510864Sjungma@eit.uni-kl.de # 1250 MHz [2] 43610864Sjungma@eit.uni-kl.de tCK = '0.8ns' 43710864Sjungma@eit.uni-kl.de 43810864Sjungma@eit.uni-kl.de # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz 43910864Sjungma@eit.uni-kl.de tBURST = '3.2ns' 44010864Sjungma@eit.uni-kl.de 44110864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 44210864Sjungma@eit.uni-kl.de tRCD = '10.2ns' 44310864Sjungma@eit.uni-kl.de tCL = '9.9ns' 44410864Sjungma@eit.uni-kl.de tRP = '7.7ns' 44510864Sjungma@eit.uni-kl.de tRAS = '21.6ns' 44610864Sjungma@eit.uni-kl.de 44710864Sjungma@eit.uni-kl.de # tRRD depends on the power supply network for each vendor. 44810864Sjungma@eit.uni-kl.de # We assume a tRRD of a double bank approach to be equal to 4 clock 44910864Sjungma@eit.uni-kl.de # cycles (Assumption) 45010864Sjungma@eit.uni-kl.de tRRD = '3.2ns' 45110864Sjungma@eit.uni-kl.de 45211186Serfan.azarkhish@unibo.it # activation limit is set to 0 since there are only 2 banks per vault 45311186Serfan.azarkhish@unibo.it # layer. 45410864Sjungma@eit.uni-kl.de activation_limit = 0 45510864Sjungma@eit.uni-kl.de 45610864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 45710864Sjungma@eit.uni-kl.de tRFC = '59ns' 45810864Sjungma@eit.uni-kl.de tWR = '8ns' 45910864Sjungma@eit.uni-kl.de tRTP = '4.9ns' 46010864Sjungma@eit.uni-kl.de 46111186Serfan.azarkhish@unibo.it # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 46211186Serfan.azarkhish@unibo.it # 0.8 ns (Assumption) 46310864Sjungma@eit.uni-kl.de tCS = '0.8ns' 46410864Sjungma@eit.uni-kl.de 46510864Sjungma@eit.uni-kl.de # Value using DRAMSpec HMC model [1] 46610864Sjungma@eit.uni-kl.de tREFI = '3.9us' 46710864Sjungma@eit.uni-kl.de 46811186Serfan.azarkhish@unibo.it # The default page policy in the vault controllers is simple closed page 46911186Serfan.azarkhish@unibo.it # [2] nevertheless 'close' policy opens and closes the row multiple times 47011186Serfan.azarkhish@unibo.it # for bursts largers than 32Bytes. For this reason we use 'close_adaptive' 47111186Serfan.azarkhish@unibo.it page_policy = 'close_adaptive' 47211186Serfan.azarkhish@unibo.it 47311186Serfan.azarkhish@unibo.it # RoCoRaBaCh resembles the default address mapping in HMC 47410864Sjungma@eit.uni-kl.de addr_mapping = 'RoCoRaBaCh' 47510864Sjungma@eit.uni-kl.de min_writes_per_switch = 8 47610864Sjungma@eit.uni-kl.de 47711186Serfan.azarkhish@unibo.it # These parameters do not directly correlate with buffer_size in real 47811186Serfan.azarkhish@unibo.it # hardware. Nevertheless, their value has been tuned to achieve a 47911186Serfan.azarkhish@unibo.it # bandwidth similar to the cycle-accurate model in [2] 48011186Serfan.azarkhish@unibo.it write_buffer_size = 32 48111186Serfan.azarkhish@unibo.it read_buffer_size = 32 48211186Serfan.azarkhish@unibo.it 48311186Serfan.azarkhish@unibo.it # The static latency of the vault controllers is estimated to be smaller 48411186Serfan.azarkhish@unibo.it # than a full DRAM channel controller 48511186Serfan.azarkhish@unibo.it static_backend_latency='4ns' 48611186Serfan.azarkhish@unibo.it static_frontend_latency='4ns' 48711186Serfan.azarkhish@unibo.it 48810217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 48910217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 49010217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 49110217Sandreas.hansson@arm.com# consistent across the two configurations. 49210217Sandreas.hansson@arm.comclass DDR3_2133_x64(DDR3_1600_x64): 49310217Sandreas.hansson@arm.com # 1066 MHz 49410217Sandreas.hansson@arm.com tCK = '0.938ns' 49510217Sandreas.hansson@arm.com 49610217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 49710217Sandreas.hansson@arm.com tBURST = '3.752ns' 49810217Sandreas.hansson@arm.com 49910217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 50010217Sandreas.hansson@arm.com tRCD = '13.09ns' 50110217Sandreas.hansson@arm.com tCL = '13.09ns' 50210217Sandreas.hansson@arm.com tRP = '13.09ns' 50310217Sandreas.hansson@arm.com tRAS = '33ns' 50410217Sandreas.hansson@arm.com tRRD = '5ns' 50510217Sandreas.hansson@arm.com tXAW = '25ns' 50610217Sandreas.hansson@arm.com 50710430SOmar.Naji@arm.com # Current values from datasheet 50810430SOmar.Naji@arm.com IDD0 = '70mA' 50910430SOmar.Naji@arm.com IDD2N = '37mA' 51010430SOmar.Naji@arm.com IDD3N = '44mA' 51110430SOmar.Naji@arm.com IDD4W = '157mA' 51210430SOmar.Naji@arm.com IDD4R = '191mA' 51310430SOmar.Naji@arm.com IDD5 = '250mA' 51410430SOmar.Naji@arm.com VDD = '1.5V' 51510430SOmar.Naji@arm.com 51610217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 51711672SOmar.Naji@arm.com# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M16) 51811672SOmar.Naji@arm.com# in an 4x16 configuration. 51910217Sandreas.hansson@arm.comclass DDR4_2400_x64(DRAMCtrl): 52010489SOmar.Naji@arm.com # size of device 52110489SOmar.Naji@arm.com device_size = '512MB' 52210489SOmar.Naji@arm.com 52311672SOmar.Naji@arm.com # 4x16 configuration, 4 devices each with an 16-bit interface 52411672SOmar.Naji@arm.com device_bus_width = 16 52510217Sandreas.hansson@arm.com 52610217Sandreas.hansson@arm.com # DDR4 is a BL8 device 52710217Sandreas.hansson@arm.com burst_length = 8 52810217Sandreas.hansson@arm.com 52911672SOmar.Naji@arm.com # Each device has a page (row buffer) size of 2 Kbyte (1K columns x16) 53011672SOmar.Naji@arm.com device_rowbuffer_size = '2kB' 53110217Sandreas.hansson@arm.com 53211672SOmar.Naji@arm.com # 4x16 configuration, so 4 devices 53311672SOmar.Naji@arm.com devices_per_rank = 4 53410217Sandreas.hansson@arm.com 53510430SOmar.Naji@arm.com # Match our DDR3 configurations which is dual rank 53610430SOmar.Naji@arm.com ranks_per_channel = 2 53710217Sandreas.hansson@arm.com 53810394Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 53911672SOmar.Naji@arm.com # Set to 2 for x16 case 54011672SOmar.Naji@arm.com bank_groups_per_rank = 2 54110394Swendy.elsasser@arm.com 54211672SOmar.Naji@arm.com # DDR4 has 16 banks(x4,x8) and 8 banks(x16) (4 bank groups in all 54311672SOmar.Naji@arm.com # configurations). Currently we do not capture the additional 54410217Sandreas.hansson@arm.com # constraints incurred by the bank groups 54511672SOmar.Naji@arm.com banks_per_rank = 8 54610217Sandreas.hansson@arm.com 54710891Sandreas.hansson@arm.com # override the default buffer sizes and go for something larger to 54810891Sandreas.hansson@arm.com # accommodate the larger bank count 54910891Sandreas.hansson@arm.com write_buffer_size = 128 55010891Sandreas.hansson@arm.com read_buffer_size = 64 55110891Sandreas.hansson@arm.com 55210217Sandreas.hansson@arm.com # 1200 MHz 55310217Sandreas.hansson@arm.com tCK = '0.833ns' 55410217Sandreas.hansson@arm.com 55510217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 55610394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 55710394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 55810394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 55910217Sandreas.hansson@arm.com tBURST = '3.333ns' 56010217Sandreas.hansson@arm.com 56110394Swendy.elsasser@arm.com # @2400 data rate, tCCD_L is 6 CK 56210394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 56310394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 56410394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 56510394Swendy.elsasser@arm.com tCCD_L = '5ns'; 56610394Swendy.elsasser@arm.com 56711672SOmar.Naji@arm.com # DDR4-2400 16-16-16 56811672SOmar.Naji@arm.com tRCD = '13.32ns' 56911672SOmar.Naji@arm.com tCL = '13.32ns' 57011672SOmar.Naji@arm.com tRP = '13.32ns' 57111672SOmar.Naji@arm.com tRAS = '35ns' 57210217Sandreas.hansson@arm.com 57311672SOmar.Naji@arm.com # RRD_S (different bank group) for 2K page is MAX(4 CK, 5.3ns) 57411672SOmar.Naji@arm.com tRRD = '5.3ns' 57510394Swendy.elsasser@arm.com 57611672SOmar.Naji@arm.com # RRD_L (same bank group) for 2K page is MAX(4 CK, 6.4ns) 57711672SOmar.Naji@arm.com tRRD_L = '6.4ns'; 57810394Swendy.elsasser@arm.com 57911672SOmar.Naji@arm.com tXAW = '30ns' 5809489SN/A activation_limit = 4 58111672SOmar.Naji@arm.com tRFC = '260ns' 5829489SN/A 58310217Sandreas.hansson@arm.com tWR = '15ns' 58410217Sandreas.hansson@arm.com 58510217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 58610217Sandreas.hansson@arm.com tWTR = '5ns' 58710217Sandreas.hansson@arm.com 58810217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 58910217Sandreas.hansson@arm.com tRTP = '7.5ns' 59010217Sandreas.hansson@arm.com 59110393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 59210217Sandreas.hansson@arm.com tRTW = '1.666ns' 59310217Sandreas.hansson@arm.com 59410393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 59510393Swendy.elsasser@arm.com tCS = '1.666ns' 59610393Swendy.elsasser@arm.com 59710217Sandreas.hansson@arm.com # <=85C, half for >85C 59810217Sandreas.hansson@arm.com tREFI = '7.8us' 5999489SN/A 60011673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 60111673SOmar.Naji@arm.com tXP = '6ns' 60211673SOmar.Naji@arm.com 60311673SOmar.Naji@arm.com # self refresh exit time 60411673SOmar.Naji@arm.com tXS = '120ns' 60511673SOmar.Naji@arm.com 60610430SOmar.Naji@arm.com # Current values from datasheet 60711672SOmar.Naji@arm.com IDD0 = '70mA' 60811672SOmar.Naji@arm.com IDD02 = '4.6mA' 60910430SOmar.Naji@arm.com IDD2N = '50mA' 61010430SOmar.Naji@arm.com IDD3N = '67mA' 61110430SOmar.Naji@arm.com IDD3N2 = '3mA' 61211672SOmar.Naji@arm.com IDD4W = '302mA' 61311672SOmar.Naji@arm.com IDD4R = '230mA' 61410430SOmar.Naji@arm.com IDD5 = '192mA' 61510430SOmar.Naji@arm.com VDD = '1.2V' 61610430SOmar.Naji@arm.com VDD2 = '2.5V' 61710430SOmar.Naji@arm.com 6189728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 61910430SOmar.Naji@arm.com# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 62010430SOmar.Naji@arm.com# in a 1x32 configuration. 62110146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 62210430SOmar.Naji@arm.com # No DLL in LPDDR2 62310430SOmar.Naji@arm.com dll = False 62410430SOmar.Naji@arm.com 62510489SOmar.Naji@arm.com # size of device 62610489SOmar.Naji@arm.com device_size = '512MB' 62710489SOmar.Naji@arm.com 6289831SN/A # 1x32 configuration, 1 device with a 32-bit interface 6299831SN/A device_bus_width = 32 6309831SN/A 6319831SN/A # LPDDR2_S4 is a BL4 and BL8 device 6329831SN/A burst_length = 8 6339831SN/A 6349831SN/A # Each device has a page (row buffer) size of 1KB 6359831SN/A # (this depends on the memory density) 6369831SN/A device_rowbuffer_size = '1kB' 6379831SN/A 6389831SN/A # 1x32 configuration, so 1 device 6399831SN/A devices_per_rank = 1 6409489SN/A 6419708SN/A # Use a single rank 6429708SN/A ranks_per_channel = 1 6439489SN/A 6449489SN/A # LPDDR2-S4 has 8 banks in all configurations 6459489SN/A banks_per_rank = 8 6469489SN/A 64710216Sandreas.hansson@arm.com # 533 MHz 64810216Sandreas.hansson@arm.com tCK = '1.876ns' 64910216Sandreas.hansson@arm.com 6509489SN/A # Fixed at 15 ns 6519489SN/A tRCD = '15ns' 6529489SN/A 6539489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 6549489SN/A tCL = '15ns' 6559489SN/A 6569728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 6579728SN/A tRP = '15ns' 6589489SN/A 6599970SN/A tRAS = '42ns' 66010210Sandreas.hansson@arm.com tWR = '15ns' 6619963SN/A 66210430SOmar.Naji@arm.com tRTP = '7.5ns' 66310212Sandreas.hansson@arm.com 6649831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 6659831SN/A # Note this is a BL8 DDR device. 6669831SN/A # Requests larger than 32 bytes are broken down into multiple requests 66710146Sandreas.hansson@arm.com # in the controller 6689831SN/A tBURST = '7.5ns' 6699489SN/A 6709708SN/A # LPDDR2-S4, 4 Gbit 6719489SN/A tRFC = '130ns' 6729489SN/A tREFI = '3.9us' 6739489SN/A 67411673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 67511673SOmar.Naji@arm.com tXP = '7.5ns' 67611673SOmar.Naji@arm.com 67711673SOmar.Naji@arm.com # self refresh exit time 67811673SOmar.Naji@arm.com tXS = '140ns' 67911673SOmar.Naji@arm.com 6809489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 6819489SN/A tWTR = '7.5ns' 6829489SN/A 68310393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 68410206Sandreas.hansson@arm.com tRTW = '3.75ns' 68510206Sandreas.hansson@arm.com 68610393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 68710393Swendy.elsasser@arm.com tCS = '3.75ns' 68810393Swendy.elsasser@arm.com 6899971SN/A # Activate to activate irrespective of density and speed grade 6909971SN/A tRRD = '10.0ns' 6919971SN/A 6929708SN/A # Irrespective of density, tFAW is 50 ns 6939489SN/A tXAW = '50ns' 6949489SN/A activation_limit = 4 6959664SN/A 69610430SOmar.Naji@arm.com # Current values from datasheet 69710430SOmar.Naji@arm.com IDD0 = '15mA' 69810430SOmar.Naji@arm.com IDD02 = '70mA' 69910430SOmar.Naji@arm.com IDD2N = '2mA' 70010430SOmar.Naji@arm.com IDD2N2 = '30mA' 70110430SOmar.Naji@arm.com IDD3N = '2.5mA' 70210430SOmar.Naji@arm.com IDD3N2 = '30mA' 70310430SOmar.Naji@arm.com IDD4W = '10mA' 70410430SOmar.Naji@arm.com IDD4W2 = '190mA' 70510430SOmar.Naji@arm.com IDD4R = '3mA' 70610430SOmar.Naji@arm.com IDD4R2 = '220mA' 70710430SOmar.Naji@arm.com IDD5 = '40mA' 70810430SOmar.Naji@arm.com IDD52 = '150mA' 70910430SOmar.Naji@arm.com VDD = '1.8V' 71010430SOmar.Naji@arm.com VDD2 = '1.2V' 71110430SOmar.Naji@arm.com 7129728SN/A# A single WideIO x128 interface (one command and address bus), with 7139728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 71410146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 71510430SOmar.Naji@arm.com # No DLL for WideIO 71610430SOmar.Naji@arm.com dll = False 71710430SOmar.Naji@arm.com 71810489SOmar.Naji@arm.com # size of device 71910489SOmar.Naji@arm.com device_size = '1024MB' 72010489SOmar.Naji@arm.com 7219831SN/A # 1x128 configuration, 1 device with a 128-bit interface 7229831SN/A device_bus_width = 128 7239831SN/A 7249831SN/A # This is a BL4 device 7259831SN/A burst_length = 4 7269831SN/A 7279831SN/A # Each device has a page (row buffer) size of 4KB 7289831SN/A # (this depends on the memory density) 7299831SN/A device_rowbuffer_size = '4kB' 7309831SN/A 7319831SN/A # 1x128 configuration, so 1 device 7329831SN/A devices_per_rank = 1 7339664SN/A 7349664SN/A # Use one rank for a one-high die stack 7359664SN/A ranks_per_channel = 1 7369664SN/A 7379664SN/A # WideIO has 4 banks in all configurations 7389664SN/A banks_per_rank = 4 7399664SN/A 74010216Sandreas.hansson@arm.com # 200 MHz 74110216Sandreas.hansson@arm.com tCK = '5ns' 74210216Sandreas.hansson@arm.com 7439664SN/A # WIO-200 7449664SN/A tRCD = '18ns' 7459664SN/A tCL = '18ns' 7469664SN/A tRP = '18ns' 7479970SN/A tRAS = '42ns' 74810210Sandreas.hansson@arm.com tWR = '15ns' 74910212Sandreas.hansson@arm.com # Read to precharge is same as the burst 75010212Sandreas.hansson@arm.com tRTP = '20ns' 7519664SN/A 7529831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 7539831SN/A # Note this is a BL4 SDR device. 7549664SN/A tBURST = '20ns' 7559664SN/A 7569664SN/A # WIO 8 Gb 7579664SN/A tRFC = '210ns' 7589664SN/A 7599664SN/A # WIO 8 Gb, <=85C, half for >85C 7609664SN/A tREFI = '3.9us' 7619664SN/A 7629664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 7639664SN/A tWTR = '15ns' 7649664SN/A 76510393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 76610206Sandreas.hansson@arm.com tRTW = '10ns' 76710206Sandreas.hansson@arm.com 76810393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 76910393Swendy.elsasser@arm.com tCS = '10ns' 77010393Swendy.elsasser@arm.com 7719971SN/A # Activate to activate irrespective of density and speed grade 7729971SN/A tRRD = '10.0ns' 7739971SN/A 7749664SN/A # Two instead of four activation window 7759664SN/A tXAW = '50ns' 7769664SN/A activation_limit = 2 7779709SN/A 77810430SOmar.Naji@arm.com # The WideIO specification does not provide current information 77910430SOmar.Naji@arm.com 7809728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 78110430SOmar.Naji@arm.com# default timings based on a LPDDR3-1600 4 Gbit part (Micron 78210430SOmar.Naji@arm.com# EDF8132A1MC) in a 1x32 configuration. 78310146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 78410430SOmar.Naji@arm.com # No DLL for LPDDR3 78510430SOmar.Naji@arm.com dll = False 78610430SOmar.Naji@arm.com 78710489SOmar.Naji@arm.com # size of device 78810489SOmar.Naji@arm.com device_size = '512MB' 78910489SOmar.Naji@arm.com 7909831SN/A # 1x32 configuration, 1 device with a 32-bit interface 7919831SN/A device_bus_width = 32 7929831SN/A 7939831SN/A # LPDDR3 is a BL8 device 7949831SN/A burst_length = 8 7959831SN/A 7969976SN/A # Each device has a page (row buffer) size of 4KB 7979976SN/A device_rowbuffer_size = '4kB' 7989831SN/A 7999831SN/A # 1x32 configuration, so 1 device 8009831SN/A devices_per_rank = 1 8019709SN/A 80210430SOmar.Naji@arm.com # Technically the datasheet is a dual-rank package, but for 80310430SOmar.Naji@arm.com # comparison with the LPDDR2 config we stick to a single rank 8049709SN/A ranks_per_channel = 1 8059709SN/A 8069709SN/A # LPDDR3 has 8 banks in all configurations 8079709SN/A banks_per_rank = 8 8089709SN/A 80910216Sandreas.hansson@arm.com # 800 MHz 81010216Sandreas.hansson@arm.com tCK = '1.25ns' 81110216Sandreas.hansson@arm.com 81210430SOmar.Naji@arm.com tRCD = '18ns' 8139709SN/A 8149709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 8159709SN/A tCL = '15ns' 8169709SN/A 8179970SN/A tRAS = '42ns' 81810210Sandreas.hansson@arm.com tWR = '15ns' 8199963SN/A 82010212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 82110212Sandreas.hansson@arm.com tRTP = '7.5ns' 82210212Sandreas.hansson@arm.com 82310430SOmar.Naji@arm.com # Pre-charge one bank 18 ns (all banks 21 ns) 82410430SOmar.Naji@arm.com tRP = '18ns' 8259709SN/A 8269831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 8279831SN/A # Note this is a BL8 DDR device. 8289831SN/A # Requests larger than 32 bytes are broken down into multiple requests 82910146Sandreas.hansson@arm.com # in the controller 8309831SN/A tBURST = '5ns' 8319709SN/A 8329709SN/A # LPDDR3, 4 Gb 8339709SN/A tRFC = '130ns' 8349709SN/A tREFI = '3.9us' 8359709SN/A 83611673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 83711673SOmar.Naji@arm.com tXP = '7.5ns' 83811673SOmar.Naji@arm.com 83911673SOmar.Naji@arm.com # self refresh exit time 84011673SOmar.Naji@arm.com tXS = '140ns' 84111673SOmar.Naji@arm.com 8429709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 8439709SN/A tWTR = '7.5ns' 8449709SN/A 84510393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 84610206Sandreas.hansson@arm.com tRTW = '2.5ns' 84710206Sandreas.hansson@arm.com 84810393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 84910393Swendy.elsasser@arm.com tCS = '2.5ns' 85010393Swendy.elsasser@arm.com 8519971SN/A # Activate to activate irrespective of density and speed grade 8529971SN/A tRRD = '10.0ns' 8539971SN/A 8549709SN/A # Irrespective of size, tFAW is 50 ns 8559709SN/A tXAW = '50ns' 8569709SN/A activation_limit = 4 85710430SOmar.Naji@arm.com 85810430SOmar.Naji@arm.com # Current values from datasheet 85910430SOmar.Naji@arm.com IDD0 = '8mA' 86010430SOmar.Naji@arm.com IDD02 = '60mA' 86110430SOmar.Naji@arm.com IDD2N = '0.8mA' 86210430SOmar.Naji@arm.com IDD2N2 = '26mA' 86310430SOmar.Naji@arm.com IDD3N = '2mA' 86410430SOmar.Naji@arm.com IDD3N2 = '34mA' 86510430SOmar.Naji@arm.com IDD4W = '2mA' 86610430SOmar.Naji@arm.com IDD4W2 = '190mA' 86710430SOmar.Naji@arm.com IDD4R = '2mA' 86810430SOmar.Naji@arm.com IDD4R2 = '230mA' 86910430SOmar.Naji@arm.com IDD5 = '28mA' 87010430SOmar.Naji@arm.com IDD52 = '150mA' 87110430SOmar.Naji@arm.com VDD = '1.8V' 87210430SOmar.Naji@arm.com VDD2 = '1.2V' 87310561SOmar.Naji@arm.com 87410561SOmar.Naji@arm.com# A single GDDR5 x64 interface, with 87510561SOmar.Naji@arm.com# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix 87610561SOmar.Naji@arm.com# H5GQ1H24AFR) in a 2x32 configuration. 87710561SOmar.Naji@arm.comclass GDDR5_4000_x64(DRAMCtrl): 87810561SOmar.Naji@arm.com # size of device 87910561SOmar.Naji@arm.com device_size = '128MB' 88010561SOmar.Naji@arm.com 88110561SOmar.Naji@arm.com # 2x32 configuration, 1 device with a 32-bit interface 88210561SOmar.Naji@arm.com device_bus_width = 32 88310561SOmar.Naji@arm.com 88410561SOmar.Naji@arm.com # GDDR5 is a BL8 device 88510561SOmar.Naji@arm.com burst_length = 8 88610561SOmar.Naji@arm.com 88710561SOmar.Naji@arm.com # Each device has a page (row buffer) size of 2Kbits (256Bytes) 88810561SOmar.Naji@arm.com device_rowbuffer_size = '256B' 88910561SOmar.Naji@arm.com 89010561SOmar.Naji@arm.com # 2x32 configuration, so 2 devices 89110561SOmar.Naji@arm.com devices_per_rank = 2 89210561SOmar.Naji@arm.com 89310561SOmar.Naji@arm.com # assume single rank 89410561SOmar.Naji@arm.com ranks_per_channel = 1 89510561SOmar.Naji@arm.com 89610561SOmar.Naji@arm.com # GDDR5 has 4 bank groups 89710561SOmar.Naji@arm.com bank_groups_per_rank = 4 89810561SOmar.Naji@arm.com 89910561SOmar.Naji@arm.com # GDDR5 has 16 banks with 4 bank groups 90010561SOmar.Naji@arm.com banks_per_rank = 16 90110561SOmar.Naji@arm.com 90210561SOmar.Naji@arm.com # 1000 MHz 90310561SOmar.Naji@arm.com tCK = '1ns' 90410561SOmar.Naji@arm.com 90510561SOmar.Naji@arm.com # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz 90610561SOmar.Naji@arm.com # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz ) 90710561SOmar.Naji@arm.com # 8 beats at 4000 MHz = 2 beats at 1000 MHz 90810561SOmar.Naji@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 90910561SOmar.Naji@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 91010561SOmar.Naji@arm.com # delay for bursts to different bank groups (tCCD_S) 91110561SOmar.Naji@arm.com tBURST = '2ns' 91210561SOmar.Naji@arm.com 91310561SOmar.Naji@arm.com # @1000MHz data rate, tCCD_L is 3 CK 91410561SOmar.Naji@arm.com # CAS-to-CAS delay for bursts to the same bank group 91510561SOmar.Naji@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 91610561SOmar.Naji@arm.com # for CAS-to-CAS delay for bursts to different bank groups 91710561SOmar.Naji@arm.com tCCD_L = '3ns'; 91810561SOmar.Naji@arm.com 91910561SOmar.Naji@arm.com tRCD = '12ns' 92010561SOmar.Naji@arm.com 92110561SOmar.Naji@arm.com # tCL is not directly found in datasheet and assumed equal tRCD 92210561SOmar.Naji@arm.com tCL = '12ns' 92310561SOmar.Naji@arm.com 92410561SOmar.Naji@arm.com tRP = '12ns' 92510561SOmar.Naji@arm.com tRAS = '28ns' 92610561SOmar.Naji@arm.com 92710561SOmar.Naji@arm.com # RRD_S (different bank group) 92810561SOmar.Naji@arm.com # RRD_S is 5.5 ns in datasheet. 92910561SOmar.Naji@arm.com # rounded to the next multiple of tCK 93010561SOmar.Naji@arm.com tRRD = '6ns' 93110561SOmar.Naji@arm.com 93210561SOmar.Naji@arm.com # RRD_L (same bank group) 93310561SOmar.Naji@arm.com # RRD_L is 5.5 ns in datasheet. 93410561SOmar.Naji@arm.com # rounded to the next multiple of tCK 93510561SOmar.Naji@arm.com tRRD_L = '6ns' 93610561SOmar.Naji@arm.com 93710561SOmar.Naji@arm.com tXAW = '23ns' 93810561SOmar.Naji@arm.com 93910561SOmar.Naji@arm.com # tXAW < 4 x tRRD. 94010561SOmar.Naji@arm.com # Therefore, activation limit is set to 0 94110561SOmar.Naji@arm.com activation_limit = 0 94210561SOmar.Naji@arm.com 94310561SOmar.Naji@arm.com tRFC = '65ns' 94410561SOmar.Naji@arm.com tWR = '12ns' 94510561SOmar.Naji@arm.com 94610561SOmar.Naji@arm.com # Here using the average of WTR_S and WTR_L 94710561SOmar.Naji@arm.com tWTR = '5ns' 94810561SOmar.Naji@arm.com 94910561SOmar.Naji@arm.com # Read-to-Precharge 2 CK 95010561SOmar.Naji@arm.com tRTP = '2ns' 95110561SOmar.Naji@arm.com 95210561SOmar.Naji@arm.com # Assume 2 cycles 95310561SOmar.Naji@arm.com tRTW = '2ns' 95410561SOmar.Naji@arm.com 95511120Swendy.elsasser@arm.com# A single HBM x128 interface (one command and address bus), with 95611120Swendy.elsasser@arm.com# default timings based on data publically released 95711120Swendy.elsasser@arm.com# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014), 95811120Swendy.elsasser@arm.com# IDD measurement values, and by extrapolating data from other classes. 95911120Swendy.elsasser@arm.com# Architecture values based on published HBM spec 96011120Swendy.elsasser@arm.com# A 4H stack is defined, 2Gb per die for a total of 1GB of memory. 96111120Swendy.elsasser@arm.comclass HBM_1000_4H_x128(DRAMCtrl): 96211120Swendy.elsasser@arm.com # HBM gen1 supports up to 8 128-bit physical channels 96311120Swendy.elsasser@arm.com # Configuration defines a single channel, with the capacity 96411120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 8) based on 2Gb dies 96511120Swendy.elsasser@arm.com # To use all 8 channels, set 'channels' parameter to 8 in 96611120Swendy.elsasser@arm.com # system configuration 96711120Swendy.elsasser@arm.com 96811120Swendy.elsasser@arm.com # 128-bit interface legacy mode 96911120Swendy.elsasser@arm.com device_bus_width = 128 97011120Swendy.elsasser@arm.com 97111120Swendy.elsasser@arm.com # HBM supports BL4 and BL2 (legacy mode only) 97211120Swendy.elsasser@arm.com burst_length = 4 97311120Swendy.elsasser@arm.com 97411120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack; 97511120Swendy.elsasser@arm.com # with 8 channels, 128MB per channel 97611120Swendy.elsasser@arm.com device_size = '128MB' 97711120Swendy.elsasser@arm.com 97811120Swendy.elsasser@arm.com device_rowbuffer_size = '2kB' 97911120Swendy.elsasser@arm.com 98011120Swendy.elsasser@arm.com # 1x128 configuration 98111120Swendy.elsasser@arm.com devices_per_rank = 1 98211120Swendy.elsasser@arm.com 98311120Swendy.elsasser@arm.com # HBM does not have a CS pin; set rank to 1 98411120Swendy.elsasser@arm.com ranks_per_channel = 1 98511120Swendy.elsasser@arm.com 98611120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 98711120Swendy.elsasser@arm.com # 2Gb dies have 8 banks 98811120Swendy.elsasser@arm.com banks_per_rank = 8 98911120Swendy.elsasser@arm.com 99011120Swendy.elsasser@arm.com # depending on frequency, bank groups may be required 99111120Swendy.elsasser@arm.com # will always have 4 bank groups when enabled 99211120Swendy.elsasser@arm.com # current specifications do not define the minimum frequency for 99311120Swendy.elsasser@arm.com # bank group architecture 99411120Swendy.elsasser@arm.com # setting bank_groups_per_rank to 0 to disable until range is defined 99511120Swendy.elsasser@arm.com bank_groups_per_rank = 0 99611120Swendy.elsasser@arm.com 99711120Swendy.elsasser@arm.com # 500 MHz for 1Gbps DDR data rate 99811120Swendy.elsasser@arm.com tCK = '2ns' 99911120Swendy.elsasser@arm.com 100011120Swendy.elsasser@arm.com # use values from IDD measurement in JEDEC spec 100111120Swendy.elsasser@arm.com # use tRP value for tRCD and tCL similar to other classes 100211120Swendy.elsasser@arm.com tRP = '15ns' 100311120Swendy.elsasser@arm.com tRCD = '15ns' 100411120Swendy.elsasser@arm.com tCL = '15ns' 100511120Swendy.elsasser@arm.com tRAS = '33ns' 100611120Swendy.elsasser@arm.com 100711120Swendy.elsasser@arm.com # BL2 and BL4 supported, default to BL4 100811120Swendy.elsasser@arm.com # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns 100911120Swendy.elsasser@arm.com tBURST = '4ns' 101011120Swendy.elsasser@arm.com 101111120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 101211120Swendy.elsasser@arm.com tRFC = '160ns' 101311120Swendy.elsasser@arm.com 101411120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 101511120Swendy.elsasser@arm.com tREFI = '3.9us' 101611120Swendy.elsasser@arm.com 101711120Swendy.elsasser@arm.com # extrapolate the following from LPDDR configs, using ns values 101811120Swendy.elsasser@arm.com # to minimize burst length, prefetch differences 101911120Swendy.elsasser@arm.com tWR = '18ns' 102011120Swendy.elsasser@arm.com tRTP = '7.5ns' 102111120Swendy.elsasser@arm.com tWTR = '10ns' 102211120Swendy.elsasser@arm.com 102311120Swendy.elsasser@arm.com # start with 2 cycles turnaround, similar to other memory classes 102411120Swendy.elsasser@arm.com # could be more with variations across the stack 102511120Swendy.elsasser@arm.com tRTW = '4ns' 102611120Swendy.elsasser@arm.com 102711120Swendy.elsasser@arm.com # single rank device, set to 0 102811120Swendy.elsasser@arm.com tCS = '0ns' 102911120Swendy.elsasser@arm.com 103011120Swendy.elsasser@arm.com # from MemCon example, tRRD is 4ns with 2ns tCK 103111120Swendy.elsasser@arm.com tRRD = '4ns' 103211120Swendy.elsasser@arm.com 103311120Swendy.elsasser@arm.com # from MemCon example, tFAW is 30ns with 2ns tCK 103411120Swendy.elsasser@arm.com tXAW = '30ns' 103511120Swendy.elsasser@arm.com activation_limit = 4 103611120Swendy.elsasser@arm.com 103711120Swendy.elsasser@arm.com # 4tCK 103811120Swendy.elsasser@arm.com tXP = '8ns' 103911120Swendy.elsasser@arm.com 104011120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 104111120Swendy.elsasser@arm.com tXS = '168ns' 104211120Swendy.elsasser@arm.com 104311120Swendy.elsasser@arm.com# A single HBM x64 interface (one command and address bus), with 104411120Swendy.elsasser@arm.com# default timings based on HBM gen1 and data publically released 104511120Swendy.elsasser@arm.com# A 4H stack is defined, 8Gb per die for a total of 4GB of memory. 104611120Swendy.elsasser@arm.com# Note: This defines a pseudo-channel with a unique controller 104711120Swendy.elsasser@arm.com# instantiated per pseudo-channel 104811120Swendy.elsasser@arm.com# Stay at same IO rate (1Gbps) to maintain timing relationship with 104911120Swendy.elsasser@arm.com# HBM gen1 class (HBM_1000_4H_x128) where possible 105011120Swendy.elsasser@arm.comclass HBM_1000_4H_x64(HBM_1000_4H_x128): 105111120Swendy.elsasser@arm.com # For HBM gen2 with pseudo-channel mode, configure 2X channels. 105211120Swendy.elsasser@arm.com # Configuration defines a single pseudo channel, with the capacity 105311120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 16) based on 8Gb dies 105411120Swendy.elsasser@arm.com # To use all 16 pseudo channels, set 'channels' parameter to 16 in 105511120Swendy.elsasser@arm.com # system configuration 105611120Swendy.elsasser@arm.com 105711120Swendy.elsasser@arm.com # 64-bit pseudo-channle interface 105811120Swendy.elsasser@arm.com device_bus_width = 64 105911120Swendy.elsasser@arm.com 106011120Swendy.elsasser@arm.com # HBM pseudo-channel only supports BL4 106111120Swendy.elsasser@arm.com burst_length = 4 106211120Swendy.elsasser@arm.com 106311120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack; 106411120Swendy.elsasser@arm.com # with 16 channels, 256MB per channel 106511120Swendy.elsasser@arm.com device_size = '256MB' 106611120Swendy.elsasser@arm.com 106711120Swendy.elsasser@arm.com # page size is halved with pseudo-channel; maintaining the same same number 106811120Swendy.elsasser@arm.com # of rows per pseudo-channel with 2X banks across 2 channels 106911120Swendy.elsasser@arm.com device_rowbuffer_size = '1kB' 107011120Swendy.elsasser@arm.com 107111120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 107211120Swendy.elsasser@arm.com # Starting with 4Gb dies, 16 banks are defined 107311120Swendy.elsasser@arm.com banks_per_rank = 16 107411120Swendy.elsasser@arm.com 107511120Swendy.elsasser@arm.com # reset tRFC for larger, 8Gb device 107611120Swendy.elsasser@arm.com # use HBM1 4Gb value as a starting point 107711120Swendy.elsasser@arm.com tRFC = '260ns' 107811120Swendy.elsasser@arm.com 107911120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 108011120Swendy.elsasser@arm.com tXS = '268ns' 108110561SOmar.Naji@arm.com # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns 108210561SOmar.Naji@arm.com tCS = '2ns' 108310561SOmar.Naji@arm.com tREFI = '3.9us' 108411673SOmar.Naji@arm.com 108511673SOmar.Naji@arm.com # active powerdown and precharge powerdown exit time 108611673SOmar.Naji@arm.com tXP = '10ns' 108711673SOmar.Naji@arm.com 108811673SOmar.Naji@arm.com # self refresh exit time 108911673SOmar.Naji@arm.com tXS = '65ns' 1090