DRAMCtrl.py revision 11120
110206Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 1410864Sjungma@eit.uni-kl.de# Copyright (c) 2015 University of Kaiserslautern 159831SN/A# All rights reserved. 169831SN/A# 179243SN/A# Redistribution and use in source and binary forms, with or without 189243SN/A# modification, are permitted provided that the following conditions are 199243SN/A# met: redistributions of source code must retain the above copyright 209243SN/A# notice, this list of conditions and the following disclaimer; 219243SN/A# redistributions in binary form must reproduce the above copyright 229243SN/A# notice, this list of conditions and the following disclaimer in the 239243SN/A# documentation and/or other materials provided with the distribution; 249243SN/A# neither the name of the copyright holders nor the names of its 259243SN/A# contributors may be used to endorse or promote products derived from 269243SN/A# this software without specific prior written permission. 279243SN/A# 289243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 299243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 309243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 319243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 329243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 339243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 349243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 359243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 369243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 379243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 389243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 399243SN/A# 409243SN/A# Authors: Andreas Hansson 419243SN/A# Ani Udipi 4210864Sjungma@eit.uni-kl.de# Omar Naji 4310864Sjungma@eit.uni-kl.de# Matthias Jung 449243SN/A 459243SN/Afrom m5.params import * 469243SN/Afrom AbstractMemory import * 479243SN/A 489243SN/A# Enum for memory scheduling algorithms, currently First-Come 499243SN/A# First-Served and a First-Row Hit then First-Come First-Served 509243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 519243SN/A 5210136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5310136SN/A# channel, rank, bank, row and column, respectively, and going from 5410136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5510136SN/A# suitable for an open-page policy, optimising for sequential accesses 5610136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5710136SN/A# maximises parallelism. 5810136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 599243SN/A 6010144SN/A# Enum for the page policy, either open, open_adaptive, close, or 6110144SN/A# close_adaptive. 6210144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6310144SN/A 'close_adaptive'] 649243SN/A 6510146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 669243SN/A# that aims to model the most important system-level performance 679243SN/A# effects of a DRAM without getting into too much detail of the DRAM 689243SN/A# itself. 6910146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 7010146Sandreas.hansson@arm.com type = 'DRAMCtrl' 7110146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 729243SN/A 739243SN/A # single-ported on the system interface side, instantiate with a 749243SN/A # bus in front of the controller for multiple ports 759243SN/A port = SlavePort("Slave port") 769243SN/A 7710536Sandreas.hansson@arm.com # the basic configuration of the controller architecture, note 7810536Sandreas.hansson@arm.com # that each entry corresponds to a burst for the specific DRAM 7910536Sandreas.hansson@arm.com # configuration (e.g. x32 with burst length 8 is 32 bytes) and not 8010536Sandreas.hansson@arm.com # the cacheline size or request/packet size 8110145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 829972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 839243SN/A 8410140SN/A # threshold in percent for when to forcefully trigger writes and 8510140SN/A # start emptying the write buffer 8610140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 879972SN/A 8810140SN/A # threshold in percentage for when to start writes if the read 8910140SN/A # queue is empty 9010140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 9110140SN/A 9210140SN/A # minimum write bursts to schedule before switching back to reads 9310140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 9410140SN/A "switching to reads") 959243SN/A 969243SN/A # scheduler, address map and page policy 979489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9810675Sandreas.hansson@arm.com addr_mapping = Param.AddrMap('RoRaBaCoCh', "Address mapping policy") 9910145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 1009243SN/A 10110141SN/A # enforce a limit on the number of accesses per row 10210141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 10310141SN/A "closing"); 10410141SN/A 10510489SOmar.Naji@arm.com # size of DRAM Chip in Bytes 10610489SOmar.Naji@arm.com device_size = Param.MemorySize("Size of DRAM chip") 10710489SOmar.Naji@arm.com 1089726SN/A # pipeline latency of the controller and PHY, split into a 1099726SN/A # frontend part and a backend part, with reads and writes serviced 1109726SN/A # by the queues only seeing the frontend contribution, and reads 1119726SN/A # serviced by the memory seeing the sum of the two 1129726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1139726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1149726SN/A 1159489SN/A # the physical organisation of the DRAM 1169831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1179831SN/A "device/chip") 1189831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1199831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1209831SN/A "device/chip") 1219831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1229489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 12310394Swendy.elsasser@arm.com 12410394Swendy.elsasser@arm.com # default to 0 bank groups per rank, indicating bank group architecture 12510394Swendy.elsasser@arm.com # is not used 12610394Swendy.elsasser@arm.com # update per memory class when bank group architecture is supported 12710394Swendy.elsasser@arm.com bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1289489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1299566SN/A # only used for the address mapping as the controller by 1309566SN/A # construction is a single channel and multiple controllers have 1319566SN/A # to be instantiated for a multi-channel configuration 1329566SN/A channels = Param.Unsigned(1, "Number of channels") 1339489SN/A 13410430SOmar.Naji@arm.com # For power modelling we need to know if the DRAM has a DLL or not 13510430SOmar.Naji@arm.com dll = Param.Bool(True, "DRAM has DLL or not") 13610430SOmar.Naji@arm.com 13710430SOmar.Naji@arm.com # DRAMPower provides in addition to the core power, the possibility to 13810430SOmar.Naji@arm.com # include RD/WR termination and IO power. This calculation assumes some 13910430SOmar.Naji@arm.com # default values. The integration of DRAMPower with gem5 does not include 14010430SOmar.Naji@arm.com # IO and RD/WR termination power by default. This might be added as an 14110430SOmar.Naji@arm.com # additional feature in the future. 14210430SOmar.Naji@arm.com 1439243SN/A # timing behaviour and constraints - all in nanoseconds 1449243SN/A 14510216Sandreas.hansson@arm.com # the base clock period of the DRAM 14610216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 14710216Sandreas.hansson@arm.com 1489243SN/A # the amount of time in nanoseconds from issuing an activate command 1499243SN/A # to the data being available in the row buffer for a read/write 1509489SN/A tRCD = Param.Latency("RAS to CAS delay") 1519243SN/A 1529243SN/A # the time from issuing a read/write command to seeing the actual data 1539489SN/A tCL = Param.Latency("CAS latency") 1549243SN/A 1559243SN/A # minimum time between a precharge and subsequent activate 1569489SN/A tRP = Param.Latency("Row precharge time") 1579243SN/A 1589963SN/A # minimum time between an activate and a precharge to the same row 1599963SN/A tRAS = Param.Latency("ACT to PRE delay") 1609963SN/A 16110210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 16210210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 16310210Sandreas.hansson@arm.com 16410212Sandreas.hansson@arm.com # minimum time between a read and precharge command 16510212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 16610212Sandreas.hansson@arm.com 1679243SN/A # time to complete a burst transfer, typically the burst length 1689243SN/A # divided by two due to the DDR bus, but by making it a parameter 1699243SN/A # it is easier to also evaluate SDR memories like WideIO. 1709831SN/A # This parameter has to account for burst length. 1719831SN/A # Read/Write requests with data size larger than one full burst are broken 17210146Sandreas.hansson@arm.com # down into multiple requests in the controller 17310394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 17410394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 17510394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 1769489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1779243SN/A 17810394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 17910394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 18010394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 18110394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 18210394Swendy.elsasser@arm.com tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 18310394Swendy.elsasser@arm.com 1849243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1859489SN/A tRFC = Param.Latency("Refresh cycle time") 1869243SN/A 1879243SN/A # refresh command interval, how often a "ref" command needs 1889243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1899489SN/A tREFI = Param.Latency("Refresh command interval") 1909243SN/A 19110393Swendy.elsasser@arm.com # write-to-read, same rank turnaround penalty 19210393Swendy.elsasser@arm.com tWTR = Param.Latency("Write to read, same rank switching time") 1939243SN/A 19410393Swendy.elsasser@arm.com # read-to-write, same rank turnaround penalty 19510393Swendy.elsasser@arm.com tRTW = Param.Latency("Read to write, same rank switching time") 19610393Swendy.elsasser@arm.com 19710393Swendy.elsasser@arm.com # rank-to-rank bus delay penalty 19810393Swendy.elsasser@arm.com # this does not correlate to a memory timing parameter and encompasses: 19910393Swendy.elsasser@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 20010393Swendy.elsasser@arm.com # different rank bus delay 20110393Swendy.elsasser@arm.com tCS = Param.Latency("Rank to rank switching time") 20210206Sandreas.hansson@arm.com 2039971SN/A # minimum row activate to row activate delay time 2049971SN/A tRRD = Param.Latency("ACT to ACT delay") 2059971SN/A 20610394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 20710394Swendy.elsasser@arm.com tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 20810394Swendy.elsasser@arm.com 2099488SN/A # time window in which a maximum number of activates are allowed 2109488SN/A # to take place, set to 0 to disable 2119489SN/A tXAW = Param.Latency("X activation window") 2129489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 2139488SN/A 21410430SOmar.Naji@arm.com # time to exit power-down mode 21510430SOmar.Naji@arm.com # Exit power-down to next valid command delay 21610430SOmar.Naji@arm.com tXP = Param.Latency("0ns", "Power-up Delay") 21710430SOmar.Naji@arm.com 21810430SOmar.Naji@arm.com # Exit Powerdown to commands requiring a locked DLL 21910430SOmar.Naji@arm.com tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL") 22010430SOmar.Naji@arm.com 22110430SOmar.Naji@arm.com # time to exit self-refresh mode 22210430SOmar.Naji@arm.com tXS = Param.Latency("0ns", "Self-refresh exit latency") 22310430SOmar.Naji@arm.com 22410430SOmar.Naji@arm.com # time to exit self-refresh mode with locked DLL 22510430SOmar.Naji@arm.com tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL") 22610430SOmar.Naji@arm.com 2279488SN/A # Currently rolled into other params 2289243SN/A ###################################################################### 2299243SN/A 2309963SN/A # tRC - assumed to be tRAS + tRP 2319243SN/A 23210430SOmar.Naji@arm.com # Power Behaviour and Constraints 23310430SOmar.Naji@arm.com # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are 23410430SOmar.Naji@arm.com # defined as VDD and VDD2. Each current is defined for each voltage domain 23510430SOmar.Naji@arm.com # separately. For example, current IDD0 is active-precharge current for 23610430SOmar.Naji@arm.com # voltage domain VDD and current IDD02 is active-precharge current for 23710430SOmar.Naji@arm.com # voltage domain VDD2. 23810430SOmar.Naji@arm.com # By default all currents are set to 0mA. Users who are only interested in 23910430SOmar.Naji@arm.com # the performance of DRAMs can leave them at 0. 24010430SOmar.Naji@arm.com 24110430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current 24210430SOmar.Naji@arm.com IDD0 = Param.Current("0mA", "Active precharge current") 24310430SOmar.Naji@arm.com 24410430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current multiple voltage Range 24510430SOmar.Naji@arm.com IDD02 = Param.Current("0mA", "Active precharge current VDD2") 24610430SOmar.Naji@arm.com 24710430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit 24810430SOmar.Naji@arm.com IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow") 24910430SOmar.Naji@arm.com 25010430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit multiple voltage Range 25110430SOmar.Naji@arm.com IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2") 25210430SOmar.Naji@arm.com 25310430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit 25410430SOmar.Naji@arm.com IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast") 25510430SOmar.Naji@arm.com 25610430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit multiple voltage Range 25710430SOmar.Naji@arm.com IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2") 25810430SOmar.Naji@arm.com 25910430SOmar.Naji@arm.com # Precharge Standby current 26010430SOmar.Naji@arm.com IDD2N = Param.Current("0mA", "Precharge Standby current") 26110430SOmar.Naji@arm.com 26210430SOmar.Naji@arm.com # Precharge Standby current multiple voltage range 26310430SOmar.Naji@arm.com IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2") 26410430SOmar.Naji@arm.com 26510430SOmar.Naji@arm.com # Active Power-down current: slow exit 26610430SOmar.Naji@arm.com IDD3P0 = Param.Current("0mA", "Active Powerdown slow") 26710430SOmar.Naji@arm.com 26810430SOmar.Naji@arm.com # Active Power-down current: slow exit multiple voltage range 26910430SOmar.Naji@arm.com IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2") 27010430SOmar.Naji@arm.com 27110430SOmar.Naji@arm.com # Active Power-down current : fast exit 27210430SOmar.Naji@arm.com IDD3P1 = Param.Current("0mA", "Active Powerdown fast") 27310430SOmar.Naji@arm.com 27410430SOmar.Naji@arm.com # Active Power-down current : fast exit multiple voltage range 27510430SOmar.Naji@arm.com IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2") 27610430SOmar.Naji@arm.com 27710430SOmar.Naji@arm.com # Active Standby current 27810430SOmar.Naji@arm.com IDD3N = Param.Current("0mA", "Active Standby current") 27910430SOmar.Naji@arm.com 28010430SOmar.Naji@arm.com # Active Standby current multiple voltage range 28110430SOmar.Naji@arm.com IDD3N2 = Param.Current("0mA", "Active Standby current VDD2") 28210430SOmar.Naji@arm.com 28310430SOmar.Naji@arm.com # Burst Read Operating Current 28410430SOmar.Naji@arm.com IDD4R = Param.Current("0mA", "READ current") 28510430SOmar.Naji@arm.com 28610430SOmar.Naji@arm.com # Burst Read Operating Current multiple voltage range 28710430SOmar.Naji@arm.com IDD4R2 = Param.Current("0mA", "READ current VDD2") 28810430SOmar.Naji@arm.com 28910430SOmar.Naji@arm.com # Burst Write Operating Current 29010430SOmar.Naji@arm.com IDD4W = Param.Current("0mA", "WRITE current") 29110430SOmar.Naji@arm.com 29210430SOmar.Naji@arm.com # Burst Write Operating Current multiple voltage range 29310430SOmar.Naji@arm.com IDD4W2 = Param.Current("0mA", "WRITE current VDD2") 29410430SOmar.Naji@arm.com 29510430SOmar.Naji@arm.com # Refresh Current 29610430SOmar.Naji@arm.com IDD5 = Param.Current("0mA", "Refresh current") 29710430SOmar.Naji@arm.com 29810430SOmar.Naji@arm.com # Refresh Current multiple voltage range 29910430SOmar.Naji@arm.com IDD52 = Param.Current("0mA", "Refresh current VDD2") 30010430SOmar.Naji@arm.com 30110430SOmar.Naji@arm.com # Self-Refresh Current 30210430SOmar.Naji@arm.com IDD6 = Param.Current("0mA", "Self-refresh Current") 30310430SOmar.Naji@arm.com 30410430SOmar.Naji@arm.com # Self-Refresh Current multiple voltage range 30510430SOmar.Naji@arm.com IDD62 = Param.Current("0mA", "Self-refresh Current VDD2") 30610430SOmar.Naji@arm.com 30710430SOmar.Naji@arm.com # Main voltage range of the DRAM 30810430SOmar.Naji@arm.com VDD = Param.Voltage("0V", "Main Voltage Range") 30910430SOmar.Naji@arm.com 31010430SOmar.Naji@arm.com # Second voltage range defined by some DRAMs 31110430SOmar.Naji@arm.com VDD2 = Param.Voltage("0V", "2nd Voltage Range") 31210430SOmar.Naji@arm.com 31310217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 31410217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 31510430SOmar.Naji@arm.com# an 8x8 configuration. 31610146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 31710489SOmar.Naji@arm.com # size of device in bytes 31810489SOmar.Naji@arm.com device_size = '512MB' 31910489SOmar.Naji@arm.com 3209831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 3219831SN/A device_bus_width = 8 3229831SN/A 3239831SN/A # DDR3 is a BL8 device 3249831SN/A burst_length = 8 3259831SN/A 32610217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 3279831SN/A device_rowbuffer_size = '1kB' 3289831SN/A 3299831SN/A # 8x8 configuration, so 8 devices 3309831SN/A devices_per_rank = 8 3319489SN/A 3329489SN/A # Use two ranks 3339489SN/A ranks_per_channel = 2 3349489SN/A 3359489SN/A # DDR3 has 8 banks in all configurations 3369489SN/A banks_per_rank = 8 3379489SN/A 33810216Sandreas.hansson@arm.com # 800 MHz 33910216Sandreas.hansson@arm.com tCK = '1.25ns' 34010216Sandreas.hansson@arm.com 34110217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 34210217Sandreas.hansson@arm.com tBURST = '5ns' 34310217Sandreas.hansson@arm.com 34410217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 3459489SN/A tRCD = '13.75ns' 3469489SN/A tCL = '13.75ns' 3479489SN/A tRP = '13.75ns' 3489970SN/A tRAS = '35ns' 34910217Sandreas.hansson@arm.com tRRD = '6ns' 35010217Sandreas.hansson@arm.com tXAW = '30ns' 35110217Sandreas.hansson@arm.com activation_limit = 4 35210217Sandreas.hansson@arm.com tRFC = '260ns' 35310217Sandreas.hansson@arm.com 35410210Sandreas.hansson@arm.com tWR = '15ns' 35510217Sandreas.hansson@arm.com 35610217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 35710217Sandreas.hansson@arm.com tWTR = '7.5ns' 35810217Sandreas.hansson@arm.com 35910217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 36010212Sandreas.hansson@arm.com tRTP = '7.5ns' 3619489SN/A 36210393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 36310206Sandreas.hansson@arm.com tRTW = '2.5ns' 36410206Sandreas.hansson@arm.com 36510393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 36610393Swendy.elsasser@arm.com tCS = '2.5ns' 36710393Swendy.elsasser@arm.com 36810217Sandreas.hansson@arm.com # <=85C, half for >85C 36910217Sandreas.hansson@arm.com tREFI = '7.8us' 3709971SN/A 37110430SOmar.Naji@arm.com # Current values from datasheet 37210430SOmar.Naji@arm.com IDD0 = '75mA' 37310430SOmar.Naji@arm.com IDD2N = '50mA' 37410430SOmar.Naji@arm.com IDD3N = '57mA' 37510430SOmar.Naji@arm.com IDD4W = '165mA' 37610430SOmar.Naji@arm.com IDD4R = '187mA' 37710430SOmar.Naji@arm.com IDD5 = '220mA' 37810430SOmar.Naji@arm.com VDD = '1.5V' 37910430SOmar.Naji@arm.com 38010864Sjungma@eit.uni-kl.de# A single HMC-2500 x32 model based on: 38110864Sjungma@eit.uni-kl.de# [1] DRAMSpec: a high-level DRAM bank modelling tool 38210864Sjungma@eit.uni-kl.de# developed at the University of Kaiserslautern. This high level tool 38310864Sjungma@eit.uni-kl.de# uses RC (resistance-capacitance) and CV (capacitance-voltage) models to 38410864Sjungma@eit.uni-kl.de# estimate the DRAM bank latency and power numbers. 38510864Sjungma@eit.uni-kl.de# [2] A Logic-base Interconnect for Supporting Near Memory Computation in the 38610864Sjungma@eit.uni-kl.de# Hybrid Memory Cube (E. Azarkhish et. al) 38710864Sjungma@eit.uni-kl.de# Assumed for the HMC model is a 30 nm technology node. 38810864Sjungma@eit.uni-kl.de# The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4 38910864Sjungma@eit.uni-kl.de# layers). 39010864Sjungma@eit.uni-kl.de# Each layer has 16 vaults and each vault consists of 2 banks per layer. 39110864Sjungma@eit.uni-kl.de# In order to be able to use the same controller used for 2D DRAM generations 39210864Sjungma@eit.uni-kl.de# for HMC, the following analogy is done: 39310864Sjungma@eit.uni-kl.de# Channel (DDR) => Vault (HMC) 39410864Sjungma@eit.uni-kl.de# device_size (DDR) => size of a single layer in a vault 39510864Sjungma@eit.uni-kl.de# ranks per channel (DDR) => number of layers 39610864Sjungma@eit.uni-kl.de# banks per rank (DDR) => banks per layer 39710864Sjungma@eit.uni-kl.de# devices per rank (DDR) => devices per layer ( 1 for HMC). 39810864Sjungma@eit.uni-kl.de# The parameters for which no input is available are inherited from the DDR3 39910864Sjungma@eit.uni-kl.de# configuration. 40010864Sjungma@eit.uni-kl.de# This configuration includes the latencies from the DRAM to the logic layer of 40110864Sjungma@eit.uni-kl.de# the HMC 40210864Sjungma@eit.uni-kl.declass HMC_2500_x32(DDR3_1600_x64): 40310864Sjungma@eit.uni-kl.de # size of device 40410864Sjungma@eit.uni-kl.de # two banks per device with each bank 4MB [2] 40510864Sjungma@eit.uni-kl.de device_size = '8MB' 40610864Sjungma@eit.uni-kl.de 40710864Sjungma@eit.uni-kl.de # 1x32 configuration, 1 device with 32 TSVs [2] 40810864Sjungma@eit.uni-kl.de device_bus_width = 32 40910864Sjungma@eit.uni-kl.de 41010864Sjungma@eit.uni-kl.de # HMC is a BL8 device [2] 41110864Sjungma@eit.uni-kl.de burst_length = 8 41210864Sjungma@eit.uni-kl.de 41310864Sjungma@eit.uni-kl.de # Each device has a page (row buffer) size of 256 bytes [2] 41410864Sjungma@eit.uni-kl.de device_rowbuffer_size = '256B' 41510864Sjungma@eit.uni-kl.de 41610864Sjungma@eit.uni-kl.de # 1x32 configuration, so 1 device [2] 41710864Sjungma@eit.uni-kl.de devices_per_rank = 1 41810864Sjungma@eit.uni-kl.de 41910864Sjungma@eit.uni-kl.de # 4 layers so 4 ranks [2] 42010864Sjungma@eit.uni-kl.de ranks_per_channel = 4 42110864Sjungma@eit.uni-kl.de 42210864Sjungma@eit.uni-kl.de # HMC has 2 banks per layer [2] 42310864Sjungma@eit.uni-kl.de # Each layer represents a rank. With 4 layers and 8 banks in total, each 42410864Sjungma@eit.uni-kl.de # layer has 2 banks; thus 2 banks per rank. 42510864Sjungma@eit.uni-kl.de banks_per_rank = 2 42610864Sjungma@eit.uni-kl.de 42710864Sjungma@eit.uni-kl.de # 1250 MHz [2] 42810864Sjungma@eit.uni-kl.de tCK = '0.8ns' 42910864Sjungma@eit.uni-kl.de 43010864Sjungma@eit.uni-kl.de # 8 beats across an x32 interface translates to 4 clocks @ 1250 MHz 43110864Sjungma@eit.uni-kl.de tBURST = '3.2ns' 43210864Sjungma@eit.uni-kl.de 43310864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 43410864Sjungma@eit.uni-kl.de tRCD = '10.2ns' 43510864Sjungma@eit.uni-kl.de tCL = '9.9ns' 43610864Sjungma@eit.uni-kl.de tRP = '7.7ns' 43710864Sjungma@eit.uni-kl.de tRAS = '21.6ns' 43810864Sjungma@eit.uni-kl.de 43910864Sjungma@eit.uni-kl.de # tRRD depends on the power supply network for each vendor. 44010864Sjungma@eit.uni-kl.de # We assume a tRRD of a double bank approach to be equal to 4 clock 44110864Sjungma@eit.uni-kl.de # cycles (Assumption) 44210864Sjungma@eit.uni-kl.de tRRD = '3.2ns' 44310864Sjungma@eit.uni-kl.de 44410864Sjungma@eit.uni-kl.de # activation limit is set to 0 since there are only 2 banks per vault layer. 44510864Sjungma@eit.uni-kl.de activation_limit = 0 44610864Sjungma@eit.uni-kl.de 44710864Sjungma@eit.uni-kl.de # Values using DRAMSpec HMC model [1] 44810864Sjungma@eit.uni-kl.de tRFC = '59ns' 44910864Sjungma@eit.uni-kl.de tWR = '8ns' 45010864Sjungma@eit.uni-kl.de tRTP = '4.9ns' 45110864Sjungma@eit.uni-kl.de 45210864Sjungma@eit.uni-kl.de # Default different rank bus delay assumed to 1 CK for TSVs, @1250 MHz = 0.8 45310864Sjungma@eit.uni-kl.de # ns (Assumption) 45410864Sjungma@eit.uni-kl.de tCS = '0.8ns' 45510864Sjungma@eit.uni-kl.de 45610864Sjungma@eit.uni-kl.de # Value using DRAMSpec HMC model [1] 45710864Sjungma@eit.uni-kl.de tREFI = '3.9us' 45810864Sjungma@eit.uni-kl.de 45910864Sjungma@eit.uni-kl.de # Set default controller parameters 46010864Sjungma@eit.uni-kl.de page_policy = 'close' 46110864Sjungma@eit.uni-kl.de write_buffer_size = 8 46210864Sjungma@eit.uni-kl.de read_buffer_size = 8 46310864Sjungma@eit.uni-kl.de addr_mapping = 'RoCoRaBaCh' 46410864Sjungma@eit.uni-kl.de min_writes_per_switch = 8 46510864Sjungma@eit.uni-kl.de 46610217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 46710217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 46810217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 46910217Sandreas.hansson@arm.com# consistent across the two configurations. 47010217Sandreas.hansson@arm.comclass DDR3_2133_x64(DDR3_1600_x64): 47110217Sandreas.hansson@arm.com # 1066 MHz 47210217Sandreas.hansson@arm.com tCK = '0.938ns' 47310217Sandreas.hansson@arm.com 47410217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 47510217Sandreas.hansson@arm.com tBURST = '3.752ns' 47610217Sandreas.hansson@arm.com 47710217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 47810217Sandreas.hansson@arm.com tRCD = '13.09ns' 47910217Sandreas.hansson@arm.com tCL = '13.09ns' 48010217Sandreas.hansson@arm.com tRP = '13.09ns' 48110217Sandreas.hansson@arm.com tRAS = '33ns' 48210217Sandreas.hansson@arm.com tRRD = '5ns' 48310217Sandreas.hansson@arm.com tXAW = '25ns' 48410217Sandreas.hansson@arm.com 48510430SOmar.Naji@arm.com # Current values from datasheet 48610430SOmar.Naji@arm.com IDD0 = '70mA' 48710430SOmar.Naji@arm.com IDD2N = '37mA' 48810430SOmar.Naji@arm.com IDD3N = '44mA' 48910430SOmar.Naji@arm.com IDD4W = '157mA' 49010430SOmar.Naji@arm.com IDD4R = '191mA' 49110430SOmar.Naji@arm.com IDD5 = '250mA' 49210430SOmar.Naji@arm.com VDD = '1.5V' 49310430SOmar.Naji@arm.com 49410217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 49510430SOmar.Naji@arm.com# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8) 49610430SOmar.Naji@arm.com# in an 8x8 configuration. 49710217Sandreas.hansson@arm.comclass DDR4_2400_x64(DRAMCtrl): 49810489SOmar.Naji@arm.com # size of device 49910489SOmar.Naji@arm.com device_size = '512MB' 50010489SOmar.Naji@arm.com 50110217Sandreas.hansson@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 50210217Sandreas.hansson@arm.com device_bus_width = 8 50310217Sandreas.hansson@arm.com 50410217Sandreas.hansson@arm.com # DDR4 is a BL8 device 50510217Sandreas.hansson@arm.com burst_length = 8 50610217Sandreas.hansson@arm.com 50710217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 50810217Sandreas.hansson@arm.com device_rowbuffer_size = '1kB' 50910217Sandreas.hansson@arm.com 51010217Sandreas.hansson@arm.com # 8x8 configuration, so 8 devices 51110217Sandreas.hansson@arm.com devices_per_rank = 8 51210217Sandreas.hansson@arm.com 51310430SOmar.Naji@arm.com # Match our DDR3 configurations which is dual rank 51410430SOmar.Naji@arm.com ranks_per_channel = 2 51510217Sandreas.hansson@arm.com 51610394Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 51710394Swendy.elsasser@arm.com # Set to 4 for x4, x8 case 51810394Swendy.elsasser@arm.com bank_groups_per_rank = 4 51910394Swendy.elsasser@arm.com 52010217Sandreas.hansson@arm.com # DDR4 has 16 banks (4 bank groups) in all 52110217Sandreas.hansson@arm.com # configurations. Currently we do not capture the additional 52210217Sandreas.hansson@arm.com # constraints incurred by the bank groups 52310217Sandreas.hansson@arm.com banks_per_rank = 16 52410217Sandreas.hansson@arm.com 52510891Sandreas.hansson@arm.com # override the default buffer sizes and go for something larger to 52610891Sandreas.hansson@arm.com # accommodate the larger bank count 52710891Sandreas.hansson@arm.com write_buffer_size = 128 52810891Sandreas.hansson@arm.com read_buffer_size = 64 52910891Sandreas.hansson@arm.com 53010217Sandreas.hansson@arm.com # 1200 MHz 53110217Sandreas.hansson@arm.com tCK = '0.833ns' 53210217Sandreas.hansson@arm.com 53310217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 53410394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 53510394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 53610394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 53710217Sandreas.hansson@arm.com tBURST = '3.333ns' 53810217Sandreas.hansson@arm.com 53910394Swendy.elsasser@arm.com # @2400 data rate, tCCD_L is 6 CK 54010394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 54110394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 54210394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 54310394Swendy.elsasser@arm.com tCCD_L = '5ns'; 54410394Swendy.elsasser@arm.com 54510217Sandreas.hansson@arm.com # DDR4-2400 17-17-17 54610217Sandreas.hansson@arm.com tRCD = '14.16ns' 54710217Sandreas.hansson@arm.com tCL = '14.16ns' 54810217Sandreas.hansson@arm.com tRP = '14.16ns' 54910217Sandreas.hansson@arm.com tRAS = '32ns' 55010217Sandreas.hansson@arm.com 55110394Swendy.elsasser@arm.com # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns) 55210394Swendy.elsasser@arm.com tRRD = '3.3ns' 55310394Swendy.elsasser@arm.com 55410394Swendy.elsasser@arm.com # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 55510394Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 55610394Swendy.elsasser@arm.com 55710217Sandreas.hansson@arm.com tXAW = '21ns' 5589489SN/A activation_limit = 4 55910430SOmar.Naji@arm.com tRFC = '350ns' 5609489SN/A 56110217Sandreas.hansson@arm.com tWR = '15ns' 56210217Sandreas.hansson@arm.com 56310217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 56410217Sandreas.hansson@arm.com tWTR = '5ns' 56510217Sandreas.hansson@arm.com 56610217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 56710217Sandreas.hansson@arm.com tRTP = '7.5ns' 56810217Sandreas.hansson@arm.com 56910393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 57010217Sandreas.hansson@arm.com tRTW = '1.666ns' 57110217Sandreas.hansson@arm.com 57210393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 57310393Swendy.elsasser@arm.com tCS = '1.666ns' 57410393Swendy.elsasser@arm.com 57510217Sandreas.hansson@arm.com # <=85C, half for >85C 57610217Sandreas.hansson@arm.com tREFI = '7.8us' 5779489SN/A 57810430SOmar.Naji@arm.com # Current values from datasheet 57910430SOmar.Naji@arm.com IDD0 = '64mA' 58010430SOmar.Naji@arm.com IDD02 = '4mA' 58110430SOmar.Naji@arm.com IDD2N = '50mA' 58210430SOmar.Naji@arm.com IDD3N = '67mA' 58310430SOmar.Naji@arm.com IDD3N2 = '3mA' 58410430SOmar.Naji@arm.com IDD4W = '180mA' 58510430SOmar.Naji@arm.com IDD4R = '160mA' 58610430SOmar.Naji@arm.com IDD5 = '192mA' 58710430SOmar.Naji@arm.com VDD = '1.2V' 58810430SOmar.Naji@arm.com VDD2 = '2.5V' 58910430SOmar.Naji@arm.com 5909728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 59110430SOmar.Naji@arm.com# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 59210430SOmar.Naji@arm.com# in a 1x32 configuration. 59310146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 59410430SOmar.Naji@arm.com # No DLL in LPDDR2 59510430SOmar.Naji@arm.com dll = False 59610430SOmar.Naji@arm.com 59710489SOmar.Naji@arm.com # size of device 59810489SOmar.Naji@arm.com device_size = '512MB' 59910489SOmar.Naji@arm.com 6009831SN/A # 1x32 configuration, 1 device with a 32-bit interface 6019831SN/A device_bus_width = 32 6029831SN/A 6039831SN/A # LPDDR2_S4 is a BL4 and BL8 device 6049831SN/A burst_length = 8 6059831SN/A 6069831SN/A # Each device has a page (row buffer) size of 1KB 6079831SN/A # (this depends on the memory density) 6089831SN/A device_rowbuffer_size = '1kB' 6099831SN/A 6109831SN/A # 1x32 configuration, so 1 device 6119831SN/A devices_per_rank = 1 6129489SN/A 6139708SN/A # Use a single rank 6149708SN/A ranks_per_channel = 1 6159489SN/A 6169489SN/A # LPDDR2-S4 has 8 banks in all configurations 6179489SN/A banks_per_rank = 8 6189489SN/A 61910216Sandreas.hansson@arm.com # 533 MHz 62010216Sandreas.hansson@arm.com tCK = '1.876ns' 62110216Sandreas.hansson@arm.com 6229489SN/A # Fixed at 15 ns 6239489SN/A tRCD = '15ns' 6249489SN/A 6259489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 6269489SN/A tCL = '15ns' 6279489SN/A 6289728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 6299728SN/A tRP = '15ns' 6309489SN/A 6319970SN/A tRAS = '42ns' 63210210Sandreas.hansson@arm.com tWR = '15ns' 6339963SN/A 63410430SOmar.Naji@arm.com tRTP = '7.5ns' 63510212Sandreas.hansson@arm.com 6369831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 6379831SN/A # Note this is a BL8 DDR device. 6389831SN/A # Requests larger than 32 bytes are broken down into multiple requests 63910146Sandreas.hansson@arm.com # in the controller 6409831SN/A tBURST = '7.5ns' 6419489SN/A 6429708SN/A # LPDDR2-S4, 4 Gbit 6439489SN/A tRFC = '130ns' 6449489SN/A tREFI = '3.9us' 6459489SN/A 6469489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 6479489SN/A tWTR = '7.5ns' 6489489SN/A 64910393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 65010206Sandreas.hansson@arm.com tRTW = '3.75ns' 65110206Sandreas.hansson@arm.com 65210393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 65310393Swendy.elsasser@arm.com tCS = '3.75ns' 65410393Swendy.elsasser@arm.com 6559971SN/A # Activate to activate irrespective of density and speed grade 6569971SN/A tRRD = '10.0ns' 6579971SN/A 6589708SN/A # Irrespective of density, tFAW is 50 ns 6599489SN/A tXAW = '50ns' 6609489SN/A activation_limit = 4 6619664SN/A 66210430SOmar.Naji@arm.com # Current values from datasheet 66310430SOmar.Naji@arm.com IDD0 = '15mA' 66410430SOmar.Naji@arm.com IDD02 = '70mA' 66510430SOmar.Naji@arm.com IDD2N = '2mA' 66610430SOmar.Naji@arm.com IDD2N2 = '30mA' 66710430SOmar.Naji@arm.com IDD3N = '2.5mA' 66810430SOmar.Naji@arm.com IDD3N2 = '30mA' 66910430SOmar.Naji@arm.com IDD4W = '10mA' 67010430SOmar.Naji@arm.com IDD4W2 = '190mA' 67110430SOmar.Naji@arm.com IDD4R = '3mA' 67210430SOmar.Naji@arm.com IDD4R2 = '220mA' 67310430SOmar.Naji@arm.com IDD5 = '40mA' 67410430SOmar.Naji@arm.com IDD52 = '150mA' 67510430SOmar.Naji@arm.com VDD = '1.8V' 67610430SOmar.Naji@arm.com VDD2 = '1.2V' 67710430SOmar.Naji@arm.com 6789728SN/A# A single WideIO x128 interface (one command and address bus), with 6799728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 68010146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 68110430SOmar.Naji@arm.com # No DLL for WideIO 68210430SOmar.Naji@arm.com dll = False 68310430SOmar.Naji@arm.com 68410489SOmar.Naji@arm.com # size of device 68510489SOmar.Naji@arm.com device_size = '1024MB' 68610489SOmar.Naji@arm.com 6879831SN/A # 1x128 configuration, 1 device with a 128-bit interface 6889831SN/A device_bus_width = 128 6899831SN/A 6909831SN/A # This is a BL4 device 6919831SN/A burst_length = 4 6929831SN/A 6939831SN/A # Each device has a page (row buffer) size of 4KB 6949831SN/A # (this depends on the memory density) 6959831SN/A device_rowbuffer_size = '4kB' 6969831SN/A 6979831SN/A # 1x128 configuration, so 1 device 6989831SN/A devices_per_rank = 1 6999664SN/A 7009664SN/A # Use one rank for a one-high die stack 7019664SN/A ranks_per_channel = 1 7029664SN/A 7039664SN/A # WideIO has 4 banks in all configurations 7049664SN/A banks_per_rank = 4 7059664SN/A 70610216Sandreas.hansson@arm.com # 200 MHz 70710216Sandreas.hansson@arm.com tCK = '5ns' 70810216Sandreas.hansson@arm.com 7099664SN/A # WIO-200 7109664SN/A tRCD = '18ns' 7119664SN/A tCL = '18ns' 7129664SN/A tRP = '18ns' 7139970SN/A tRAS = '42ns' 71410210Sandreas.hansson@arm.com tWR = '15ns' 71510212Sandreas.hansson@arm.com # Read to precharge is same as the burst 71610212Sandreas.hansson@arm.com tRTP = '20ns' 7179664SN/A 7189831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 7199831SN/A # Note this is a BL4 SDR device. 7209664SN/A tBURST = '20ns' 7219664SN/A 7229664SN/A # WIO 8 Gb 7239664SN/A tRFC = '210ns' 7249664SN/A 7259664SN/A # WIO 8 Gb, <=85C, half for >85C 7269664SN/A tREFI = '3.9us' 7279664SN/A 7289664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 7299664SN/A tWTR = '15ns' 7309664SN/A 73110393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 73210206Sandreas.hansson@arm.com tRTW = '10ns' 73310206Sandreas.hansson@arm.com 73410393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 73510393Swendy.elsasser@arm.com tCS = '10ns' 73610393Swendy.elsasser@arm.com 7379971SN/A # Activate to activate irrespective of density and speed grade 7389971SN/A tRRD = '10.0ns' 7399971SN/A 7409664SN/A # Two instead of four activation window 7419664SN/A tXAW = '50ns' 7429664SN/A activation_limit = 2 7439709SN/A 74410430SOmar.Naji@arm.com # The WideIO specification does not provide current information 74510430SOmar.Naji@arm.com 7469728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 74710430SOmar.Naji@arm.com# default timings based on a LPDDR3-1600 4 Gbit part (Micron 74810430SOmar.Naji@arm.com# EDF8132A1MC) in a 1x32 configuration. 74910146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 75010430SOmar.Naji@arm.com # No DLL for LPDDR3 75110430SOmar.Naji@arm.com dll = False 75210430SOmar.Naji@arm.com 75310489SOmar.Naji@arm.com # size of device 75410489SOmar.Naji@arm.com device_size = '512MB' 75510489SOmar.Naji@arm.com 7569831SN/A # 1x32 configuration, 1 device with a 32-bit interface 7579831SN/A device_bus_width = 32 7589831SN/A 7599831SN/A # LPDDR3 is a BL8 device 7609831SN/A burst_length = 8 7619831SN/A 7629976SN/A # Each device has a page (row buffer) size of 4KB 7639976SN/A device_rowbuffer_size = '4kB' 7649831SN/A 7659831SN/A # 1x32 configuration, so 1 device 7669831SN/A devices_per_rank = 1 7679709SN/A 76810430SOmar.Naji@arm.com # Technically the datasheet is a dual-rank package, but for 76910430SOmar.Naji@arm.com # comparison with the LPDDR2 config we stick to a single rank 7709709SN/A ranks_per_channel = 1 7719709SN/A 7729709SN/A # LPDDR3 has 8 banks in all configurations 7739709SN/A banks_per_rank = 8 7749709SN/A 77510216Sandreas.hansson@arm.com # 800 MHz 77610216Sandreas.hansson@arm.com tCK = '1.25ns' 77710216Sandreas.hansson@arm.com 77810430SOmar.Naji@arm.com tRCD = '18ns' 7799709SN/A 7809709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 7819709SN/A tCL = '15ns' 7829709SN/A 7839970SN/A tRAS = '42ns' 78410210Sandreas.hansson@arm.com tWR = '15ns' 7859963SN/A 78610212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 78710212Sandreas.hansson@arm.com tRTP = '7.5ns' 78810212Sandreas.hansson@arm.com 78910430SOmar.Naji@arm.com # Pre-charge one bank 18 ns (all banks 21 ns) 79010430SOmar.Naji@arm.com tRP = '18ns' 7919709SN/A 7929831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 7939831SN/A # Note this is a BL8 DDR device. 7949831SN/A # Requests larger than 32 bytes are broken down into multiple requests 79510146Sandreas.hansson@arm.com # in the controller 7969831SN/A tBURST = '5ns' 7979709SN/A 7989709SN/A # LPDDR3, 4 Gb 7999709SN/A tRFC = '130ns' 8009709SN/A tREFI = '3.9us' 8019709SN/A 8029709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 8039709SN/A tWTR = '7.5ns' 8049709SN/A 80510393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 80610206Sandreas.hansson@arm.com tRTW = '2.5ns' 80710206Sandreas.hansson@arm.com 80810393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 80910393Swendy.elsasser@arm.com tCS = '2.5ns' 81010393Swendy.elsasser@arm.com 8119971SN/A # Activate to activate irrespective of density and speed grade 8129971SN/A tRRD = '10.0ns' 8139971SN/A 8149709SN/A # Irrespective of size, tFAW is 50 ns 8159709SN/A tXAW = '50ns' 8169709SN/A activation_limit = 4 81710430SOmar.Naji@arm.com 81810430SOmar.Naji@arm.com # Current values from datasheet 81910430SOmar.Naji@arm.com IDD0 = '8mA' 82010430SOmar.Naji@arm.com IDD02 = '60mA' 82110430SOmar.Naji@arm.com IDD2N = '0.8mA' 82210430SOmar.Naji@arm.com IDD2N2 = '26mA' 82310430SOmar.Naji@arm.com IDD3N = '2mA' 82410430SOmar.Naji@arm.com IDD3N2 = '34mA' 82510430SOmar.Naji@arm.com IDD4W = '2mA' 82610430SOmar.Naji@arm.com IDD4W2 = '190mA' 82710430SOmar.Naji@arm.com IDD4R = '2mA' 82810430SOmar.Naji@arm.com IDD4R2 = '230mA' 82910430SOmar.Naji@arm.com IDD5 = '28mA' 83010430SOmar.Naji@arm.com IDD52 = '150mA' 83110430SOmar.Naji@arm.com VDD = '1.8V' 83210430SOmar.Naji@arm.com VDD2 = '1.2V' 83310561SOmar.Naji@arm.com 83410561SOmar.Naji@arm.com# A single GDDR5 x64 interface, with 83510561SOmar.Naji@arm.com# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix 83610561SOmar.Naji@arm.com# H5GQ1H24AFR) in a 2x32 configuration. 83710561SOmar.Naji@arm.comclass GDDR5_4000_x64(DRAMCtrl): 83810561SOmar.Naji@arm.com # size of device 83910561SOmar.Naji@arm.com device_size = '128MB' 84010561SOmar.Naji@arm.com 84110561SOmar.Naji@arm.com # 2x32 configuration, 1 device with a 32-bit interface 84210561SOmar.Naji@arm.com device_bus_width = 32 84310561SOmar.Naji@arm.com 84410561SOmar.Naji@arm.com # GDDR5 is a BL8 device 84510561SOmar.Naji@arm.com burst_length = 8 84610561SOmar.Naji@arm.com 84710561SOmar.Naji@arm.com # Each device has a page (row buffer) size of 2Kbits (256Bytes) 84810561SOmar.Naji@arm.com device_rowbuffer_size = '256B' 84910561SOmar.Naji@arm.com 85010561SOmar.Naji@arm.com # 2x32 configuration, so 2 devices 85110561SOmar.Naji@arm.com devices_per_rank = 2 85210561SOmar.Naji@arm.com 85310561SOmar.Naji@arm.com # assume single rank 85410561SOmar.Naji@arm.com ranks_per_channel = 1 85510561SOmar.Naji@arm.com 85610561SOmar.Naji@arm.com # GDDR5 has 4 bank groups 85710561SOmar.Naji@arm.com bank_groups_per_rank = 4 85810561SOmar.Naji@arm.com 85910561SOmar.Naji@arm.com # GDDR5 has 16 banks with 4 bank groups 86010561SOmar.Naji@arm.com banks_per_rank = 16 86110561SOmar.Naji@arm.com 86210561SOmar.Naji@arm.com # 1000 MHz 86310561SOmar.Naji@arm.com tCK = '1ns' 86410561SOmar.Naji@arm.com 86510561SOmar.Naji@arm.com # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz 86610561SOmar.Naji@arm.com # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz ) 86710561SOmar.Naji@arm.com # 8 beats at 4000 MHz = 2 beats at 1000 MHz 86810561SOmar.Naji@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 86910561SOmar.Naji@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 87010561SOmar.Naji@arm.com # delay for bursts to different bank groups (tCCD_S) 87110561SOmar.Naji@arm.com tBURST = '2ns' 87210561SOmar.Naji@arm.com 87310561SOmar.Naji@arm.com # @1000MHz data rate, tCCD_L is 3 CK 87410561SOmar.Naji@arm.com # CAS-to-CAS delay for bursts to the same bank group 87510561SOmar.Naji@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 87610561SOmar.Naji@arm.com # for CAS-to-CAS delay for bursts to different bank groups 87710561SOmar.Naji@arm.com tCCD_L = '3ns'; 87810561SOmar.Naji@arm.com 87910561SOmar.Naji@arm.com tRCD = '12ns' 88010561SOmar.Naji@arm.com 88110561SOmar.Naji@arm.com # tCL is not directly found in datasheet and assumed equal tRCD 88210561SOmar.Naji@arm.com tCL = '12ns' 88310561SOmar.Naji@arm.com 88410561SOmar.Naji@arm.com tRP = '12ns' 88510561SOmar.Naji@arm.com tRAS = '28ns' 88610561SOmar.Naji@arm.com 88710561SOmar.Naji@arm.com # RRD_S (different bank group) 88810561SOmar.Naji@arm.com # RRD_S is 5.5 ns in datasheet. 88910561SOmar.Naji@arm.com # rounded to the next multiple of tCK 89010561SOmar.Naji@arm.com tRRD = '6ns' 89110561SOmar.Naji@arm.com 89210561SOmar.Naji@arm.com # RRD_L (same bank group) 89310561SOmar.Naji@arm.com # RRD_L is 5.5 ns in datasheet. 89410561SOmar.Naji@arm.com # rounded to the next multiple of tCK 89510561SOmar.Naji@arm.com tRRD_L = '6ns' 89610561SOmar.Naji@arm.com 89710561SOmar.Naji@arm.com tXAW = '23ns' 89810561SOmar.Naji@arm.com 89910561SOmar.Naji@arm.com # tXAW < 4 x tRRD. 90010561SOmar.Naji@arm.com # Therefore, activation limit is set to 0 90110561SOmar.Naji@arm.com activation_limit = 0 90210561SOmar.Naji@arm.com 90310561SOmar.Naji@arm.com tRFC = '65ns' 90410561SOmar.Naji@arm.com tWR = '12ns' 90510561SOmar.Naji@arm.com 90610561SOmar.Naji@arm.com # Here using the average of WTR_S and WTR_L 90710561SOmar.Naji@arm.com tWTR = '5ns' 90810561SOmar.Naji@arm.com 90910561SOmar.Naji@arm.com # Read-to-Precharge 2 CK 91010561SOmar.Naji@arm.com tRTP = '2ns' 91110561SOmar.Naji@arm.com 91210561SOmar.Naji@arm.com # Assume 2 cycles 91310561SOmar.Naji@arm.com tRTW = '2ns' 91410561SOmar.Naji@arm.com 91511120Swendy.elsasser@arm.com# A single HBM x128 interface (one command and address bus), with 91611120Swendy.elsasser@arm.com# default timings based on data publically released 91711120Swendy.elsasser@arm.com# ("HBM: Memory Solution for High Performance Processors", MemCon, 2014), 91811120Swendy.elsasser@arm.com# IDD measurement values, and by extrapolating data from other classes. 91911120Swendy.elsasser@arm.com# Architecture values based on published HBM spec 92011120Swendy.elsasser@arm.com# A 4H stack is defined, 2Gb per die for a total of 1GB of memory. 92111120Swendy.elsasser@arm.comclass HBM_1000_4H_x128(DRAMCtrl): 92211120Swendy.elsasser@arm.com # HBM gen1 supports up to 8 128-bit physical channels 92311120Swendy.elsasser@arm.com # Configuration defines a single channel, with the capacity 92411120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 8) based on 2Gb dies 92511120Swendy.elsasser@arm.com # To use all 8 channels, set 'channels' parameter to 8 in 92611120Swendy.elsasser@arm.com # system configuration 92711120Swendy.elsasser@arm.com 92811120Swendy.elsasser@arm.com # 128-bit interface legacy mode 92911120Swendy.elsasser@arm.com device_bus_width = 128 93011120Swendy.elsasser@arm.com 93111120Swendy.elsasser@arm.com # HBM supports BL4 and BL2 (legacy mode only) 93211120Swendy.elsasser@arm.com burst_length = 4 93311120Swendy.elsasser@arm.com 93411120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 2Gb dies is 1GB per stack; 93511120Swendy.elsasser@arm.com # with 8 channels, 128MB per channel 93611120Swendy.elsasser@arm.com device_size = '128MB' 93711120Swendy.elsasser@arm.com 93811120Swendy.elsasser@arm.com device_rowbuffer_size = '2kB' 93911120Swendy.elsasser@arm.com 94011120Swendy.elsasser@arm.com # 1x128 configuration 94111120Swendy.elsasser@arm.com devices_per_rank = 1 94211120Swendy.elsasser@arm.com 94311120Swendy.elsasser@arm.com # HBM does not have a CS pin; set rank to 1 94411120Swendy.elsasser@arm.com ranks_per_channel = 1 94511120Swendy.elsasser@arm.com 94611120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 94711120Swendy.elsasser@arm.com # 2Gb dies have 8 banks 94811120Swendy.elsasser@arm.com banks_per_rank = 8 94911120Swendy.elsasser@arm.com 95011120Swendy.elsasser@arm.com # depending on frequency, bank groups may be required 95111120Swendy.elsasser@arm.com # will always have 4 bank groups when enabled 95211120Swendy.elsasser@arm.com # current specifications do not define the minimum frequency for 95311120Swendy.elsasser@arm.com # bank group architecture 95411120Swendy.elsasser@arm.com # setting bank_groups_per_rank to 0 to disable until range is defined 95511120Swendy.elsasser@arm.com bank_groups_per_rank = 0 95611120Swendy.elsasser@arm.com 95711120Swendy.elsasser@arm.com # 500 MHz for 1Gbps DDR data rate 95811120Swendy.elsasser@arm.com tCK = '2ns' 95911120Swendy.elsasser@arm.com 96011120Swendy.elsasser@arm.com # use values from IDD measurement in JEDEC spec 96111120Swendy.elsasser@arm.com # use tRP value for tRCD and tCL similar to other classes 96211120Swendy.elsasser@arm.com tRP = '15ns' 96311120Swendy.elsasser@arm.com tRCD = '15ns' 96411120Swendy.elsasser@arm.com tCL = '15ns' 96511120Swendy.elsasser@arm.com tRAS = '33ns' 96611120Swendy.elsasser@arm.com 96711120Swendy.elsasser@arm.com # BL2 and BL4 supported, default to BL4 96811120Swendy.elsasser@arm.com # DDR @ 500 MHz means 4 * 2ns / 2 = 4ns 96911120Swendy.elsasser@arm.com tBURST = '4ns' 97011120Swendy.elsasser@arm.com 97111120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 97211120Swendy.elsasser@arm.com tRFC = '160ns' 97311120Swendy.elsasser@arm.com 97411120Swendy.elsasser@arm.com # value for 2Gb device from JEDEC spec 97511120Swendy.elsasser@arm.com tREFI = '3.9us' 97611120Swendy.elsasser@arm.com 97711120Swendy.elsasser@arm.com # extrapolate the following from LPDDR configs, using ns values 97811120Swendy.elsasser@arm.com # to minimize burst length, prefetch differences 97911120Swendy.elsasser@arm.com tWR = '18ns' 98011120Swendy.elsasser@arm.com tRTP = '7.5ns' 98111120Swendy.elsasser@arm.com tWTR = '10ns' 98211120Swendy.elsasser@arm.com 98311120Swendy.elsasser@arm.com # start with 2 cycles turnaround, similar to other memory classes 98411120Swendy.elsasser@arm.com # could be more with variations across the stack 98511120Swendy.elsasser@arm.com tRTW = '4ns' 98611120Swendy.elsasser@arm.com 98711120Swendy.elsasser@arm.com # single rank device, set to 0 98811120Swendy.elsasser@arm.com tCS = '0ns' 98911120Swendy.elsasser@arm.com 99011120Swendy.elsasser@arm.com # from MemCon example, tRRD is 4ns with 2ns tCK 99111120Swendy.elsasser@arm.com tRRD = '4ns' 99211120Swendy.elsasser@arm.com 99311120Swendy.elsasser@arm.com # from MemCon example, tFAW is 30ns with 2ns tCK 99411120Swendy.elsasser@arm.com tXAW = '30ns' 99511120Swendy.elsasser@arm.com activation_limit = 4 99611120Swendy.elsasser@arm.com 99711120Swendy.elsasser@arm.com # 4tCK 99811120Swendy.elsasser@arm.com tXP = '8ns' 99911120Swendy.elsasser@arm.com 100011120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 100111120Swendy.elsasser@arm.com tXS = '168ns' 100211120Swendy.elsasser@arm.com 100311120Swendy.elsasser@arm.com# A single HBM x64 interface (one command and address bus), with 100411120Swendy.elsasser@arm.com# default timings based on HBM gen1 and data publically released 100511120Swendy.elsasser@arm.com# A 4H stack is defined, 8Gb per die for a total of 4GB of memory. 100611120Swendy.elsasser@arm.com# Note: This defines a pseudo-channel with a unique controller 100711120Swendy.elsasser@arm.com# instantiated per pseudo-channel 100811120Swendy.elsasser@arm.com# Stay at same IO rate (1Gbps) to maintain timing relationship with 100911120Swendy.elsasser@arm.com# HBM gen1 class (HBM_1000_4H_x128) where possible 101011120Swendy.elsasser@arm.comclass HBM_1000_4H_x64(HBM_1000_4H_x128): 101111120Swendy.elsasser@arm.com # For HBM gen2 with pseudo-channel mode, configure 2X channels. 101211120Swendy.elsasser@arm.com # Configuration defines a single pseudo channel, with the capacity 101311120Swendy.elsasser@arm.com # set to (full_ stack_capacity / 16) based on 8Gb dies 101411120Swendy.elsasser@arm.com # To use all 16 pseudo channels, set 'channels' parameter to 16 in 101511120Swendy.elsasser@arm.com # system configuration 101611120Swendy.elsasser@arm.com 101711120Swendy.elsasser@arm.com # 64-bit pseudo-channle interface 101811120Swendy.elsasser@arm.com device_bus_width = 64 101911120Swendy.elsasser@arm.com 102011120Swendy.elsasser@arm.com # HBM pseudo-channel only supports BL4 102111120Swendy.elsasser@arm.com burst_length = 4 102211120Swendy.elsasser@arm.com 102311120Swendy.elsasser@arm.com # size of channel in bytes, 4H stack of 8Gb dies is 4GB per stack; 102411120Swendy.elsasser@arm.com # with 16 channels, 256MB per channel 102511120Swendy.elsasser@arm.com device_size = '256MB' 102611120Swendy.elsasser@arm.com 102711120Swendy.elsasser@arm.com # page size is halved with pseudo-channel; maintaining the same same number 102811120Swendy.elsasser@arm.com # of rows per pseudo-channel with 2X banks across 2 channels 102911120Swendy.elsasser@arm.com device_rowbuffer_size = '1kB' 103011120Swendy.elsasser@arm.com 103111120Swendy.elsasser@arm.com # HBM has 8 or 16 banks depending on capacity 103211120Swendy.elsasser@arm.com # Starting with 4Gb dies, 16 banks are defined 103311120Swendy.elsasser@arm.com banks_per_rank = 16 103411120Swendy.elsasser@arm.com 103511120Swendy.elsasser@arm.com # reset tRFC for larger, 8Gb device 103611120Swendy.elsasser@arm.com # use HBM1 4Gb value as a starting point 103711120Swendy.elsasser@arm.com tRFC = '260ns' 103811120Swendy.elsasser@arm.com 103911120Swendy.elsasser@arm.com # start with tRFC + tXP -> 160ns + 8ns = 168ns 104011120Swendy.elsasser@arm.com tXS = '268ns' 104110561SOmar.Naji@arm.com # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns 104210561SOmar.Naji@arm.com tCS = '2ns' 104310561SOmar.Naji@arm.com tREFI = '3.9us' 1044