DRAMCtrl.py revision 10561
110206Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 149831SN/A# All rights reserved. 159831SN/A# 169243SN/A# Redistribution and use in source and binary forms, with or without 179243SN/A# modification, are permitted provided that the following conditions are 189243SN/A# met: redistributions of source code must retain the above copyright 199243SN/A# notice, this list of conditions and the following disclaimer; 209243SN/A# redistributions in binary form must reproduce the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer in the 229243SN/A# documentation and/or other materials provided with the distribution; 239243SN/A# neither the name of the copyright holders nor the names of its 249243SN/A# contributors may be used to endorse or promote products derived from 259243SN/A# this software without specific prior written permission. 269243SN/A# 279243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 289243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 299243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 309243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 319243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 329243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 339243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 349243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 359243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 369243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389243SN/A# 399243SN/A# Authors: Andreas Hansson 409243SN/A# Ani Udipi 419243SN/A 429243SN/Afrom m5.params import * 439243SN/Afrom AbstractMemory import * 449243SN/A 459243SN/A# Enum for memory scheduling algorithms, currently First-Come 469243SN/A# First-Served and a First-Row Hit then First-Come First-Served 479243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 489243SN/A 4910136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5010136SN/A# channel, rank, bank, row and column, respectively, and going from 5110136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210136SN/A# suitable for an open-page policy, optimising for sequential accesses 5310136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5410136SN/A# maximises parallelism. 5510136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 569243SN/A 5710144SN/A# Enum for the page policy, either open, open_adaptive, close, or 5810144SN/A# close_adaptive. 5910144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6010144SN/A 'close_adaptive'] 619243SN/A 6210146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 639243SN/A# that aims to model the most important system-level performance 649243SN/A# effects of a DRAM without getting into too much detail of the DRAM 659243SN/A# itself. 6610146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 6710146Sandreas.hansson@arm.com type = 'DRAMCtrl' 6810146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 699243SN/A 709243SN/A # single-ported on the system interface side, instantiate with a 719243SN/A # bus in front of the controller for multiple ports 729243SN/A port = SlavePort("Slave port") 739243SN/A 7410536Sandreas.hansson@arm.com # the basic configuration of the controller architecture, note 7510536Sandreas.hansson@arm.com # that each entry corresponds to a burst for the specific DRAM 7610536Sandreas.hansson@arm.com # configuration (e.g. x32 with burst length 8 is 32 bytes) and not 7710536Sandreas.hansson@arm.com # the cacheline size or request/packet size 7810145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 799972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 809243SN/A 8110140SN/A # threshold in percent for when to forcefully trigger writes and 8210140SN/A # start emptying the write buffer 8310140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 849972SN/A 8510140SN/A # threshold in percentage for when to start writes if the read 8610140SN/A # queue is empty 8710140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 8810140SN/A 8910140SN/A # minimum write bursts to schedule before switching back to reads 9010140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 9110140SN/A "switching to reads") 929243SN/A 939243SN/A # scheduler, address map and page policy 949489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9510136SN/A addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 9610145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 979243SN/A 9810141SN/A # enforce a limit on the number of accesses per row 9910141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 10010141SN/A "closing"); 10110141SN/A 10210489SOmar.Naji@arm.com # size of DRAM Chip in Bytes 10310489SOmar.Naji@arm.com device_size = Param.MemorySize("Size of DRAM chip") 10410489SOmar.Naji@arm.com 1059726SN/A # pipeline latency of the controller and PHY, split into a 1069726SN/A # frontend part and a backend part, with reads and writes serviced 1079726SN/A # by the queues only seeing the frontend contribution, and reads 1089726SN/A # serviced by the memory seeing the sum of the two 1099726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1109726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1119726SN/A 1129489SN/A # the physical organisation of the DRAM 1139831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1149831SN/A "device/chip") 1159831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1169831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1179831SN/A "device/chip") 1189831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1199489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 12010394Swendy.elsasser@arm.com 12110394Swendy.elsasser@arm.com # default to 0 bank groups per rank, indicating bank group architecture 12210394Swendy.elsasser@arm.com # is not used 12310394Swendy.elsasser@arm.com # update per memory class when bank group architecture is supported 12410394Swendy.elsasser@arm.com bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1259489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1269566SN/A # only used for the address mapping as the controller by 1279566SN/A # construction is a single channel and multiple controllers have 1289566SN/A # to be instantiated for a multi-channel configuration 1299566SN/A channels = Param.Unsigned(1, "Number of channels") 1309489SN/A 13110430SOmar.Naji@arm.com # For power modelling we need to know if the DRAM has a DLL or not 13210430SOmar.Naji@arm.com dll = Param.Bool(True, "DRAM has DLL or not") 13310430SOmar.Naji@arm.com 13410430SOmar.Naji@arm.com # DRAMPower provides in addition to the core power, the possibility to 13510430SOmar.Naji@arm.com # include RD/WR termination and IO power. This calculation assumes some 13610430SOmar.Naji@arm.com # default values. The integration of DRAMPower with gem5 does not include 13710430SOmar.Naji@arm.com # IO and RD/WR termination power by default. This might be added as an 13810430SOmar.Naji@arm.com # additional feature in the future. 13910430SOmar.Naji@arm.com 1409243SN/A # timing behaviour and constraints - all in nanoseconds 1419243SN/A 14210216Sandreas.hansson@arm.com # the base clock period of the DRAM 14310216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 14410216Sandreas.hansson@arm.com 1459243SN/A # the amount of time in nanoseconds from issuing an activate command 1469243SN/A # to the data being available in the row buffer for a read/write 1479489SN/A tRCD = Param.Latency("RAS to CAS delay") 1489243SN/A 1499243SN/A # the time from issuing a read/write command to seeing the actual data 1509489SN/A tCL = Param.Latency("CAS latency") 1519243SN/A 1529243SN/A # minimum time between a precharge and subsequent activate 1539489SN/A tRP = Param.Latency("Row precharge time") 1549243SN/A 1559963SN/A # minimum time between an activate and a precharge to the same row 1569963SN/A tRAS = Param.Latency("ACT to PRE delay") 1579963SN/A 15810210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 15910210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 16010210Sandreas.hansson@arm.com 16110212Sandreas.hansson@arm.com # minimum time between a read and precharge command 16210212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 16310212Sandreas.hansson@arm.com 1649243SN/A # time to complete a burst transfer, typically the burst length 1659243SN/A # divided by two due to the DDR bus, but by making it a parameter 1669243SN/A # it is easier to also evaluate SDR memories like WideIO. 1679831SN/A # This parameter has to account for burst length. 1689831SN/A # Read/Write requests with data size larger than one full burst are broken 16910146Sandreas.hansson@arm.com # down into multiple requests in the controller 17010394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 17110394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 17210394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 1739489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1749243SN/A 17510394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 17610394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 17710394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 17810394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 17910394Swendy.elsasser@arm.com tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 18010394Swendy.elsasser@arm.com 1819243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1829489SN/A tRFC = Param.Latency("Refresh cycle time") 1839243SN/A 1849243SN/A # refresh command interval, how often a "ref" command needs 1859243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1869489SN/A tREFI = Param.Latency("Refresh command interval") 1879243SN/A 18810393Swendy.elsasser@arm.com # write-to-read, same rank turnaround penalty 18910393Swendy.elsasser@arm.com tWTR = Param.Latency("Write to read, same rank switching time") 1909243SN/A 19110393Swendy.elsasser@arm.com # read-to-write, same rank turnaround penalty 19210393Swendy.elsasser@arm.com tRTW = Param.Latency("Read to write, same rank switching time") 19310393Swendy.elsasser@arm.com 19410393Swendy.elsasser@arm.com # rank-to-rank bus delay penalty 19510393Swendy.elsasser@arm.com # this does not correlate to a memory timing parameter and encompasses: 19610393Swendy.elsasser@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 19710393Swendy.elsasser@arm.com # different rank bus delay 19810393Swendy.elsasser@arm.com tCS = Param.Latency("Rank to rank switching time") 19910206Sandreas.hansson@arm.com 2009971SN/A # minimum row activate to row activate delay time 2019971SN/A tRRD = Param.Latency("ACT to ACT delay") 2029971SN/A 20310394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 20410394Swendy.elsasser@arm.com tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 20510394Swendy.elsasser@arm.com 2069488SN/A # time window in which a maximum number of activates are allowed 2079488SN/A # to take place, set to 0 to disable 2089489SN/A tXAW = Param.Latency("X activation window") 2099489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 2109488SN/A 21110430SOmar.Naji@arm.com # time to exit power-down mode 21210430SOmar.Naji@arm.com # Exit power-down to next valid command delay 21310430SOmar.Naji@arm.com tXP = Param.Latency("0ns", "Power-up Delay") 21410430SOmar.Naji@arm.com 21510430SOmar.Naji@arm.com # Exit Powerdown to commands requiring a locked DLL 21610430SOmar.Naji@arm.com tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL") 21710430SOmar.Naji@arm.com 21810430SOmar.Naji@arm.com # time to exit self-refresh mode 21910430SOmar.Naji@arm.com tXS = Param.Latency("0ns", "Self-refresh exit latency") 22010430SOmar.Naji@arm.com 22110430SOmar.Naji@arm.com # time to exit self-refresh mode with locked DLL 22210430SOmar.Naji@arm.com tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL") 22310430SOmar.Naji@arm.com 2249488SN/A # Currently rolled into other params 2259243SN/A ###################################################################### 2269243SN/A 2279963SN/A # tRC - assumed to be tRAS + tRP 2289243SN/A 22910430SOmar.Naji@arm.com # Power Behaviour and Constraints 23010430SOmar.Naji@arm.com # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are 23110430SOmar.Naji@arm.com # defined as VDD and VDD2. Each current is defined for each voltage domain 23210430SOmar.Naji@arm.com # separately. For example, current IDD0 is active-precharge current for 23310430SOmar.Naji@arm.com # voltage domain VDD and current IDD02 is active-precharge current for 23410430SOmar.Naji@arm.com # voltage domain VDD2. 23510430SOmar.Naji@arm.com # By default all currents are set to 0mA. Users who are only interested in 23610430SOmar.Naji@arm.com # the performance of DRAMs can leave them at 0. 23710430SOmar.Naji@arm.com 23810430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current 23910430SOmar.Naji@arm.com IDD0 = Param.Current("0mA", "Active precharge current") 24010430SOmar.Naji@arm.com 24110430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current multiple voltage Range 24210430SOmar.Naji@arm.com IDD02 = Param.Current("0mA", "Active precharge current VDD2") 24310430SOmar.Naji@arm.com 24410430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit 24510430SOmar.Naji@arm.com IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow") 24610430SOmar.Naji@arm.com 24710430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit multiple voltage Range 24810430SOmar.Naji@arm.com IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2") 24910430SOmar.Naji@arm.com 25010430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit 25110430SOmar.Naji@arm.com IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast") 25210430SOmar.Naji@arm.com 25310430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit multiple voltage Range 25410430SOmar.Naji@arm.com IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2") 25510430SOmar.Naji@arm.com 25610430SOmar.Naji@arm.com # Precharge Standby current 25710430SOmar.Naji@arm.com IDD2N = Param.Current("0mA", "Precharge Standby current") 25810430SOmar.Naji@arm.com 25910430SOmar.Naji@arm.com # Precharge Standby current multiple voltage range 26010430SOmar.Naji@arm.com IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2") 26110430SOmar.Naji@arm.com 26210430SOmar.Naji@arm.com # Active Power-down current: slow exit 26310430SOmar.Naji@arm.com IDD3P0 = Param.Current("0mA", "Active Powerdown slow") 26410430SOmar.Naji@arm.com 26510430SOmar.Naji@arm.com # Active Power-down current: slow exit multiple voltage range 26610430SOmar.Naji@arm.com IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2") 26710430SOmar.Naji@arm.com 26810430SOmar.Naji@arm.com # Active Power-down current : fast exit 26910430SOmar.Naji@arm.com IDD3P1 = Param.Current("0mA", "Active Powerdown fast") 27010430SOmar.Naji@arm.com 27110430SOmar.Naji@arm.com # Active Power-down current : fast exit multiple voltage range 27210430SOmar.Naji@arm.com IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2") 27310430SOmar.Naji@arm.com 27410430SOmar.Naji@arm.com # Active Standby current 27510430SOmar.Naji@arm.com IDD3N = Param.Current("0mA", "Active Standby current") 27610430SOmar.Naji@arm.com 27710430SOmar.Naji@arm.com # Active Standby current multiple voltage range 27810430SOmar.Naji@arm.com IDD3N2 = Param.Current("0mA", "Active Standby current VDD2") 27910430SOmar.Naji@arm.com 28010430SOmar.Naji@arm.com # Burst Read Operating Current 28110430SOmar.Naji@arm.com IDD4R = Param.Current("0mA", "READ current") 28210430SOmar.Naji@arm.com 28310430SOmar.Naji@arm.com # Burst Read Operating Current multiple voltage range 28410430SOmar.Naji@arm.com IDD4R2 = Param.Current("0mA", "READ current VDD2") 28510430SOmar.Naji@arm.com 28610430SOmar.Naji@arm.com # Burst Write Operating Current 28710430SOmar.Naji@arm.com IDD4W = Param.Current("0mA", "WRITE current") 28810430SOmar.Naji@arm.com 28910430SOmar.Naji@arm.com # Burst Write Operating Current multiple voltage range 29010430SOmar.Naji@arm.com IDD4W2 = Param.Current("0mA", "WRITE current VDD2") 29110430SOmar.Naji@arm.com 29210430SOmar.Naji@arm.com # Refresh Current 29310430SOmar.Naji@arm.com IDD5 = Param.Current("0mA", "Refresh current") 29410430SOmar.Naji@arm.com 29510430SOmar.Naji@arm.com # Refresh Current multiple voltage range 29610430SOmar.Naji@arm.com IDD52 = Param.Current("0mA", "Refresh current VDD2") 29710430SOmar.Naji@arm.com 29810430SOmar.Naji@arm.com # Self-Refresh Current 29910430SOmar.Naji@arm.com IDD6 = Param.Current("0mA", "Self-refresh Current") 30010430SOmar.Naji@arm.com 30110430SOmar.Naji@arm.com # Self-Refresh Current multiple voltage range 30210430SOmar.Naji@arm.com IDD62 = Param.Current("0mA", "Self-refresh Current VDD2") 30310430SOmar.Naji@arm.com 30410430SOmar.Naji@arm.com # Main voltage range of the DRAM 30510430SOmar.Naji@arm.com VDD = Param.Voltage("0V", "Main Voltage Range") 30610430SOmar.Naji@arm.com 30710430SOmar.Naji@arm.com # Second voltage range defined by some DRAMs 30810430SOmar.Naji@arm.com VDD2 = Param.Voltage("0V", "2nd Voltage Range") 30910430SOmar.Naji@arm.com 31010217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 31110217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 31210430SOmar.Naji@arm.com# an 8x8 configuration. 31310146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 31410489SOmar.Naji@arm.com # size of device in bytes 31510489SOmar.Naji@arm.com device_size = '512MB' 31610489SOmar.Naji@arm.com 3179831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 3189831SN/A device_bus_width = 8 3199831SN/A 3209831SN/A # DDR3 is a BL8 device 3219831SN/A burst_length = 8 3229831SN/A 32310217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 3249831SN/A device_rowbuffer_size = '1kB' 3259831SN/A 3269831SN/A # 8x8 configuration, so 8 devices 3279831SN/A devices_per_rank = 8 3289489SN/A 3299489SN/A # Use two ranks 3309489SN/A ranks_per_channel = 2 3319489SN/A 3329489SN/A # DDR3 has 8 banks in all configurations 3339489SN/A banks_per_rank = 8 3349489SN/A 33510216Sandreas.hansson@arm.com # 800 MHz 33610216Sandreas.hansson@arm.com tCK = '1.25ns' 33710216Sandreas.hansson@arm.com 33810217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 33910217Sandreas.hansson@arm.com tBURST = '5ns' 34010217Sandreas.hansson@arm.com 34110217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 3429489SN/A tRCD = '13.75ns' 3439489SN/A tCL = '13.75ns' 3449489SN/A tRP = '13.75ns' 3459970SN/A tRAS = '35ns' 34610217Sandreas.hansson@arm.com tRRD = '6ns' 34710217Sandreas.hansson@arm.com tXAW = '30ns' 34810217Sandreas.hansson@arm.com activation_limit = 4 34910217Sandreas.hansson@arm.com tRFC = '260ns' 35010217Sandreas.hansson@arm.com 35110210Sandreas.hansson@arm.com tWR = '15ns' 35210217Sandreas.hansson@arm.com 35310217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 35410217Sandreas.hansson@arm.com tWTR = '7.5ns' 35510217Sandreas.hansson@arm.com 35610217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 35710212Sandreas.hansson@arm.com tRTP = '7.5ns' 3589489SN/A 35910393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 36010206Sandreas.hansson@arm.com tRTW = '2.5ns' 36110206Sandreas.hansson@arm.com 36210393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 36310393Swendy.elsasser@arm.com tCS = '2.5ns' 36410393Swendy.elsasser@arm.com 36510217Sandreas.hansson@arm.com # <=85C, half for >85C 36610217Sandreas.hansson@arm.com tREFI = '7.8us' 3679971SN/A 36810430SOmar.Naji@arm.com # Current values from datasheet 36910430SOmar.Naji@arm.com IDD0 = '75mA' 37010430SOmar.Naji@arm.com IDD2N = '50mA' 37110430SOmar.Naji@arm.com IDD3N = '57mA' 37210430SOmar.Naji@arm.com IDD4W = '165mA' 37310430SOmar.Naji@arm.com IDD4R = '187mA' 37410430SOmar.Naji@arm.com IDD5 = '220mA' 37510430SOmar.Naji@arm.com VDD = '1.5V' 37610430SOmar.Naji@arm.com 37710217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 37810217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 37910217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 38010217Sandreas.hansson@arm.com# consistent across the two configurations. 38110217Sandreas.hansson@arm.comclass DDR3_2133_x64(DDR3_1600_x64): 38210217Sandreas.hansson@arm.com # 1066 MHz 38310217Sandreas.hansson@arm.com tCK = '0.938ns' 38410217Sandreas.hansson@arm.com 38510217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 38610217Sandreas.hansson@arm.com tBURST = '3.752ns' 38710217Sandreas.hansson@arm.com 38810217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 38910217Sandreas.hansson@arm.com tRCD = '13.09ns' 39010217Sandreas.hansson@arm.com tCL = '13.09ns' 39110217Sandreas.hansson@arm.com tRP = '13.09ns' 39210217Sandreas.hansson@arm.com tRAS = '33ns' 39310217Sandreas.hansson@arm.com tRRD = '5ns' 39410217Sandreas.hansson@arm.com tXAW = '25ns' 39510217Sandreas.hansson@arm.com 39610430SOmar.Naji@arm.com # Current values from datasheet 39710430SOmar.Naji@arm.com IDD0 = '70mA' 39810430SOmar.Naji@arm.com IDD2N = '37mA' 39910430SOmar.Naji@arm.com IDD3N = '44mA' 40010430SOmar.Naji@arm.com IDD4W = '157mA' 40110430SOmar.Naji@arm.com IDD4R = '191mA' 40210430SOmar.Naji@arm.com IDD5 = '250mA' 40310430SOmar.Naji@arm.com VDD = '1.5V' 40410430SOmar.Naji@arm.com 40510217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 40610430SOmar.Naji@arm.com# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8) 40710430SOmar.Naji@arm.com# in an 8x8 configuration. 40810217Sandreas.hansson@arm.comclass DDR4_2400_x64(DRAMCtrl): 40910489SOmar.Naji@arm.com # size of device 41010489SOmar.Naji@arm.com device_size = '512MB' 41110489SOmar.Naji@arm.com 41210217Sandreas.hansson@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 41310217Sandreas.hansson@arm.com device_bus_width = 8 41410217Sandreas.hansson@arm.com 41510217Sandreas.hansson@arm.com # DDR4 is a BL8 device 41610217Sandreas.hansson@arm.com burst_length = 8 41710217Sandreas.hansson@arm.com 41810217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 41910217Sandreas.hansson@arm.com device_rowbuffer_size = '1kB' 42010217Sandreas.hansson@arm.com 42110217Sandreas.hansson@arm.com # 8x8 configuration, so 8 devices 42210217Sandreas.hansson@arm.com devices_per_rank = 8 42310217Sandreas.hansson@arm.com 42410430SOmar.Naji@arm.com # Match our DDR3 configurations which is dual rank 42510430SOmar.Naji@arm.com ranks_per_channel = 2 42610217Sandreas.hansson@arm.com 42710394Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 42810394Swendy.elsasser@arm.com # Set to 4 for x4, x8 case 42910394Swendy.elsasser@arm.com bank_groups_per_rank = 4 43010394Swendy.elsasser@arm.com 43110217Sandreas.hansson@arm.com # DDR4 has 16 banks (4 bank groups) in all 43210217Sandreas.hansson@arm.com # configurations. Currently we do not capture the additional 43310217Sandreas.hansson@arm.com # constraints incurred by the bank groups 43410217Sandreas.hansson@arm.com banks_per_rank = 16 43510217Sandreas.hansson@arm.com 43610217Sandreas.hansson@arm.com # 1200 MHz 43710217Sandreas.hansson@arm.com tCK = '0.833ns' 43810217Sandreas.hansson@arm.com 43910217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 44010394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 44110394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 44210394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 44310217Sandreas.hansson@arm.com tBURST = '3.333ns' 44410217Sandreas.hansson@arm.com 44510394Swendy.elsasser@arm.com # @2400 data rate, tCCD_L is 6 CK 44610394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 44710394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 44810394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 44910394Swendy.elsasser@arm.com tCCD_L = '5ns'; 45010394Swendy.elsasser@arm.com 45110217Sandreas.hansson@arm.com # DDR4-2400 17-17-17 45210217Sandreas.hansson@arm.com tRCD = '14.16ns' 45310217Sandreas.hansson@arm.com tCL = '14.16ns' 45410217Sandreas.hansson@arm.com tRP = '14.16ns' 45510217Sandreas.hansson@arm.com tRAS = '32ns' 45610217Sandreas.hansson@arm.com 45710394Swendy.elsasser@arm.com # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns) 45810394Swendy.elsasser@arm.com tRRD = '3.3ns' 45910394Swendy.elsasser@arm.com 46010394Swendy.elsasser@arm.com # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 46110394Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 46210394Swendy.elsasser@arm.com 46310217Sandreas.hansson@arm.com tXAW = '21ns' 4649489SN/A activation_limit = 4 46510430SOmar.Naji@arm.com tRFC = '350ns' 4669489SN/A 46710217Sandreas.hansson@arm.com tWR = '15ns' 46810217Sandreas.hansson@arm.com 46910217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 47010217Sandreas.hansson@arm.com tWTR = '5ns' 47110217Sandreas.hansson@arm.com 47210217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 47310217Sandreas.hansson@arm.com tRTP = '7.5ns' 47410217Sandreas.hansson@arm.com 47510393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 47610217Sandreas.hansson@arm.com tRTW = '1.666ns' 47710217Sandreas.hansson@arm.com 47810393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 47910393Swendy.elsasser@arm.com tCS = '1.666ns' 48010393Swendy.elsasser@arm.com 48110217Sandreas.hansson@arm.com # <=85C, half for >85C 48210217Sandreas.hansson@arm.com tREFI = '7.8us' 4839489SN/A 48410430SOmar.Naji@arm.com # Current values from datasheet 48510430SOmar.Naji@arm.com IDD0 = '64mA' 48610430SOmar.Naji@arm.com IDD02 = '4mA' 48710430SOmar.Naji@arm.com IDD2N = '50mA' 48810430SOmar.Naji@arm.com IDD3N = '67mA' 48910430SOmar.Naji@arm.com IDD3N2 = '3mA' 49010430SOmar.Naji@arm.com IDD4W = '180mA' 49110430SOmar.Naji@arm.com IDD4R = '160mA' 49210430SOmar.Naji@arm.com IDD5 = '192mA' 49310430SOmar.Naji@arm.com VDD = '1.2V' 49410430SOmar.Naji@arm.com VDD2 = '2.5V' 49510430SOmar.Naji@arm.com 4969728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 49710430SOmar.Naji@arm.com# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 49810430SOmar.Naji@arm.com# in a 1x32 configuration. 49910146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 50010430SOmar.Naji@arm.com # No DLL in LPDDR2 50110430SOmar.Naji@arm.com dll = False 50210430SOmar.Naji@arm.com 50310489SOmar.Naji@arm.com # size of device 50410489SOmar.Naji@arm.com device_size = '512MB' 50510489SOmar.Naji@arm.com 5069831SN/A # 1x32 configuration, 1 device with a 32-bit interface 5079831SN/A device_bus_width = 32 5089831SN/A 5099831SN/A # LPDDR2_S4 is a BL4 and BL8 device 5109831SN/A burst_length = 8 5119831SN/A 5129831SN/A # Each device has a page (row buffer) size of 1KB 5139831SN/A # (this depends on the memory density) 5149831SN/A device_rowbuffer_size = '1kB' 5159831SN/A 5169831SN/A # 1x32 configuration, so 1 device 5179831SN/A devices_per_rank = 1 5189489SN/A 5199708SN/A # Use a single rank 5209708SN/A ranks_per_channel = 1 5219489SN/A 5229489SN/A # LPDDR2-S4 has 8 banks in all configurations 5239489SN/A banks_per_rank = 8 5249489SN/A 52510216Sandreas.hansson@arm.com # 533 MHz 52610216Sandreas.hansson@arm.com tCK = '1.876ns' 52710216Sandreas.hansson@arm.com 5289489SN/A # Fixed at 15 ns 5299489SN/A tRCD = '15ns' 5309489SN/A 5319489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 5329489SN/A tCL = '15ns' 5339489SN/A 5349728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 5359728SN/A tRP = '15ns' 5369489SN/A 5379970SN/A tRAS = '42ns' 53810210Sandreas.hansson@arm.com tWR = '15ns' 5399963SN/A 54010430SOmar.Naji@arm.com tRTP = '7.5ns' 54110212Sandreas.hansson@arm.com 5429831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 5439831SN/A # Note this is a BL8 DDR device. 5449831SN/A # Requests larger than 32 bytes are broken down into multiple requests 54510146Sandreas.hansson@arm.com # in the controller 5469831SN/A tBURST = '7.5ns' 5479489SN/A 5489708SN/A # LPDDR2-S4, 4 Gbit 5499489SN/A tRFC = '130ns' 5509489SN/A tREFI = '3.9us' 5519489SN/A 5529489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 5539489SN/A tWTR = '7.5ns' 5549489SN/A 55510393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 55610206Sandreas.hansson@arm.com tRTW = '3.75ns' 55710206Sandreas.hansson@arm.com 55810393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 55910393Swendy.elsasser@arm.com tCS = '3.75ns' 56010393Swendy.elsasser@arm.com 5619971SN/A # Activate to activate irrespective of density and speed grade 5629971SN/A tRRD = '10.0ns' 5639971SN/A 5649708SN/A # Irrespective of density, tFAW is 50 ns 5659489SN/A tXAW = '50ns' 5669489SN/A activation_limit = 4 5679664SN/A 56810430SOmar.Naji@arm.com # Current values from datasheet 56910430SOmar.Naji@arm.com IDD0 = '15mA' 57010430SOmar.Naji@arm.com IDD02 = '70mA' 57110430SOmar.Naji@arm.com IDD2N = '2mA' 57210430SOmar.Naji@arm.com IDD2N2 = '30mA' 57310430SOmar.Naji@arm.com IDD3N = '2.5mA' 57410430SOmar.Naji@arm.com IDD3N2 = '30mA' 57510430SOmar.Naji@arm.com IDD4W = '10mA' 57610430SOmar.Naji@arm.com IDD4W2 = '190mA' 57710430SOmar.Naji@arm.com IDD4R = '3mA' 57810430SOmar.Naji@arm.com IDD4R2 = '220mA' 57910430SOmar.Naji@arm.com IDD5 = '40mA' 58010430SOmar.Naji@arm.com IDD52 = '150mA' 58110430SOmar.Naji@arm.com VDD = '1.8V' 58210430SOmar.Naji@arm.com VDD2 = '1.2V' 58310430SOmar.Naji@arm.com 5849728SN/A# A single WideIO x128 interface (one command and address bus), with 5859728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 58610146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 58710430SOmar.Naji@arm.com # No DLL for WideIO 58810430SOmar.Naji@arm.com dll = False 58910430SOmar.Naji@arm.com 59010489SOmar.Naji@arm.com # size of device 59110489SOmar.Naji@arm.com device_size = '1024MB' 59210489SOmar.Naji@arm.com 5939831SN/A # 1x128 configuration, 1 device with a 128-bit interface 5949831SN/A device_bus_width = 128 5959831SN/A 5969831SN/A # This is a BL4 device 5979831SN/A burst_length = 4 5989831SN/A 5999831SN/A # Each device has a page (row buffer) size of 4KB 6009831SN/A # (this depends on the memory density) 6019831SN/A device_rowbuffer_size = '4kB' 6029831SN/A 6039831SN/A # 1x128 configuration, so 1 device 6049831SN/A devices_per_rank = 1 6059664SN/A 6069664SN/A # Use one rank for a one-high die stack 6079664SN/A ranks_per_channel = 1 6089664SN/A 6099664SN/A # WideIO has 4 banks in all configurations 6109664SN/A banks_per_rank = 4 6119664SN/A 61210216Sandreas.hansson@arm.com # 200 MHz 61310216Sandreas.hansson@arm.com tCK = '5ns' 61410216Sandreas.hansson@arm.com 6159664SN/A # WIO-200 6169664SN/A tRCD = '18ns' 6179664SN/A tCL = '18ns' 6189664SN/A tRP = '18ns' 6199970SN/A tRAS = '42ns' 62010210Sandreas.hansson@arm.com tWR = '15ns' 62110212Sandreas.hansson@arm.com # Read to precharge is same as the burst 62210212Sandreas.hansson@arm.com tRTP = '20ns' 6239664SN/A 6249831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 6259831SN/A # Note this is a BL4 SDR device. 6269664SN/A tBURST = '20ns' 6279664SN/A 6289664SN/A # WIO 8 Gb 6299664SN/A tRFC = '210ns' 6309664SN/A 6319664SN/A # WIO 8 Gb, <=85C, half for >85C 6329664SN/A tREFI = '3.9us' 6339664SN/A 6349664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 6359664SN/A tWTR = '15ns' 6369664SN/A 63710393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 63810206Sandreas.hansson@arm.com tRTW = '10ns' 63910206Sandreas.hansson@arm.com 64010393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 64110393Swendy.elsasser@arm.com tCS = '10ns' 64210393Swendy.elsasser@arm.com 6439971SN/A # Activate to activate irrespective of density and speed grade 6449971SN/A tRRD = '10.0ns' 6459971SN/A 6469664SN/A # Two instead of four activation window 6479664SN/A tXAW = '50ns' 6489664SN/A activation_limit = 2 6499709SN/A 65010430SOmar.Naji@arm.com # The WideIO specification does not provide current information 65110430SOmar.Naji@arm.com 6529728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 65310430SOmar.Naji@arm.com# default timings based on a LPDDR3-1600 4 Gbit part (Micron 65410430SOmar.Naji@arm.com# EDF8132A1MC) in a 1x32 configuration. 65510146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 65610430SOmar.Naji@arm.com # No DLL for LPDDR3 65710430SOmar.Naji@arm.com dll = False 65810430SOmar.Naji@arm.com 65910489SOmar.Naji@arm.com # size of device 66010489SOmar.Naji@arm.com device_size = '512MB' 66110489SOmar.Naji@arm.com 6629831SN/A # 1x32 configuration, 1 device with a 32-bit interface 6639831SN/A device_bus_width = 32 6649831SN/A 6659831SN/A # LPDDR3 is a BL8 device 6669831SN/A burst_length = 8 6679831SN/A 6689976SN/A # Each device has a page (row buffer) size of 4KB 6699976SN/A device_rowbuffer_size = '4kB' 6709831SN/A 6719831SN/A # 1x32 configuration, so 1 device 6729831SN/A devices_per_rank = 1 6739709SN/A 67410430SOmar.Naji@arm.com # Technically the datasheet is a dual-rank package, but for 67510430SOmar.Naji@arm.com # comparison with the LPDDR2 config we stick to a single rank 6769709SN/A ranks_per_channel = 1 6779709SN/A 6789709SN/A # LPDDR3 has 8 banks in all configurations 6799709SN/A banks_per_rank = 8 6809709SN/A 68110216Sandreas.hansson@arm.com # 800 MHz 68210216Sandreas.hansson@arm.com tCK = '1.25ns' 68310216Sandreas.hansson@arm.com 68410430SOmar.Naji@arm.com tRCD = '18ns' 6859709SN/A 6869709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 6879709SN/A tCL = '15ns' 6889709SN/A 6899970SN/A tRAS = '42ns' 69010210Sandreas.hansson@arm.com tWR = '15ns' 6919963SN/A 69210212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 69310212Sandreas.hansson@arm.com tRTP = '7.5ns' 69410212Sandreas.hansson@arm.com 69510430SOmar.Naji@arm.com # Pre-charge one bank 18 ns (all banks 21 ns) 69610430SOmar.Naji@arm.com tRP = '18ns' 6979709SN/A 6989831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 6999831SN/A # Note this is a BL8 DDR device. 7009831SN/A # Requests larger than 32 bytes are broken down into multiple requests 70110146Sandreas.hansson@arm.com # in the controller 7029831SN/A tBURST = '5ns' 7039709SN/A 7049709SN/A # LPDDR3, 4 Gb 7059709SN/A tRFC = '130ns' 7069709SN/A tREFI = '3.9us' 7079709SN/A 7089709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 7099709SN/A tWTR = '7.5ns' 7109709SN/A 71110393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 71210206Sandreas.hansson@arm.com tRTW = '2.5ns' 71310206Sandreas.hansson@arm.com 71410393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 71510393Swendy.elsasser@arm.com tCS = '2.5ns' 71610393Swendy.elsasser@arm.com 7179971SN/A # Activate to activate irrespective of density and speed grade 7189971SN/A tRRD = '10.0ns' 7199971SN/A 7209709SN/A # Irrespective of size, tFAW is 50 ns 7219709SN/A tXAW = '50ns' 7229709SN/A activation_limit = 4 72310430SOmar.Naji@arm.com 72410430SOmar.Naji@arm.com # Current values from datasheet 72510430SOmar.Naji@arm.com IDD0 = '8mA' 72610430SOmar.Naji@arm.com IDD02 = '60mA' 72710430SOmar.Naji@arm.com IDD2N = '0.8mA' 72810430SOmar.Naji@arm.com IDD2N2 = '26mA' 72910430SOmar.Naji@arm.com IDD3N = '2mA' 73010430SOmar.Naji@arm.com IDD3N2 = '34mA' 73110430SOmar.Naji@arm.com IDD4W = '2mA' 73210430SOmar.Naji@arm.com IDD4W2 = '190mA' 73310430SOmar.Naji@arm.com IDD4R = '2mA' 73410430SOmar.Naji@arm.com IDD4R2 = '230mA' 73510430SOmar.Naji@arm.com IDD5 = '28mA' 73610430SOmar.Naji@arm.com IDD52 = '150mA' 73710430SOmar.Naji@arm.com VDD = '1.8V' 73810430SOmar.Naji@arm.com VDD2 = '1.2V' 73910561SOmar.Naji@arm.com 74010561SOmar.Naji@arm.com# A single GDDR5 x64 interface, with 74110561SOmar.Naji@arm.com# default timings based on a GDDR5-4000 1 Gbit part (SK Hynix 74210561SOmar.Naji@arm.com# H5GQ1H24AFR) in a 2x32 configuration. 74310561SOmar.Naji@arm.comclass GDDR5_4000_x64(DRAMCtrl): 74410561SOmar.Naji@arm.com # size of device 74510561SOmar.Naji@arm.com device_size = '128MB' 74610561SOmar.Naji@arm.com 74710561SOmar.Naji@arm.com # 2x32 configuration, 1 device with a 32-bit interface 74810561SOmar.Naji@arm.com device_bus_width = 32 74910561SOmar.Naji@arm.com 75010561SOmar.Naji@arm.com # GDDR5 is a BL8 device 75110561SOmar.Naji@arm.com burst_length = 8 75210561SOmar.Naji@arm.com 75310561SOmar.Naji@arm.com # Each device has a page (row buffer) size of 2Kbits (256Bytes) 75410561SOmar.Naji@arm.com device_rowbuffer_size = '256B' 75510561SOmar.Naji@arm.com 75610561SOmar.Naji@arm.com # 2x32 configuration, so 2 devices 75710561SOmar.Naji@arm.com devices_per_rank = 2 75810561SOmar.Naji@arm.com 75910561SOmar.Naji@arm.com # assume single rank 76010561SOmar.Naji@arm.com ranks_per_channel = 1 76110561SOmar.Naji@arm.com 76210561SOmar.Naji@arm.com # GDDR5 has 4 bank groups 76310561SOmar.Naji@arm.com bank_groups_per_rank = 4 76410561SOmar.Naji@arm.com 76510561SOmar.Naji@arm.com # GDDR5 has 16 banks with 4 bank groups 76610561SOmar.Naji@arm.com banks_per_rank = 16 76710561SOmar.Naji@arm.com 76810561SOmar.Naji@arm.com # 1000 MHz 76910561SOmar.Naji@arm.com tCK = '1ns' 77010561SOmar.Naji@arm.com 77110561SOmar.Naji@arm.com # 8 beats across an x64 interface translates to 2 clocks @ 1000 MHz 77210561SOmar.Naji@arm.com # Data bus runs @2000 Mhz => DDR ( data runs at 4000 MHz ) 77310561SOmar.Naji@arm.com # 8 beats at 4000 MHz = 2 beats at 1000 MHz 77410561SOmar.Naji@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 77510561SOmar.Naji@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 77610561SOmar.Naji@arm.com # delay for bursts to different bank groups (tCCD_S) 77710561SOmar.Naji@arm.com tBURST = '2ns' 77810561SOmar.Naji@arm.com 77910561SOmar.Naji@arm.com # @1000MHz data rate, tCCD_L is 3 CK 78010561SOmar.Naji@arm.com # CAS-to-CAS delay for bursts to the same bank group 78110561SOmar.Naji@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 78210561SOmar.Naji@arm.com # for CAS-to-CAS delay for bursts to different bank groups 78310561SOmar.Naji@arm.com tCCD_L = '3ns'; 78410561SOmar.Naji@arm.com 78510561SOmar.Naji@arm.com tRCD = '12ns' 78610561SOmar.Naji@arm.com 78710561SOmar.Naji@arm.com # tCL is not directly found in datasheet and assumed equal tRCD 78810561SOmar.Naji@arm.com tCL = '12ns' 78910561SOmar.Naji@arm.com 79010561SOmar.Naji@arm.com tRP = '12ns' 79110561SOmar.Naji@arm.com tRAS = '28ns' 79210561SOmar.Naji@arm.com 79310561SOmar.Naji@arm.com # RRD_S (different bank group) 79410561SOmar.Naji@arm.com # RRD_S is 5.5 ns in datasheet. 79510561SOmar.Naji@arm.com # rounded to the next multiple of tCK 79610561SOmar.Naji@arm.com tRRD = '6ns' 79710561SOmar.Naji@arm.com 79810561SOmar.Naji@arm.com # RRD_L (same bank group) 79910561SOmar.Naji@arm.com # RRD_L is 5.5 ns in datasheet. 80010561SOmar.Naji@arm.com # rounded to the next multiple of tCK 80110561SOmar.Naji@arm.com tRRD_L = '6ns' 80210561SOmar.Naji@arm.com 80310561SOmar.Naji@arm.com tXAW = '23ns' 80410561SOmar.Naji@arm.com 80510561SOmar.Naji@arm.com # tXAW < 4 x tRRD. 80610561SOmar.Naji@arm.com # Therefore, activation limit is set to 0 80710561SOmar.Naji@arm.com activation_limit = 0 80810561SOmar.Naji@arm.com 80910561SOmar.Naji@arm.com tRFC = '65ns' 81010561SOmar.Naji@arm.com tWR = '12ns' 81110561SOmar.Naji@arm.com 81210561SOmar.Naji@arm.com # Here using the average of WTR_S and WTR_L 81310561SOmar.Naji@arm.com tWTR = '5ns' 81410561SOmar.Naji@arm.com 81510561SOmar.Naji@arm.com # Read-to-Precharge 2 CK 81610561SOmar.Naji@arm.com tRTP = '2ns' 81710561SOmar.Naji@arm.com 81810561SOmar.Naji@arm.com # Assume 2 cycles 81910561SOmar.Naji@arm.com tRTW = '2ns' 82010561SOmar.Naji@arm.com 82110561SOmar.Naji@arm.com # Default different rank bus delay to 2 CK, @1000 MHz = 2 ns 82210561SOmar.Naji@arm.com tCS = '2ns' 82310561SOmar.Naji@arm.com tREFI = '3.9us' 824