DRAMCtrl.py revision 10430
110206Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 149831SN/A# All rights reserved. 159831SN/A# 169243SN/A# Redistribution and use in source and binary forms, with or without 179243SN/A# modification, are permitted provided that the following conditions are 189243SN/A# met: redistributions of source code must retain the above copyright 199243SN/A# notice, this list of conditions and the following disclaimer; 209243SN/A# redistributions in binary form must reproduce the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer in the 229243SN/A# documentation and/or other materials provided with the distribution; 239243SN/A# neither the name of the copyright holders nor the names of its 249243SN/A# contributors may be used to endorse or promote products derived from 259243SN/A# this software without specific prior written permission. 269243SN/A# 279243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 289243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 299243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 309243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 319243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 329243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 339243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 349243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 359243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 369243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389243SN/A# 399243SN/A# Authors: Andreas Hansson 409243SN/A# Ani Udipi 419243SN/A 429243SN/Afrom m5.params import * 439243SN/Afrom AbstractMemory import * 449243SN/A 459243SN/A# Enum for memory scheduling algorithms, currently First-Come 469243SN/A# First-Served and a First-Row Hit then First-Come First-Served 479243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 489243SN/A 4910136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5010136SN/A# channel, rank, bank, row and column, respectively, and going from 5110136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210136SN/A# suitable for an open-page policy, optimising for sequential accesses 5310136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5410136SN/A# maximises parallelism. 5510136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 569243SN/A 5710144SN/A# Enum for the page policy, either open, open_adaptive, close, or 5810144SN/A# close_adaptive. 5910144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6010144SN/A 'close_adaptive'] 619243SN/A 6210146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 639243SN/A# that aims to model the most important system-level performance 649243SN/A# effects of a DRAM without getting into too much detail of the DRAM 659243SN/A# itself. 6610146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 6710146Sandreas.hansson@arm.com type = 'DRAMCtrl' 6810146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 699243SN/A 709243SN/A # single-ported on the system interface side, instantiate with a 719243SN/A # bus in front of the controller for multiple ports 729243SN/A port = SlavePort("Slave port") 739243SN/A 749243SN/A # the basic configuration of the controller architecture 7510145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 769972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 779243SN/A 7810140SN/A # threshold in percent for when to forcefully trigger writes and 7910140SN/A # start emptying the write buffer 8010140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 819972SN/A 8210140SN/A # threshold in percentage for when to start writes if the read 8310140SN/A # queue is empty 8410140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 8510140SN/A 8610140SN/A # minimum write bursts to schedule before switching back to reads 8710140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 8810140SN/A "switching to reads") 899243SN/A 909243SN/A # scheduler, address map and page policy 919489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9210136SN/A addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 9310145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 949243SN/A 9510141SN/A # enforce a limit on the number of accesses per row 9610141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 9710141SN/A "closing"); 9810141SN/A 999726SN/A # pipeline latency of the controller and PHY, split into a 1009726SN/A # frontend part and a backend part, with reads and writes serviced 1019726SN/A # by the queues only seeing the frontend contribution, and reads 1029726SN/A # serviced by the memory seeing the sum of the two 1039726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1049726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1059726SN/A 1069489SN/A # the physical organisation of the DRAM 1079831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1089831SN/A "device/chip") 1099831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1109831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1119831SN/A "device/chip") 1129831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1139489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 11410394Swendy.elsasser@arm.com 11510394Swendy.elsasser@arm.com # default to 0 bank groups per rank, indicating bank group architecture 11610394Swendy.elsasser@arm.com # is not used 11710394Swendy.elsasser@arm.com # update per memory class when bank group architecture is supported 11810394Swendy.elsasser@arm.com bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1199489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1209566SN/A # only used for the address mapping as the controller by 1219566SN/A # construction is a single channel and multiple controllers have 1229566SN/A # to be instantiated for a multi-channel configuration 1239566SN/A channels = Param.Unsigned(1, "Number of channels") 1249489SN/A 12510430SOmar.Naji@arm.com # For power modelling we need to know if the DRAM has a DLL or not 12610430SOmar.Naji@arm.com dll = Param.Bool(True, "DRAM has DLL or not") 12710430SOmar.Naji@arm.com 12810430SOmar.Naji@arm.com # DRAMPower provides in addition to the core power, the possibility to 12910430SOmar.Naji@arm.com # include RD/WR termination and IO power. This calculation assumes some 13010430SOmar.Naji@arm.com # default values. The integration of DRAMPower with gem5 does not include 13110430SOmar.Naji@arm.com # IO and RD/WR termination power by default. This might be added as an 13210430SOmar.Naji@arm.com # additional feature in the future. 13310430SOmar.Naji@arm.com 1349243SN/A # timing behaviour and constraints - all in nanoseconds 1359243SN/A 13610216Sandreas.hansson@arm.com # the base clock period of the DRAM 13710216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 13810216Sandreas.hansson@arm.com 1399243SN/A # the amount of time in nanoseconds from issuing an activate command 1409243SN/A # to the data being available in the row buffer for a read/write 1419489SN/A tRCD = Param.Latency("RAS to CAS delay") 1429243SN/A 1439243SN/A # the time from issuing a read/write command to seeing the actual data 1449489SN/A tCL = Param.Latency("CAS latency") 1459243SN/A 1469243SN/A # minimum time between a precharge and subsequent activate 1479489SN/A tRP = Param.Latency("Row precharge time") 1489243SN/A 1499963SN/A # minimum time between an activate and a precharge to the same row 1509963SN/A tRAS = Param.Latency("ACT to PRE delay") 1519963SN/A 15210210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 15310210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 15410210Sandreas.hansson@arm.com 15510212Sandreas.hansson@arm.com # minimum time between a read and precharge command 15610212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 15710212Sandreas.hansson@arm.com 1589243SN/A # time to complete a burst transfer, typically the burst length 1599243SN/A # divided by two due to the DDR bus, but by making it a parameter 1609243SN/A # it is easier to also evaluate SDR memories like WideIO. 1619831SN/A # This parameter has to account for burst length. 1629831SN/A # Read/Write requests with data size larger than one full burst are broken 16310146Sandreas.hansson@arm.com # down into multiple requests in the controller 16410394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 16510394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 16610394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 1679489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1689243SN/A 16910394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 17010394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 17110394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 17210394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 17310394Swendy.elsasser@arm.com tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 17410394Swendy.elsasser@arm.com 1759243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1769489SN/A tRFC = Param.Latency("Refresh cycle time") 1779243SN/A 1789243SN/A # refresh command interval, how often a "ref" command needs 1799243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1809489SN/A tREFI = Param.Latency("Refresh command interval") 1819243SN/A 18210393Swendy.elsasser@arm.com # write-to-read, same rank turnaround penalty 18310393Swendy.elsasser@arm.com tWTR = Param.Latency("Write to read, same rank switching time") 1849243SN/A 18510393Swendy.elsasser@arm.com # read-to-write, same rank turnaround penalty 18610393Swendy.elsasser@arm.com tRTW = Param.Latency("Read to write, same rank switching time") 18710393Swendy.elsasser@arm.com 18810393Swendy.elsasser@arm.com # rank-to-rank bus delay penalty 18910393Swendy.elsasser@arm.com # this does not correlate to a memory timing parameter and encompasses: 19010393Swendy.elsasser@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 19110393Swendy.elsasser@arm.com # different rank bus delay 19210393Swendy.elsasser@arm.com tCS = Param.Latency("Rank to rank switching time") 19310206Sandreas.hansson@arm.com 1949971SN/A # minimum row activate to row activate delay time 1959971SN/A tRRD = Param.Latency("ACT to ACT delay") 1969971SN/A 19710394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 19810394Swendy.elsasser@arm.com tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 19910394Swendy.elsasser@arm.com 2009488SN/A # time window in which a maximum number of activates are allowed 2019488SN/A # to take place, set to 0 to disable 2029489SN/A tXAW = Param.Latency("X activation window") 2039489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 2049488SN/A 20510430SOmar.Naji@arm.com # time to exit power-down mode 20610430SOmar.Naji@arm.com # Exit power-down to next valid command delay 20710430SOmar.Naji@arm.com tXP = Param.Latency("0ns", "Power-up Delay") 20810430SOmar.Naji@arm.com 20910430SOmar.Naji@arm.com # Exit Powerdown to commands requiring a locked DLL 21010430SOmar.Naji@arm.com tXPDLL = Param.Latency("0ns", "Power-up Delay with locked DLL") 21110430SOmar.Naji@arm.com 21210430SOmar.Naji@arm.com # time to exit self-refresh mode 21310430SOmar.Naji@arm.com tXS = Param.Latency("0ns", "Self-refresh exit latency") 21410430SOmar.Naji@arm.com 21510430SOmar.Naji@arm.com # time to exit self-refresh mode with locked DLL 21610430SOmar.Naji@arm.com tXSDLL = Param.Latency("0ns", "Self-refresh exit latency DLL") 21710430SOmar.Naji@arm.com 2189488SN/A # Currently rolled into other params 2199243SN/A ###################################################################### 2209243SN/A 2219963SN/A # tRC - assumed to be tRAS + tRP 2229243SN/A 22310430SOmar.Naji@arm.com # Power Behaviour and Constraints 22410430SOmar.Naji@arm.com # DRAMs like LPDDR and WideIO have 2 external voltage domains. These are 22510430SOmar.Naji@arm.com # defined as VDD and VDD2. Each current is defined for each voltage domain 22610430SOmar.Naji@arm.com # separately. For example, current IDD0 is active-precharge current for 22710430SOmar.Naji@arm.com # voltage domain VDD and current IDD02 is active-precharge current for 22810430SOmar.Naji@arm.com # voltage domain VDD2. 22910430SOmar.Naji@arm.com # By default all currents are set to 0mA. Users who are only interested in 23010430SOmar.Naji@arm.com # the performance of DRAMs can leave them at 0. 23110430SOmar.Naji@arm.com 23210430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current 23310430SOmar.Naji@arm.com IDD0 = Param.Current("0mA", "Active precharge current") 23410430SOmar.Naji@arm.com 23510430SOmar.Naji@arm.com # Operating 1 Bank Active-Precharge current multiple voltage Range 23610430SOmar.Naji@arm.com IDD02 = Param.Current("0mA", "Active precharge current VDD2") 23710430SOmar.Naji@arm.com 23810430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit 23910430SOmar.Naji@arm.com IDD2P0 = Param.Current("0mA", "Precharge Powerdown slow") 24010430SOmar.Naji@arm.com 24110430SOmar.Naji@arm.com # Precharge Power-down Current: Slow exit multiple voltage Range 24210430SOmar.Naji@arm.com IDD2P02 = Param.Current("0mA", "Precharge Powerdown slow VDD2") 24310430SOmar.Naji@arm.com 24410430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit 24510430SOmar.Naji@arm.com IDD2P1 = Param.Current("0mA", "Precharge Powerdown fast") 24610430SOmar.Naji@arm.com 24710430SOmar.Naji@arm.com # Precharge Power-down Current: Fast exit multiple voltage Range 24810430SOmar.Naji@arm.com IDD2P12 = Param.Current("0mA", "Precharge Powerdown fast VDD2") 24910430SOmar.Naji@arm.com 25010430SOmar.Naji@arm.com # Precharge Standby current 25110430SOmar.Naji@arm.com IDD2N = Param.Current("0mA", "Precharge Standby current") 25210430SOmar.Naji@arm.com 25310430SOmar.Naji@arm.com # Precharge Standby current multiple voltage range 25410430SOmar.Naji@arm.com IDD2N2 = Param.Current("0mA", "Precharge Standby current VDD2") 25510430SOmar.Naji@arm.com 25610430SOmar.Naji@arm.com # Active Power-down current: slow exit 25710430SOmar.Naji@arm.com IDD3P0 = Param.Current("0mA", "Active Powerdown slow") 25810430SOmar.Naji@arm.com 25910430SOmar.Naji@arm.com # Active Power-down current: slow exit multiple voltage range 26010430SOmar.Naji@arm.com IDD3P02 = Param.Current("0mA", "Active Powerdown slow VDD2") 26110430SOmar.Naji@arm.com 26210430SOmar.Naji@arm.com # Active Power-down current : fast exit 26310430SOmar.Naji@arm.com IDD3P1 = Param.Current("0mA", "Active Powerdown fast") 26410430SOmar.Naji@arm.com 26510430SOmar.Naji@arm.com # Active Power-down current : fast exit multiple voltage range 26610430SOmar.Naji@arm.com IDD3P12 = Param.Current("0mA", "Active Powerdown fast VDD2") 26710430SOmar.Naji@arm.com 26810430SOmar.Naji@arm.com # Active Standby current 26910430SOmar.Naji@arm.com IDD3N = Param.Current("0mA", "Active Standby current") 27010430SOmar.Naji@arm.com 27110430SOmar.Naji@arm.com # Active Standby current multiple voltage range 27210430SOmar.Naji@arm.com IDD3N2 = Param.Current("0mA", "Active Standby current VDD2") 27310430SOmar.Naji@arm.com 27410430SOmar.Naji@arm.com # Burst Read Operating Current 27510430SOmar.Naji@arm.com IDD4R = Param.Current("0mA", "READ current") 27610430SOmar.Naji@arm.com 27710430SOmar.Naji@arm.com # Burst Read Operating Current multiple voltage range 27810430SOmar.Naji@arm.com IDD4R2 = Param.Current("0mA", "READ current VDD2") 27910430SOmar.Naji@arm.com 28010430SOmar.Naji@arm.com # Burst Write Operating Current 28110430SOmar.Naji@arm.com IDD4W = Param.Current("0mA", "WRITE current") 28210430SOmar.Naji@arm.com 28310430SOmar.Naji@arm.com # Burst Write Operating Current multiple voltage range 28410430SOmar.Naji@arm.com IDD4W2 = Param.Current("0mA", "WRITE current VDD2") 28510430SOmar.Naji@arm.com 28610430SOmar.Naji@arm.com # Refresh Current 28710430SOmar.Naji@arm.com IDD5 = Param.Current("0mA", "Refresh current") 28810430SOmar.Naji@arm.com 28910430SOmar.Naji@arm.com # Refresh Current multiple voltage range 29010430SOmar.Naji@arm.com IDD52 = Param.Current("0mA", "Refresh current VDD2") 29110430SOmar.Naji@arm.com 29210430SOmar.Naji@arm.com # Self-Refresh Current 29310430SOmar.Naji@arm.com IDD6 = Param.Current("0mA", "Self-refresh Current") 29410430SOmar.Naji@arm.com 29510430SOmar.Naji@arm.com # Self-Refresh Current multiple voltage range 29610430SOmar.Naji@arm.com IDD62 = Param.Current("0mA", "Self-refresh Current VDD2") 29710430SOmar.Naji@arm.com 29810430SOmar.Naji@arm.com # Main voltage range of the DRAM 29910430SOmar.Naji@arm.com VDD = Param.Voltage("0V", "Main Voltage Range") 30010430SOmar.Naji@arm.com 30110430SOmar.Naji@arm.com # Second voltage range defined by some DRAMs 30210430SOmar.Naji@arm.com VDD2 = Param.Voltage("0V", "2nd Voltage Range") 30310430SOmar.Naji@arm.com 30410217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 30510217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 30610430SOmar.Naji@arm.com# an 8x8 configuration. 30710146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 3089831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 3099831SN/A device_bus_width = 8 3109831SN/A 3119831SN/A # DDR3 is a BL8 device 3129831SN/A burst_length = 8 3139831SN/A 31410217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 3159831SN/A device_rowbuffer_size = '1kB' 3169831SN/A 3179831SN/A # 8x8 configuration, so 8 devices 3189831SN/A devices_per_rank = 8 3199489SN/A 3209489SN/A # Use two ranks 3219489SN/A ranks_per_channel = 2 3229489SN/A 3239489SN/A # DDR3 has 8 banks in all configurations 3249489SN/A banks_per_rank = 8 3259489SN/A 32610216Sandreas.hansson@arm.com # 800 MHz 32710216Sandreas.hansson@arm.com tCK = '1.25ns' 32810216Sandreas.hansson@arm.com 32910217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 33010217Sandreas.hansson@arm.com tBURST = '5ns' 33110217Sandreas.hansson@arm.com 33210217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 3339489SN/A tRCD = '13.75ns' 3349489SN/A tCL = '13.75ns' 3359489SN/A tRP = '13.75ns' 3369970SN/A tRAS = '35ns' 33710217Sandreas.hansson@arm.com tRRD = '6ns' 33810217Sandreas.hansson@arm.com tXAW = '30ns' 33910217Sandreas.hansson@arm.com activation_limit = 4 34010217Sandreas.hansson@arm.com tRFC = '260ns' 34110217Sandreas.hansson@arm.com 34210210Sandreas.hansson@arm.com tWR = '15ns' 34310217Sandreas.hansson@arm.com 34410217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 34510217Sandreas.hansson@arm.com tWTR = '7.5ns' 34610217Sandreas.hansson@arm.com 34710217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 34810212Sandreas.hansson@arm.com tRTP = '7.5ns' 3499489SN/A 35010393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 35110206Sandreas.hansson@arm.com tRTW = '2.5ns' 35210206Sandreas.hansson@arm.com 35310393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 35410393Swendy.elsasser@arm.com tCS = '2.5ns' 35510393Swendy.elsasser@arm.com 35610217Sandreas.hansson@arm.com # <=85C, half for >85C 35710217Sandreas.hansson@arm.com tREFI = '7.8us' 3589971SN/A 35910430SOmar.Naji@arm.com # Current values from datasheet 36010430SOmar.Naji@arm.com IDD0 = '75mA' 36110430SOmar.Naji@arm.com IDD2N = '50mA' 36210430SOmar.Naji@arm.com IDD3N = '57mA' 36310430SOmar.Naji@arm.com IDD4W = '165mA' 36410430SOmar.Naji@arm.com IDD4R = '187mA' 36510430SOmar.Naji@arm.com IDD5 = '220mA' 36610430SOmar.Naji@arm.com VDD = '1.5V' 36710430SOmar.Naji@arm.com 36810217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 36910217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 37010217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 37110217Sandreas.hansson@arm.com# consistent across the two configurations. 37210217Sandreas.hansson@arm.comclass DDR3_2133_x64(DDR3_1600_x64): 37310217Sandreas.hansson@arm.com # 1066 MHz 37410217Sandreas.hansson@arm.com tCK = '0.938ns' 37510217Sandreas.hansson@arm.com 37610217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 37710217Sandreas.hansson@arm.com tBURST = '3.752ns' 37810217Sandreas.hansson@arm.com 37910217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 38010217Sandreas.hansson@arm.com tRCD = '13.09ns' 38110217Sandreas.hansson@arm.com tCL = '13.09ns' 38210217Sandreas.hansson@arm.com tRP = '13.09ns' 38310217Sandreas.hansson@arm.com tRAS = '33ns' 38410217Sandreas.hansson@arm.com tRRD = '5ns' 38510217Sandreas.hansson@arm.com tXAW = '25ns' 38610217Sandreas.hansson@arm.com 38710430SOmar.Naji@arm.com # Current values from datasheet 38810430SOmar.Naji@arm.com IDD0 = '70mA' 38910430SOmar.Naji@arm.com IDD2N = '37mA' 39010430SOmar.Naji@arm.com IDD3N = '44mA' 39110430SOmar.Naji@arm.com IDD4W = '157mA' 39210430SOmar.Naji@arm.com IDD4R = '191mA' 39310430SOmar.Naji@arm.com IDD5 = '250mA' 39410430SOmar.Naji@arm.com VDD = '1.5V' 39510430SOmar.Naji@arm.com 39610217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 39710430SOmar.Naji@arm.com# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8) 39810430SOmar.Naji@arm.com# in an 8x8 configuration. 39910217Sandreas.hansson@arm.comclass DDR4_2400_x64(DRAMCtrl): 40010217Sandreas.hansson@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 40110217Sandreas.hansson@arm.com device_bus_width = 8 40210217Sandreas.hansson@arm.com 40310217Sandreas.hansson@arm.com # DDR4 is a BL8 device 40410217Sandreas.hansson@arm.com burst_length = 8 40510217Sandreas.hansson@arm.com 40610217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 40710217Sandreas.hansson@arm.com device_rowbuffer_size = '1kB' 40810217Sandreas.hansson@arm.com 40910217Sandreas.hansson@arm.com # 8x8 configuration, so 8 devices 41010217Sandreas.hansson@arm.com devices_per_rank = 8 41110217Sandreas.hansson@arm.com 41210430SOmar.Naji@arm.com # Match our DDR3 configurations which is dual rank 41310430SOmar.Naji@arm.com ranks_per_channel = 2 41410217Sandreas.hansson@arm.com 41510394Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 41610394Swendy.elsasser@arm.com # Set to 4 for x4, x8 case 41710394Swendy.elsasser@arm.com bank_groups_per_rank = 4 41810394Swendy.elsasser@arm.com 41910217Sandreas.hansson@arm.com # DDR4 has 16 banks (4 bank groups) in all 42010217Sandreas.hansson@arm.com # configurations. Currently we do not capture the additional 42110217Sandreas.hansson@arm.com # constraints incurred by the bank groups 42210217Sandreas.hansson@arm.com banks_per_rank = 16 42310217Sandreas.hansson@arm.com 42410217Sandreas.hansson@arm.com # 1200 MHz 42510217Sandreas.hansson@arm.com tCK = '0.833ns' 42610217Sandreas.hansson@arm.com 42710217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 42810394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 42910394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 43010394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 43110217Sandreas.hansson@arm.com tBURST = '3.333ns' 43210217Sandreas.hansson@arm.com 43310394Swendy.elsasser@arm.com # @2400 data rate, tCCD_L is 6 CK 43410394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 43510394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 43610394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 43710394Swendy.elsasser@arm.com tCCD_L = '5ns'; 43810394Swendy.elsasser@arm.com 43910217Sandreas.hansson@arm.com # DDR4-2400 17-17-17 44010217Sandreas.hansson@arm.com tRCD = '14.16ns' 44110217Sandreas.hansson@arm.com tCL = '14.16ns' 44210217Sandreas.hansson@arm.com tRP = '14.16ns' 44310217Sandreas.hansson@arm.com tRAS = '32ns' 44410217Sandreas.hansson@arm.com 44510394Swendy.elsasser@arm.com # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns) 44610394Swendy.elsasser@arm.com tRRD = '3.3ns' 44710394Swendy.elsasser@arm.com 44810394Swendy.elsasser@arm.com # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 44910394Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 45010394Swendy.elsasser@arm.com 45110217Sandreas.hansson@arm.com tXAW = '21ns' 4529489SN/A activation_limit = 4 45310430SOmar.Naji@arm.com tRFC = '350ns' 4549489SN/A 45510217Sandreas.hansson@arm.com tWR = '15ns' 45610217Sandreas.hansson@arm.com 45710217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 45810217Sandreas.hansson@arm.com tWTR = '5ns' 45910217Sandreas.hansson@arm.com 46010217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 46110217Sandreas.hansson@arm.com tRTP = '7.5ns' 46210217Sandreas.hansson@arm.com 46310393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 46410217Sandreas.hansson@arm.com tRTW = '1.666ns' 46510217Sandreas.hansson@arm.com 46610393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 46710393Swendy.elsasser@arm.com tCS = '1.666ns' 46810393Swendy.elsasser@arm.com 46910217Sandreas.hansson@arm.com # <=85C, half for >85C 47010217Sandreas.hansson@arm.com tREFI = '7.8us' 4719489SN/A 47210430SOmar.Naji@arm.com # Current values from datasheet 47310430SOmar.Naji@arm.com IDD0 = '64mA' 47410430SOmar.Naji@arm.com IDD02 = '4mA' 47510430SOmar.Naji@arm.com IDD2N = '50mA' 47610430SOmar.Naji@arm.com IDD3N = '67mA' 47710430SOmar.Naji@arm.com IDD3N2 = '3mA' 47810430SOmar.Naji@arm.com IDD4W = '180mA' 47910430SOmar.Naji@arm.com IDD4R = '160mA' 48010430SOmar.Naji@arm.com IDD5 = '192mA' 48110430SOmar.Naji@arm.com VDD = '1.2V' 48210430SOmar.Naji@arm.com VDD2 = '2.5V' 48310430SOmar.Naji@arm.com 4849728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 48510430SOmar.Naji@arm.com# default timings based on a LPDDR2-1066 4 Gbit part (Micron MT42L128M32D1) 48610430SOmar.Naji@arm.com# in a 1x32 configuration. 48710146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 48810430SOmar.Naji@arm.com # No DLL in LPDDR2 48910430SOmar.Naji@arm.com dll = False 49010430SOmar.Naji@arm.com 4919831SN/A # 1x32 configuration, 1 device with a 32-bit interface 4929831SN/A device_bus_width = 32 4939831SN/A 4949831SN/A # LPDDR2_S4 is a BL4 and BL8 device 4959831SN/A burst_length = 8 4969831SN/A 4979831SN/A # Each device has a page (row buffer) size of 1KB 4989831SN/A # (this depends on the memory density) 4999831SN/A device_rowbuffer_size = '1kB' 5009831SN/A 5019831SN/A # 1x32 configuration, so 1 device 5029831SN/A devices_per_rank = 1 5039489SN/A 5049708SN/A # Use a single rank 5059708SN/A ranks_per_channel = 1 5069489SN/A 5079489SN/A # LPDDR2-S4 has 8 banks in all configurations 5089489SN/A banks_per_rank = 8 5099489SN/A 51010216Sandreas.hansson@arm.com # 533 MHz 51110216Sandreas.hansson@arm.com tCK = '1.876ns' 51210216Sandreas.hansson@arm.com 5139489SN/A # Fixed at 15 ns 5149489SN/A tRCD = '15ns' 5159489SN/A 5169489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 5179489SN/A tCL = '15ns' 5189489SN/A 5199728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 5209728SN/A tRP = '15ns' 5219489SN/A 5229970SN/A tRAS = '42ns' 52310210Sandreas.hansson@arm.com tWR = '15ns' 5249963SN/A 52510430SOmar.Naji@arm.com tRTP = '7.5ns' 52610212Sandreas.hansson@arm.com 5279831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 5289831SN/A # Note this is a BL8 DDR device. 5299831SN/A # Requests larger than 32 bytes are broken down into multiple requests 53010146Sandreas.hansson@arm.com # in the controller 5319831SN/A tBURST = '7.5ns' 5329489SN/A 5339708SN/A # LPDDR2-S4, 4 Gbit 5349489SN/A tRFC = '130ns' 5359489SN/A tREFI = '3.9us' 5369489SN/A 5379489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 5389489SN/A tWTR = '7.5ns' 5399489SN/A 54010393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 54110206Sandreas.hansson@arm.com tRTW = '3.75ns' 54210206Sandreas.hansson@arm.com 54310393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 54410393Swendy.elsasser@arm.com tCS = '3.75ns' 54510393Swendy.elsasser@arm.com 5469971SN/A # Activate to activate irrespective of density and speed grade 5479971SN/A tRRD = '10.0ns' 5489971SN/A 5499708SN/A # Irrespective of density, tFAW is 50 ns 5509489SN/A tXAW = '50ns' 5519489SN/A activation_limit = 4 5529664SN/A 55310430SOmar.Naji@arm.com # Current values from datasheet 55410430SOmar.Naji@arm.com IDD0 = '15mA' 55510430SOmar.Naji@arm.com IDD02 = '70mA' 55610430SOmar.Naji@arm.com IDD2N = '2mA' 55710430SOmar.Naji@arm.com IDD2N2 = '30mA' 55810430SOmar.Naji@arm.com IDD3N = '2.5mA' 55910430SOmar.Naji@arm.com IDD3N2 = '30mA' 56010430SOmar.Naji@arm.com IDD4W = '10mA' 56110430SOmar.Naji@arm.com IDD4W2 = '190mA' 56210430SOmar.Naji@arm.com IDD4R = '3mA' 56310430SOmar.Naji@arm.com IDD4R2 = '220mA' 56410430SOmar.Naji@arm.com IDD5 = '40mA' 56510430SOmar.Naji@arm.com IDD52 = '150mA' 56610430SOmar.Naji@arm.com VDD = '1.8V' 56710430SOmar.Naji@arm.com VDD2 = '1.2V' 56810430SOmar.Naji@arm.com 5699728SN/A# A single WideIO x128 interface (one command and address bus), with 5709728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 57110146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 57210430SOmar.Naji@arm.com # No DLL for WideIO 57310430SOmar.Naji@arm.com dll = False 57410430SOmar.Naji@arm.com 5759831SN/A # 1x128 configuration, 1 device with a 128-bit interface 5769831SN/A device_bus_width = 128 5779831SN/A 5789831SN/A # This is a BL4 device 5799831SN/A burst_length = 4 5809831SN/A 5819831SN/A # Each device has a page (row buffer) size of 4KB 5829831SN/A # (this depends on the memory density) 5839831SN/A device_rowbuffer_size = '4kB' 5849831SN/A 5859831SN/A # 1x128 configuration, so 1 device 5869831SN/A devices_per_rank = 1 5879664SN/A 5889664SN/A # Use one rank for a one-high die stack 5899664SN/A ranks_per_channel = 1 5909664SN/A 5919664SN/A # WideIO has 4 banks in all configurations 5929664SN/A banks_per_rank = 4 5939664SN/A 59410216Sandreas.hansson@arm.com # 200 MHz 59510216Sandreas.hansson@arm.com tCK = '5ns' 59610216Sandreas.hansson@arm.com 5979664SN/A # WIO-200 5989664SN/A tRCD = '18ns' 5999664SN/A tCL = '18ns' 6009664SN/A tRP = '18ns' 6019970SN/A tRAS = '42ns' 60210210Sandreas.hansson@arm.com tWR = '15ns' 60310212Sandreas.hansson@arm.com # Read to precharge is same as the burst 60410212Sandreas.hansson@arm.com tRTP = '20ns' 6059664SN/A 6069831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 6079831SN/A # Note this is a BL4 SDR device. 6089664SN/A tBURST = '20ns' 6099664SN/A 6109664SN/A # WIO 8 Gb 6119664SN/A tRFC = '210ns' 6129664SN/A 6139664SN/A # WIO 8 Gb, <=85C, half for >85C 6149664SN/A tREFI = '3.9us' 6159664SN/A 6169664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 6179664SN/A tWTR = '15ns' 6189664SN/A 61910393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 62010206Sandreas.hansson@arm.com tRTW = '10ns' 62110206Sandreas.hansson@arm.com 62210393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 62310393Swendy.elsasser@arm.com tCS = '10ns' 62410393Swendy.elsasser@arm.com 6259971SN/A # Activate to activate irrespective of density and speed grade 6269971SN/A tRRD = '10.0ns' 6279971SN/A 6289664SN/A # Two instead of four activation window 6299664SN/A tXAW = '50ns' 6309664SN/A activation_limit = 2 6319709SN/A 63210430SOmar.Naji@arm.com # The WideIO specification does not provide current information 63310430SOmar.Naji@arm.com 6349728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 63510430SOmar.Naji@arm.com# default timings based on a LPDDR3-1600 4 Gbit part (Micron 63610430SOmar.Naji@arm.com# EDF8132A1MC) in a 1x32 configuration. 63710146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 63810430SOmar.Naji@arm.com # No DLL for LPDDR3 63910430SOmar.Naji@arm.com dll = False 64010430SOmar.Naji@arm.com 6419831SN/A # 1x32 configuration, 1 device with a 32-bit interface 6429831SN/A device_bus_width = 32 6439831SN/A 6449831SN/A # LPDDR3 is a BL8 device 6459831SN/A burst_length = 8 6469831SN/A 6479976SN/A # Each device has a page (row buffer) size of 4KB 6489976SN/A device_rowbuffer_size = '4kB' 6499831SN/A 6509831SN/A # 1x32 configuration, so 1 device 6519831SN/A devices_per_rank = 1 6529709SN/A 65310430SOmar.Naji@arm.com # Technically the datasheet is a dual-rank package, but for 65410430SOmar.Naji@arm.com # comparison with the LPDDR2 config we stick to a single rank 6559709SN/A ranks_per_channel = 1 6569709SN/A 6579709SN/A # LPDDR3 has 8 banks in all configurations 6589709SN/A banks_per_rank = 8 6599709SN/A 66010216Sandreas.hansson@arm.com # 800 MHz 66110216Sandreas.hansson@arm.com tCK = '1.25ns' 66210216Sandreas.hansson@arm.com 66310430SOmar.Naji@arm.com tRCD = '18ns' 6649709SN/A 6659709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 6669709SN/A tCL = '15ns' 6679709SN/A 6689970SN/A tRAS = '42ns' 66910210Sandreas.hansson@arm.com tWR = '15ns' 6709963SN/A 67110212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 67210212Sandreas.hansson@arm.com tRTP = '7.5ns' 67310212Sandreas.hansson@arm.com 67410430SOmar.Naji@arm.com # Pre-charge one bank 18 ns (all banks 21 ns) 67510430SOmar.Naji@arm.com tRP = '18ns' 6769709SN/A 6779831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 6789831SN/A # Note this is a BL8 DDR device. 6799831SN/A # Requests larger than 32 bytes are broken down into multiple requests 68010146Sandreas.hansson@arm.com # in the controller 6819831SN/A tBURST = '5ns' 6829709SN/A 6839709SN/A # LPDDR3, 4 Gb 6849709SN/A tRFC = '130ns' 6859709SN/A tREFI = '3.9us' 6869709SN/A 6879709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 6889709SN/A tWTR = '7.5ns' 6899709SN/A 69010393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 69110206Sandreas.hansson@arm.com tRTW = '2.5ns' 69210206Sandreas.hansson@arm.com 69310393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 69410393Swendy.elsasser@arm.com tCS = '2.5ns' 69510393Swendy.elsasser@arm.com 6969971SN/A # Activate to activate irrespective of density and speed grade 6979971SN/A tRRD = '10.0ns' 6989971SN/A 6999709SN/A # Irrespective of size, tFAW is 50 ns 7009709SN/A tXAW = '50ns' 7019709SN/A activation_limit = 4 70210430SOmar.Naji@arm.com 70310430SOmar.Naji@arm.com # Current values from datasheet 70410430SOmar.Naji@arm.com IDD0 = '8mA' 70510430SOmar.Naji@arm.com IDD02 = '60mA' 70610430SOmar.Naji@arm.com IDD2N = '0.8mA' 70710430SOmar.Naji@arm.com IDD2N2 = '26mA' 70810430SOmar.Naji@arm.com IDD3N = '2mA' 70910430SOmar.Naji@arm.com IDD3N2 = '34mA' 71010430SOmar.Naji@arm.com IDD4W = '2mA' 71110430SOmar.Naji@arm.com IDD4W2 = '190mA' 71210430SOmar.Naji@arm.com IDD4R = '2mA' 71310430SOmar.Naji@arm.com IDD4R2 = '230mA' 71410430SOmar.Naji@arm.com IDD5 = '28mA' 71510430SOmar.Naji@arm.com IDD52 = '150mA' 71610430SOmar.Naji@arm.com VDD = '1.8V' 71710430SOmar.Naji@arm.com VDD2 = '1.2V' 718