DRAMCtrl.py revision 10394
110206Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 149831SN/A# All rights reserved. 159831SN/A# 169243SN/A# Redistribution and use in source and binary forms, with or without 179243SN/A# modification, are permitted provided that the following conditions are 189243SN/A# met: redistributions of source code must retain the above copyright 199243SN/A# notice, this list of conditions and the following disclaimer; 209243SN/A# redistributions in binary form must reproduce the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer in the 229243SN/A# documentation and/or other materials provided with the distribution; 239243SN/A# neither the name of the copyright holders nor the names of its 249243SN/A# contributors may be used to endorse or promote products derived from 259243SN/A# this software without specific prior written permission. 269243SN/A# 279243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 289243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 299243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 309243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 319243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 329243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 339243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 349243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 359243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 369243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389243SN/A# 399243SN/A# Authors: Andreas Hansson 409243SN/A# Ani Udipi 419243SN/A 429243SN/Afrom m5.params import * 439243SN/Afrom AbstractMemory import * 449243SN/A 459243SN/A# Enum for memory scheduling algorithms, currently First-Come 469243SN/A# First-Served and a First-Row Hit then First-Come First-Served 479243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 489243SN/A 4910136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5010136SN/A# channel, rank, bank, row and column, respectively, and going from 5110136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210136SN/A# suitable for an open-page policy, optimising for sequential accesses 5310136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5410136SN/A# maximises parallelism. 5510136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 569243SN/A 5710144SN/A# Enum for the page policy, either open, open_adaptive, close, or 5810144SN/A# close_adaptive. 5910144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6010144SN/A 'close_adaptive'] 619243SN/A 6210146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 639243SN/A# that aims to model the most important system-level performance 649243SN/A# effects of a DRAM without getting into too much detail of the DRAM 659243SN/A# itself. 6610146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 6710146Sandreas.hansson@arm.com type = 'DRAMCtrl' 6810146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 699243SN/A 709243SN/A # single-ported on the system interface side, instantiate with a 719243SN/A # bus in front of the controller for multiple ports 729243SN/A port = SlavePort("Slave port") 739243SN/A 749243SN/A # the basic configuration of the controller architecture 7510145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 769972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 779243SN/A 7810140SN/A # threshold in percent for when to forcefully trigger writes and 7910140SN/A # start emptying the write buffer 8010140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 819972SN/A 8210140SN/A # threshold in percentage for when to start writes if the read 8310140SN/A # queue is empty 8410140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 8510140SN/A 8610140SN/A # minimum write bursts to schedule before switching back to reads 8710140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 8810140SN/A "switching to reads") 899243SN/A 909243SN/A # scheduler, address map and page policy 919489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9210136SN/A addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 9310145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 949243SN/A 9510141SN/A # enforce a limit on the number of accesses per row 9610141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 9710141SN/A "closing"); 9810141SN/A 999726SN/A # pipeline latency of the controller and PHY, split into a 1009726SN/A # frontend part and a backend part, with reads and writes serviced 1019726SN/A # by the queues only seeing the frontend contribution, and reads 1029726SN/A # serviced by the memory seeing the sum of the two 1039726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1049726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1059726SN/A 1069489SN/A # the physical organisation of the DRAM 1079831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1089831SN/A "device/chip") 1099831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1109831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1119831SN/A "device/chip") 1129831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1139489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 11410394Swendy.elsasser@arm.com 11510394Swendy.elsasser@arm.com # default to 0 bank groups per rank, indicating bank group architecture 11610394Swendy.elsasser@arm.com # is not used 11710394Swendy.elsasser@arm.com # update per memory class when bank group architecture is supported 11810394Swendy.elsasser@arm.com bank_groups_per_rank = Param.Unsigned(0, "Number of bank groups per rank") 1199489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1209566SN/A # only used for the address mapping as the controller by 1219566SN/A # construction is a single channel and multiple controllers have 1229566SN/A # to be instantiated for a multi-channel configuration 1239566SN/A channels = Param.Unsigned(1, "Number of channels") 1249489SN/A 1259243SN/A # timing behaviour and constraints - all in nanoseconds 1269243SN/A 12710216Sandreas.hansson@arm.com # the base clock period of the DRAM 12810216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 12910216Sandreas.hansson@arm.com 1309243SN/A # the amount of time in nanoseconds from issuing an activate command 1319243SN/A # to the data being available in the row buffer for a read/write 1329489SN/A tRCD = Param.Latency("RAS to CAS delay") 1339243SN/A 1349243SN/A # the time from issuing a read/write command to seeing the actual data 1359489SN/A tCL = Param.Latency("CAS latency") 1369243SN/A 1379243SN/A # minimum time between a precharge and subsequent activate 1389489SN/A tRP = Param.Latency("Row precharge time") 1399243SN/A 1409963SN/A # minimum time between an activate and a precharge to the same row 1419963SN/A tRAS = Param.Latency("ACT to PRE delay") 1429963SN/A 14310210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 14410210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 14510210Sandreas.hansson@arm.com 14610212Sandreas.hansson@arm.com # minimum time between a read and precharge command 14710212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 14810212Sandreas.hansson@arm.com 1499243SN/A # time to complete a burst transfer, typically the burst length 1509243SN/A # divided by two due to the DDR bus, but by making it a parameter 1519243SN/A # it is easier to also evaluate SDR memories like WideIO. 1529831SN/A # This parameter has to account for burst length. 1539831SN/A # Read/Write requests with data size larger than one full burst are broken 15410146Sandreas.hansson@arm.com # down into multiple requests in the controller 15510394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 15610394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 15710394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 1589489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1599243SN/A 16010394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 16110394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 16210394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 16310394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 16410394Swendy.elsasser@arm.com tCCD_L = Param.Latency("0ns", "Same bank group CAS to CAS delay") 16510394Swendy.elsasser@arm.com 1669243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1679489SN/A tRFC = Param.Latency("Refresh cycle time") 1689243SN/A 1699243SN/A # refresh command interval, how often a "ref" command needs 1709243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1719489SN/A tREFI = Param.Latency("Refresh command interval") 1729243SN/A 17310393Swendy.elsasser@arm.com # write-to-read, same rank turnaround penalty 17410393Swendy.elsasser@arm.com tWTR = Param.Latency("Write to read, same rank switching time") 1759243SN/A 17610393Swendy.elsasser@arm.com # read-to-write, same rank turnaround penalty 17710393Swendy.elsasser@arm.com tRTW = Param.Latency("Read to write, same rank switching time") 17810393Swendy.elsasser@arm.com 17910393Swendy.elsasser@arm.com # rank-to-rank bus delay penalty 18010393Swendy.elsasser@arm.com # this does not correlate to a memory timing parameter and encompasses: 18110393Swendy.elsasser@arm.com # 1) RD-to-RD, 2) WR-to-WR, 3) RD-to-WR, and 4) WR-to-RD 18210393Swendy.elsasser@arm.com # different rank bus delay 18310393Swendy.elsasser@arm.com tCS = Param.Latency("Rank to rank switching time") 18410206Sandreas.hansson@arm.com 1859971SN/A # minimum row activate to row activate delay time 1869971SN/A tRRD = Param.Latency("ACT to ACT delay") 1879971SN/A 18810394Swendy.elsasser@arm.com # only utilized with bank group architectures; set to 0 for default case 18910394Swendy.elsasser@arm.com tRRD_L = Param.Latency("0ns", "Same bank group ACT to ACT delay") 19010394Swendy.elsasser@arm.com 1919488SN/A # time window in which a maximum number of activates are allowed 1929488SN/A # to take place, set to 0 to disable 1939489SN/A tXAW = Param.Latency("X activation window") 1949489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 1959488SN/A 1969488SN/A # Currently rolled into other params 1979243SN/A ###################################################################### 1989243SN/A 1999963SN/A # tRC - assumed to be tRAS + tRP 2009243SN/A 20110217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 20210217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 20310217Sandreas.hansson@arm.com# an 8x8 configuration, amounting to 4 Gbyte of memory. 20410146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 2059831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 2069831SN/A device_bus_width = 8 2079831SN/A 2089831SN/A # DDR3 is a BL8 device 2099831SN/A burst_length = 8 2109831SN/A 21110217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 2129831SN/A device_rowbuffer_size = '1kB' 2139831SN/A 2149831SN/A # 8x8 configuration, so 8 devices 2159831SN/A devices_per_rank = 8 2169489SN/A 2179489SN/A # Use two ranks 2189489SN/A ranks_per_channel = 2 2199489SN/A 2209489SN/A # DDR3 has 8 banks in all configurations 2219489SN/A banks_per_rank = 8 2229489SN/A 22310216Sandreas.hansson@arm.com # 800 MHz 22410216Sandreas.hansson@arm.com tCK = '1.25ns' 22510216Sandreas.hansson@arm.com 22610217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 22710217Sandreas.hansson@arm.com tBURST = '5ns' 22810217Sandreas.hansson@arm.com 22910217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 2309489SN/A tRCD = '13.75ns' 2319489SN/A tCL = '13.75ns' 2329489SN/A tRP = '13.75ns' 2339970SN/A tRAS = '35ns' 23410217Sandreas.hansson@arm.com tRRD = '6ns' 23510217Sandreas.hansson@arm.com tXAW = '30ns' 23610217Sandreas.hansson@arm.com activation_limit = 4 23710217Sandreas.hansson@arm.com tRFC = '260ns' 23810217Sandreas.hansson@arm.com 23910210Sandreas.hansson@arm.com tWR = '15ns' 24010217Sandreas.hansson@arm.com 24110217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 24210217Sandreas.hansson@arm.com tWTR = '7.5ns' 24310217Sandreas.hansson@arm.com 24410217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 24510212Sandreas.hansson@arm.com tRTP = '7.5ns' 2469489SN/A 24710393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 24810206Sandreas.hansson@arm.com tRTW = '2.5ns' 24910206Sandreas.hansson@arm.com 25010393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 25110393Swendy.elsasser@arm.com tCS = '2.5ns' 25210393Swendy.elsasser@arm.com 25310217Sandreas.hansson@arm.com # <=85C, half for >85C 25410217Sandreas.hansson@arm.com tREFI = '7.8us' 2559971SN/A 25610217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 25710217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 25810217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 25910217Sandreas.hansson@arm.com# consistent across the two configurations. 26010217Sandreas.hansson@arm.comclass DDR3_2133_x64(DDR3_1600_x64): 26110217Sandreas.hansson@arm.com # 1066 MHz 26210217Sandreas.hansson@arm.com tCK = '0.938ns' 26310217Sandreas.hansson@arm.com 26410217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 26510217Sandreas.hansson@arm.com tBURST = '3.752ns' 26610217Sandreas.hansson@arm.com 26710217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 26810217Sandreas.hansson@arm.com tRCD = '13.09ns' 26910217Sandreas.hansson@arm.com tCL = '13.09ns' 27010217Sandreas.hansson@arm.com tRP = '13.09ns' 27110217Sandreas.hansson@arm.com tRAS = '33ns' 27210217Sandreas.hansson@arm.com tRRD = '5ns' 27310217Sandreas.hansson@arm.com tXAW = '25ns' 27410217Sandreas.hansson@arm.com 27510217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 27610217Sandreas.hansson@arm.com# timings based on a DDR4-2400 4 Gbit datasheet (Samsung K4A4G085WD) 27710217Sandreas.hansson@arm.com# in an 8x8 configuration, amounting to 4 Gbyte of memory. 27810217Sandreas.hansson@arm.comclass DDR4_2400_x64(DRAMCtrl): 27910217Sandreas.hansson@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 28010217Sandreas.hansson@arm.com device_bus_width = 8 28110217Sandreas.hansson@arm.com 28210217Sandreas.hansson@arm.com # DDR4 is a BL8 device 28310217Sandreas.hansson@arm.com burst_length = 8 28410217Sandreas.hansson@arm.com 28510217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 28610217Sandreas.hansson@arm.com device_rowbuffer_size = '1kB' 28710217Sandreas.hansson@arm.com 28810217Sandreas.hansson@arm.com # 8x8 configuration, so 8 devices 28910217Sandreas.hansson@arm.com devices_per_rank = 8 29010217Sandreas.hansson@arm.com 29110217Sandreas.hansson@arm.com # Use a single rank 29210217Sandreas.hansson@arm.com ranks_per_channel = 1 29310217Sandreas.hansson@arm.com 29410394Swendy.elsasser@arm.com # DDR4 has 2 (x16) or 4 (x4 and x8) bank groups 29510394Swendy.elsasser@arm.com # Set to 4 for x4, x8 case 29610394Swendy.elsasser@arm.com bank_groups_per_rank = 4 29710394Swendy.elsasser@arm.com 29810217Sandreas.hansson@arm.com # DDR4 has 16 banks (4 bank groups) in all 29910217Sandreas.hansson@arm.com # configurations. Currently we do not capture the additional 30010217Sandreas.hansson@arm.com # constraints incurred by the bank groups 30110217Sandreas.hansson@arm.com banks_per_rank = 16 30210217Sandreas.hansson@arm.com 30310217Sandreas.hansson@arm.com # 1200 MHz 30410217Sandreas.hansson@arm.com tCK = '0.833ns' 30510217Sandreas.hansson@arm.com 30610217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 30710394Swendy.elsasser@arm.com # tBURST is equivalent to the CAS-to-CAS delay (tCCD) 30810394Swendy.elsasser@arm.com # With bank group architectures, tBURST represents the CAS-to-CAS 30910394Swendy.elsasser@arm.com # delay for bursts to different bank groups (tCCD_S) 31010217Sandreas.hansson@arm.com tBURST = '3.333ns' 31110217Sandreas.hansson@arm.com 31210394Swendy.elsasser@arm.com # @2400 data rate, tCCD_L is 6 CK 31310394Swendy.elsasser@arm.com # CAS-to-CAS delay for bursts to the same bank group 31410394Swendy.elsasser@arm.com # tBURST is equivalent to tCCD_S; no explicit parameter required 31510394Swendy.elsasser@arm.com # for CAS-to-CAS delay for bursts to different bank groups 31610394Swendy.elsasser@arm.com tCCD_L = '5ns'; 31710394Swendy.elsasser@arm.com 31810217Sandreas.hansson@arm.com # DDR4-2400 17-17-17 31910217Sandreas.hansson@arm.com tRCD = '14.16ns' 32010217Sandreas.hansson@arm.com tCL = '14.16ns' 32110217Sandreas.hansson@arm.com tRP = '14.16ns' 32210217Sandreas.hansson@arm.com tRAS = '32ns' 32310217Sandreas.hansson@arm.com 32410394Swendy.elsasser@arm.com # RRD_S (different bank group) for 1K page is MAX(4 CK, 3.3ns) 32510394Swendy.elsasser@arm.com tRRD = '3.3ns' 32610394Swendy.elsasser@arm.com 32710394Swendy.elsasser@arm.com # RRD_L (same bank group) for 1K page is MAX(4 CK, 4.9ns) 32810394Swendy.elsasser@arm.com tRRD_L = '4.9ns'; 32910394Swendy.elsasser@arm.com 33010217Sandreas.hansson@arm.com tXAW = '21ns' 3319489SN/A activation_limit = 4 33210217Sandreas.hansson@arm.com tRFC = '260ns' 3339489SN/A 33410217Sandreas.hansson@arm.com tWR = '15ns' 33510217Sandreas.hansson@arm.com 33610217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 33710217Sandreas.hansson@arm.com tWTR = '5ns' 33810217Sandreas.hansson@arm.com 33910217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 34010217Sandreas.hansson@arm.com tRTP = '7.5ns' 34110217Sandreas.hansson@arm.com 34210393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @1200 MHz = 1.666 ns 34310217Sandreas.hansson@arm.com tRTW = '1.666ns' 34410217Sandreas.hansson@arm.com 34510393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @1200 MHz = 1.666 ns 34610393Swendy.elsasser@arm.com tCS = '1.666ns' 34710393Swendy.elsasser@arm.com 34810217Sandreas.hansson@arm.com # <=85C, half for >85C 34910217Sandreas.hansson@arm.com tREFI = '7.8us' 3509489SN/A 35110137SN/A# A single DDR3 x64 interface (one command and address bus), with 35210137SN/A# default timings based on DDR3-1333 4 Gbit parts in an 8x8 35310137SN/A# configuration, which would amount to 4 GByte of memory. This 35410137SN/A# configuration is primarily for comparing with DRAMSim2, and all the 35510137SN/A# parameters except ranks_per_channel are based on the DRAMSim2 config 35610137SN/A# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 35710137SN/A# to be manually set, depending on size of the memory to be 35810137SN/A# simulated. By default DRAMSim2 has 2048MB of memory with a single 35910137SN/A# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 36010146Sandreas.hansson@arm.comclass DDR3_1333_x64_DRAMSim2(DRAMCtrl): 36110137SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 36210137SN/A device_bus_width = 8 36310137SN/A 36410137SN/A # DDR3 is a BL8 device 36510137SN/A burst_length = 8 36610137SN/A 36710137SN/A # Each device has a page (row buffer) size of 1KB 36810137SN/A # (this depends on the memory density) 36910137SN/A device_rowbuffer_size = '1kB' 37010137SN/A 37110137SN/A # 8x8 configuration, so 8 devices 37210137SN/A devices_per_rank = 8 37310137SN/A 37410137SN/A # Use two ranks 37510137SN/A ranks_per_channel = 2 37610137SN/A 37710137SN/A # DDR3 has 8 banks in all configurations 37810137SN/A banks_per_rank = 8 37910137SN/A 38010216Sandreas.hansson@arm.com # 666 MHs 38110216Sandreas.hansson@arm.com tCK = '1.5ns' 38210216Sandreas.hansson@arm.com 38310137SN/A tRCD = '15ns' 38410137SN/A tCL = '15ns' 38510137SN/A tRP = '15ns' 38610137SN/A tRAS = '36ns' 38710210Sandreas.hansson@arm.com tWR = '15ns' 38810212Sandreas.hansson@arm.com tRTP = '7.5ns' 38910137SN/A 39010137SN/A # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 39110137SN/A # Note this is a BL8 DDR device. 39210137SN/A tBURST = '6ns' 39310137SN/A 39410137SN/A tRFC = '160ns' 39510137SN/A 39610137SN/A # DDR3, <=85C, half for >85C 39710137SN/A tREFI = '7.8us' 39810137SN/A 39910137SN/A # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 40010137SN/A tWTR = '7.5ns' 40110137SN/A 40210393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @666.66 MHz = 3 ns 40310206Sandreas.hansson@arm.com tRTW = '3ns' 40410206Sandreas.hansson@arm.com 40510393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @666.66 MHz = 3 ns 40610393Swendy.elsasser@arm.com tCS = '3ns' 40710393Swendy.elsasser@arm.com 40810137SN/A tRRD = '6.0ns' 40910137SN/A 41010137SN/A tXAW = '30ns' 41110137SN/A activation_limit = 4 41210137SN/A 41310137SN/A 4149728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 4159728SN/A# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 4169728SN/A# configuration. 41710146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 4189831SN/A # 1x32 configuration, 1 device with a 32-bit interface 4199831SN/A device_bus_width = 32 4209831SN/A 4219831SN/A # LPDDR2_S4 is a BL4 and BL8 device 4229831SN/A burst_length = 8 4239831SN/A 4249831SN/A # Each device has a page (row buffer) size of 1KB 4259831SN/A # (this depends on the memory density) 4269831SN/A device_rowbuffer_size = '1kB' 4279831SN/A 4289831SN/A # 1x32 configuration, so 1 device 4299831SN/A devices_per_rank = 1 4309489SN/A 4319708SN/A # Use a single rank 4329708SN/A ranks_per_channel = 1 4339489SN/A 4349489SN/A # LPDDR2-S4 has 8 banks in all configurations 4359489SN/A banks_per_rank = 8 4369489SN/A 43710216Sandreas.hansson@arm.com # 533 MHz 43810216Sandreas.hansson@arm.com tCK = '1.876ns' 43910216Sandreas.hansson@arm.com 4409489SN/A # Fixed at 15 ns 4419489SN/A tRCD = '15ns' 4429489SN/A 4439489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 4449489SN/A tCL = '15ns' 4459489SN/A 4469728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 4479728SN/A tRP = '15ns' 4489489SN/A 4499970SN/A tRAS = '42ns' 45010210Sandreas.hansson@arm.com tWR = '15ns' 4519963SN/A 45210212Sandreas.hansson@arm.com # 6 CK read to precharge delay 45310212Sandreas.hansson@arm.com tRTP = '11.256ns' 45410212Sandreas.hansson@arm.com 4559831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 4569831SN/A # Note this is a BL8 DDR device. 4579831SN/A # Requests larger than 32 bytes are broken down into multiple requests 45810146Sandreas.hansson@arm.com # in the controller 4599831SN/A tBURST = '7.5ns' 4609489SN/A 4619708SN/A # LPDDR2-S4, 4 Gbit 4629489SN/A tRFC = '130ns' 4639489SN/A tREFI = '3.9us' 4649489SN/A 4659489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 4669489SN/A tWTR = '7.5ns' 4679489SN/A 46810393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @533 MHz = 3.75 ns 46910206Sandreas.hansson@arm.com tRTW = '3.75ns' 47010206Sandreas.hansson@arm.com 47110393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @533 MHz = 3.75 ns 47210393Swendy.elsasser@arm.com tCS = '3.75ns' 47310393Swendy.elsasser@arm.com 4749971SN/A # Activate to activate irrespective of density and speed grade 4759971SN/A tRRD = '10.0ns' 4769971SN/A 4779708SN/A # Irrespective of density, tFAW is 50 ns 4789489SN/A tXAW = '50ns' 4799489SN/A activation_limit = 4 4809664SN/A 4819728SN/A# A single WideIO x128 interface (one command and address bus), with 4829728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 48310146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 4849831SN/A # 1x128 configuration, 1 device with a 128-bit interface 4859831SN/A device_bus_width = 128 4869831SN/A 4879831SN/A # This is a BL4 device 4889831SN/A burst_length = 4 4899831SN/A 4909831SN/A # Each device has a page (row buffer) size of 4KB 4919831SN/A # (this depends on the memory density) 4929831SN/A device_rowbuffer_size = '4kB' 4939831SN/A 4949831SN/A # 1x128 configuration, so 1 device 4959831SN/A devices_per_rank = 1 4969664SN/A 4979664SN/A # Use one rank for a one-high die stack 4989664SN/A ranks_per_channel = 1 4999664SN/A 5009664SN/A # WideIO has 4 banks in all configurations 5019664SN/A banks_per_rank = 4 5029664SN/A 50310216Sandreas.hansson@arm.com # 200 MHz 50410216Sandreas.hansson@arm.com tCK = '5ns' 50510216Sandreas.hansson@arm.com 5069664SN/A # WIO-200 5079664SN/A tRCD = '18ns' 5089664SN/A tCL = '18ns' 5099664SN/A tRP = '18ns' 5109970SN/A tRAS = '42ns' 51110210Sandreas.hansson@arm.com tWR = '15ns' 51210212Sandreas.hansson@arm.com # Read to precharge is same as the burst 51310212Sandreas.hansson@arm.com tRTP = '20ns' 5149664SN/A 5159831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 5169831SN/A # Note this is a BL4 SDR device. 5179664SN/A tBURST = '20ns' 5189664SN/A 5199664SN/A # WIO 8 Gb 5209664SN/A tRFC = '210ns' 5219664SN/A 5229664SN/A # WIO 8 Gb, <=85C, half for >85C 5239664SN/A tREFI = '3.9us' 5249664SN/A 5259664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 5269664SN/A tWTR = '15ns' 5279664SN/A 52810393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @200 MHz = 10 ns 52910206Sandreas.hansson@arm.com tRTW = '10ns' 53010206Sandreas.hansson@arm.com 53110393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @200 MHz = 10 ns 53210393Swendy.elsasser@arm.com tCS = '10ns' 53310393Swendy.elsasser@arm.com 5349971SN/A # Activate to activate irrespective of density and speed grade 5359971SN/A tRRD = '10.0ns' 5369971SN/A 5379664SN/A # Two instead of four activation window 5389664SN/A tXAW = '50ns' 5399664SN/A activation_limit = 2 5409709SN/A 5419728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 5429728SN/A# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 5439728SN/A# configuration 54410146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 5459831SN/A # 1x32 configuration, 1 device with a 32-bit interface 5469831SN/A device_bus_width = 32 5479831SN/A 5489831SN/A # LPDDR3 is a BL8 device 5499831SN/A burst_length = 8 5509831SN/A 5519976SN/A # Each device has a page (row buffer) size of 4KB 5529976SN/A device_rowbuffer_size = '4kB' 5539831SN/A 5549831SN/A # 1x32 configuration, so 1 device 5559831SN/A devices_per_rank = 1 5569709SN/A 5579709SN/A # Use a single rank 5589709SN/A ranks_per_channel = 1 5599709SN/A 5609709SN/A # LPDDR3 has 8 banks in all configurations 5619709SN/A banks_per_rank = 8 5629709SN/A 56310216Sandreas.hansson@arm.com # 800 MHz 56410216Sandreas.hansson@arm.com tCK = '1.25ns' 56510216Sandreas.hansson@arm.com 5669709SN/A # Fixed at 15 ns 5679709SN/A tRCD = '15ns' 5689709SN/A 5699709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 5709709SN/A tCL = '15ns' 5719709SN/A 5729970SN/A tRAS = '42ns' 57310210Sandreas.hansson@arm.com tWR = '15ns' 5749963SN/A 57510212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 57610212Sandreas.hansson@arm.com tRTP = '7.5ns' 57710212Sandreas.hansson@arm.com 5789728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 5799728SN/A tRP = '15ns' 5809709SN/A 5819831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 5829831SN/A # Note this is a BL8 DDR device. 5839831SN/A # Requests larger than 32 bytes are broken down into multiple requests 58410146Sandreas.hansson@arm.com # in the controller 5859831SN/A tBURST = '5ns' 5869709SN/A 5879709SN/A # LPDDR3, 4 Gb 5889709SN/A tRFC = '130ns' 5899709SN/A tREFI = '3.9us' 5909709SN/A 5919709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 5929709SN/A tWTR = '7.5ns' 5939709SN/A 59410393Swendy.elsasser@arm.com # Default same rank rd-to-wr bus turnaround to 2 CK, @800 MHz = 2.5 ns 59510206Sandreas.hansson@arm.com tRTW = '2.5ns' 59610206Sandreas.hansson@arm.com 59710393Swendy.elsasser@arm.com # Default different rank bus delay to 2 CK, @800 MHz = 2.5 ns 59810393Swendy.elsasser@arm.com tCS = '2.5ns' 59910393Swendy.elsasser@arm.com 6009971SN/A # Activate to activate irrespective of density and speed grade 6019971SN/A tRRD = '10.0ns' 6029971SN/A 6039709SN/A # Irrespective of size, tFAW is 50 ns 6049709SN/A tXAW = '50ns' 6059709SN/A activation_limit = 4 606