DRAMCtrl.py revision 10217
110206Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 149831SN/A# All rights reserved. 159831SN/A# 169243SN/A# Redistribution and use in source and binary forms, with or without 179243SN/A# modification, are permitted provided that the following conditions are 189243SN/A# met: redistributions of source code must retain the above copyright 199243SN/A# notice, this list of conditions and the following disclaimer; 209243SN/A# redistributions in binary form must reproduce the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer in the 229243SN/A# documentation and/or other materials provided with the distribution; 239243SN/A# neither the name of the copyright holders nor the names of its 249243SN/A# contributors may be used to endorse or promote products derived from 259243SN/A# this software without specific prior written permission. 269243SN/A# 279243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 289243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 299243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 309243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 319243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 329243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 339243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 349243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 359243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 369243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389243SN/A# 399243SN/A# Authors: Andreas Hansson 409243SN/A# Ani Udipi 419243SN/A 429243SN/Afrom m5.params import * 439243SN/Afrom AbstractMemory import * 449243SN/A 459243SN/A# Enum for memory scheduling algorithms, currently First-Come 469243SN/A# First-Served and a First-Row Hit then First-Come First-Served 479243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 489243SN/A 4910136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5010136SN/A# channel, rank, bank, row and column, respectively, and going from 5110136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210136SN/A# suitable for an open-page policy, optimising for sequential accesses 5310136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5410136SN/A# maximises parallelism. 5510136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 569243SN/A 5710144SN/A# Enum for the page policy, either open, open_adaptive, close, or 5810144SN/A# close_adaptive. 5910144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6010144SN/A 'close_adaptive'] 619243SN/A 6210146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 639243SN/A# that aims to model the most important system-level performance 649243SN/A# effects of a DRAM without getting into too much detail of the DRAM 659243SN/A# itself. 6610146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 6710146Sandreas.hansson@arm.com type = 'DRAMCtrl' 6810146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 699243SN/A 709243SN/A # single-ported on the system interface side, instantiate with a 719243SN/A # bus in front of the controller for multiple ports 729243SN/A port = SlavePort("Slave port") 739243SN/A 749243SN/A # the basic configuration of the controller architecture 7510145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 769972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 779243SN/A 7810140SN/A # threshold in percent for when to forcefully trigger writes and 7910140SN/A # start emptying the write buffer 8010140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 819972SN/A 8210140SN/A # threshold in percentage for when to start writes if the read 8310140SN/A # queue is empty 8410140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 8510140SN/A 8610140SN/A # minimum write bursts to schedule before switching back to reads 8710140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 8810140SN/A "switching to reads") 899243SN/A 909243SN/A # scheduler, address map and page policy 919489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9210136SN/A addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 9310145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 949243SN/A 9510141SN/A # enforce a limit on the number of accesses per row 9610141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 9710141SN/A "closing"); 9810141SN/A 999726SN/A # pipeline latency of the controller and PHY, split into a 1009726SN/A # frontend part and a backend part, with reads and writes serviced 1019726SN/A # by the queues only seeing the frontend contribution, and reads 1029726SN/A # serviced by the memory seeing the sum of the two 1039726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1049726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1059726SN/A 1069489SN/A # the physical organisation of the DRAM 1079831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1089831SN/A "device/chip") 1099831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1109831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1119831SN/A "device/chip") 1129831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1139489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 1149489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1159566SN/A # only used for the address mapping as the controller by 1169566SN/A # construction is a single channel and multiple controllers have 1179566SN/A # to be instantiated for a multi-channel configuration 1189566SN/A channels = Param.Unsigned(1, "Number of channels") 1199489SN/A 1209243SN/A # timing behaviour and constraints - all in nanoseconds 1219243SN/A 12210216Sandreas.hansson@arm.com # the base clock period of the DRAM 12310216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 12410216Sandreas.hansson@arm.com 1259243SN/A # the amount of time in nanoseconds from issuing an activate command 1269243SN/A # to the data being available in the row buffer for a read/write 1279489SN/A tRCD = Param.Latency("RAS to CAS delay") 1289243SN/A 1299243SN/A # the time from issuing a read/write command to seeing the actual data 1309489SN/A tCL = Param.Latency("CAS latency") 1319243SN/A 1329243SN/A # minimum time between a precharge and subsequent activate 1339489SN/A tRP = Param.Latency("Row precharge time") 1349243SN/A 1359963SN/A # minimum time between an activate and a precharge to the same row 1369963SN/A tRAS = Param.Latency("ACT to PRE delay") 1379963SN/A 13810210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 13910210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 14010210Sandreas.hansson@arm.com 14110212Sandreas.hansson@arm.com # minimum time between a read and precharge command 14210212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 14310212Sandreas.hansson@arm.com 1449243SN/A # time to complete a burst transfer, typically the burst length 1459243SN/A # divided by two due to the DDR bus, but by making it a parameter 1469243SN/A # it is easier to also evaluate SDR memories like WideIO. 1479831SN/A # This parameter has to account for burst length. 1489831SN/A # Read/Write requests with data size larger than one full burst are broken 14910146Sandreas.hansson@arm.com # down into multiple requests in the controller 1509489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1519243SN/A 1529243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1539489SN/A tRFC = Param.Latency("Refresh cycle time") 1549243SN/A 1559243SN/A # refresh command interval, how often a "ref" command needs 1569243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1579489SN/A tREFI = Param.Latency("Refresh command interval") 1589243SN/A 15910206Sandreas.hansson@arm.com # write-to-read turn around penalty 1609489SN/A tWTR = Param.Latency("Write to read switching time") 1619243SN/A 16210206Sandreas.hansson@arm.com # read-to-write turn around penalty, bus turnaround delay 16310206Sandreas.hansson@arm.com tRTW = Param.Latency("Read to write switching time") 16410206Sandreas.hansson@arm.com 1659971SN/A # minimum row activate to row activate delay time 1669971SN/A tRRD = Param.Latency("ACT to ACT delay") 1679971SN/A 1689488SN/A # time window in which a maximum number of activates are allowed 1699488SN/A # to take place, set to 0 to disable 1709489SN/A tXAW = Param.Latency("X activation window") 1719489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 1729488SN/A 1739488SN/A # Currently rolled into other params 1749243SN/A ###################################################################### 1759243SN/A 1769963SN/A # tRC - assumed to be tRAS + tRP 1779243SN/A 17810217Sandreas.hansson@arm.com# A single DDR3-1600 x64 channel (one command and address bus), with 17910217Sandreas.hansson@arm.com# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in 18010217Sandreas.hansson@arm.com# an 8x8 configuration, amounting to 4 Gbyte of memory. 18110146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 1829831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 1839831SN/A device_bus_width = 8 1849831SN/A 1859831SN/A # DDR3 is a BL8 device 1869831SN/A burst_length = 8 1879831SN/A 18810217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 1899831SN/A device_rowbuffer_size = '1kB' 1909831SN/A 1919831SN/A # 8x8 configuration, so 8 devices 1929831SN/A devices_per_rank = 8 1939489SN/A 1949489SN/A # Use two ranks 1959489SN/A ranks_per_channel = 2 1969489SN/A 1979489SN/A # DDR3 has 8 banks in all configurations 1989489SN/A banks_per_rank = 8 1999489SN/A 20010216Sandreas.hansson@arm.com # 800 MHz 20110216Sandreas.hansson@arm.com tCK = '1.25ns' 20210216Sandreas.hansson@arm.com 20310217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz 20410217Sandreas.hansson@arm.com tBURST = '5ns' 20510217Sandreas.hansson@arm.com 20610217Sandreas.hansson@arm.com # DDR3-1600 11-11-11 2079489SN/A tRCD = '13.75ns' 2089489SN/A tCL = '13.75ns' 2099489SN/A tRP = '13.75ns' 2109970SN/A tRAS = '35ns' 21110217Sandreas.hansson@arm.com tRRD = '6ns' 21210217Sandreas.hansson@arm.com tXAW = '30ns' 21310217Sandreas.hansson@arm.com activation_limit = 4 21410217Sandreas.hansson@arm.com tRFC = '260ns' 21510217Sandreas.hansson@arm.com 21610210Sandreas.hansson@arm.com tWR = '15ns' 21710217Sandreas.hansson@arm.com 21810217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 21910217Sandreas.hansson@arm.com tWTR = '7.5ns' 22010217Sandreas.hansson@arm.com 22110217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 22210212Sandreas.hansson@arm.com tRTP = '7.5ns' 2239489SN/A 22410206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 22510206Sandreas.hansson@arm.com tRTW = '2.5ns' 22610206Sandreas.hansson@arm.com 22710217Sandreas.hansson@arm.com # <=85C, half for >85C 22810217Sandreas.hansson@arm.com tREFI = '7.8us' 2299971SN/A 23010217Sandreas.hansson@arm.com# A single DDR3-2133 x64 channel refining a selected subset of the 23110217Sandreas.hansson@arm.com# options for the DDR-1600 configuration, based on the same DDR3-1600 23210217Sandreas.hansson@arm.com# 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept 23310217Sandreas.hansson@arm.com# consistent across the two configurations. 23410217Sandreas.hansson@arm.comclass DDR3_2133_x64(DDR3_1600_x64): 23510217Sandreas.hansson@arm.com # 1066 MHz 23610217Sandreas.hansson@arm.com tCK = '0.938ns' 23710217Sandreas.hansson@arm.com 23810217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1066 MHz 23910217Sandreas.hansson@arm.com tBURST = '3.752ns' 24010217Sandreas.hansson@arm.com 24110217Sandreas.hansson@arm.com # DDR3-2133 14-14-14 24210217Sandreas.hansson@arm.com tRCD = '13.09ns' 24310217Sandreas.hansson@arm.com tCL = '13.09ns' 24410217Sandreas.hansson@arm.com tRP = '13.09ns' 24510217Sandreas.hansson@arm.com tRAS = '33ns' 24610217Sandreas.hansson@arm.com tRRD = '5ns' 24710217Sandreas.hansson@arm.com tXAW = '25ns' 24810217Sandreas.hansson@arm.com 24910217Sandreas.hansson@arm.com# A single DDR4-2400 x64 channel (one command and address bus), with 25010217Sandreas.hansson@arm.com# timings based on a DDR4-2400 4 Gbit datasheet (Samsung K4A4G085WD) 25110217Sandreas.hansson@arm.com# in an 8x8 configuration, amounting to 4 Gbyte of memory. 25210217Sandreas.hansson@arm.comclass DDR4_2400_x64(DRAMCtrl): 25310217Sandreas.hansson@arm.com # 8x8 configuration, 8 devices each with an 8-bit interface 25410217Sandreas.hansson@arm.com device_bus_width = 8 25510217Sandreas.hansson@arm.com 25610217Sandreas.hansson@arm.com # DDR4 is a BL8 device 25710217Sandreas.hansson@arm.com burst_length = 8 25810217Sandreas.hansson@arm.com 25910217Sandreas.hansson@arm.com # Each device has a page (row buffer) size of 1 Kbyte (1K columns x8) 26010217Sandreas.hansson@arm.com device_rowbuffer_size = '1kB' 26110217Sandreas.hansson@arm.com 26210217Sandreas.hansson@arm.com # 8x8 configuration, so 8 devices 26310217Sandreas.hansson@arm.com devices_per_rank = 8 26410217Sandreas.hansson@arm.com 26510217Sandreas.hansson@arm.com # Use a single rank 26610217Sandreas.hansson@arm.com ranks_per_channel = 1 26710217Sandreas.hansson@arm.com 26810217Sandreas.hansson@arm.com # DDR4 has 16 banks (4 bank groups) in all 26910217Sandreas.hansson@arm.com # configurations. Currently we do not capture the additional 27010217Sandreas.hansson@arm.com # constraints incurred by the bank groups 27110217Sandreas.hansson@arm.com banks_per_rank = 16 27210217Sandreas.hansson@arm.com 27310217Sandreas.hansson@arm.com # 1200 MHz 27410217Sandreas.hansson@arm.com tCK = '0.833ns' 27510217Sandreas.hansson@arm.com 27610217Sandreas.hansson@arm.com # 8 beats across an x64 interface translates to 4 clocks @ 1200 MHz 27710217Sandreas.hansson@arm.com tBURST = '3.333ns' 27810217Sandreas.hansson@arm.com 27910217Sandreas.hansson@arm.com # DDR4-2400 17-17-17 28010217Sandreas.hansson@arm.com tRCD = '14.16ns' 28110217Sandreas.hansson@arm.com tCL = '14.16ns' 28210217Sandreas.hansson@arm.com tRP = '14.16ns' 28310217Sandreas.hansson@arm.com tRAS = '32ns' 28410217Sandreas.hansson@arm.com 28510217Sandreas.hansson@arm.com # Here using the average of RRD_S and RRD_L 28610217Sandreas.hansson@arm.com tRRD = '4.1ns' 28710217Sandreas.hansson@arm.com tXAW = '21ns' 2889489SN/A activation_limit = 4 28910217Sandreas.hansson@arm.com tRFC = '260ns' 2909489SN/A 29110217Sandreas.hansson@arm.com tWR = '15ns' 29210217Sandreas.hansson@arm.com 29310217Sandreas.hansson@arm.com # Here using the average of WTR_S and WTR_L 29410217Sandreas.hansson@arm.com tWTR = '5ns' 29510217Sandreas.hansson@arm.com 29610217Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns 29710217Sandreas.hansson@arm.com tRTP = '7.5ns' 29810217Sandreas.hansson@arm.com 29910217Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @1200 MHz = 1.666 ns 30010217Sandreas.hansson@arm.com tRTW = '1.666ns' 30110217Sandreas.hansson@arm.com 30210217Sandreas.hansson@arm.com # <=85C, half for >85C 30310217Sandreas.hansson@arm.com tREFI = '7.8us' 3049489SN/A 30510137SN/A# A single DDR3 x64 interface (one command and address bus), with 30610137SN/A# default timings based on DDR3-1333 4 Gbit parts in an 8x8 30710137SN/A# configuration, which would amount to 4 GByte of memory. This 30810137SN/A# configuration is primarily for comparing with DRAMSim2, and all the 30910137SN/A# parameters except ranks_per_channel are based on the DRAMSim2 config 31010137SN/A# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 31110137SN/A# to be manually set, depending on size of the memory to be 31210137SN/A# simulated. By default DRAMSim2 has 2048MB of memory with a single 31310137SN/A# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 31410146Sandreas.hansson@arm.comclass DDR3_1333_x64_DRAMSim2(DRAMCtrl): 31510137SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 31610137SN/A device_bus_width = 8 31710137SN/A 31810137SN/A # DDR3 is a BL8 device 31910137SN/A burst_length = 8 32010137SN/A 32110137SN/A # Each device has a page (row buffer) size of 1KB 32210137SN/A # (this depends on the memory density) 32310137SN/A device_rowbuffer_size = '1kB' 32410137SN/A 32510137SN/A # 8x8 configuration, so 8 devices 32610137SN/A devices_per_rank = 8 32710137SN/A 32810137SN/A # Use two ranks 32910137SN/A ranks_per_channel = 2 33010137SN/A 33110137SN/A # DDR3 has 8 banks in all configurations 33210137SN/A banks_per_rank = 8 33310137SN/A 33410216Sandreas.hansson@arm.com # 666 MHs 33510216Sandreas.hansson@arm.com tCK = '1.5ns' 33610216Sandreas.hansson@arm.com 33710137SN/A tRCD = '15ns' 33810137SN/A tCL = '15ns' 33910137SN/A tRP = '15ns' 34010137SN/A tRAS = '36ns' 34110210Sandreas.hansson@arm.com tWR = '15ns' 34210212Sandreas.hansson@arm.com tRTP = '7.5ns' 34310137SN/A 34410137SN/A # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 34510137SN/A # Note this is a BL8 DDR device. 34610137SN/A tBURST = '6ns' 34710137SN/A 34810137SN/A tRFC = '160ns' 34910137SN/A 35010137SN/A # DDR3, <=85C, half for >85C 35110137SN/A tREFI = '7.8us' 35210137SN/A 35310137SN/A # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 35410137SN/A tWTR = '7.5ns' 35510137SN/A 35610206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns 35710206Sandreas.hansson@arm.com tRTW = '3ns' 35810206Sandreas.hansson@arm.com 35910137SN/A tRRD = '6.0ns' 36010137SN/A 36110137SN/A tXAW = '30ns' 36210137SN/A activation_limit = 4 36310137SN/A 36410137SN/A 3659728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 3669728SN/A# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 3679728SN/A# configuration. 36810146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 3699831SN/A # 1x32 configuration, 1 device with a 32-bit interface 3709831SN/A device_bus_width = 32 3719831SN/A 3729831SN/A # LPDDR2_S4 is a BL4 and BL8 device 3739831SN/A burst_length = 8 3749831SN/A 3759831SN/A # Each device has a page (row buffer) size of 1KB 3769831SN/A # (this depends on the memory density) 3779831SN/A device_rowbuffer_size = '1kB' 3789831SN/A 3799831SN/A # 1x32 configuration, so 1 device 3809831SN/A devices_per_rank = 1 3819489SN/A 3829708SN/A # Use a single rank 3839708SN/A ranks_per_channel = 1 3849489SN/A 3859489SN/A # LPDDR2-S4 has 8 banks in all configurations 3869489SN/A banks_per_rank = 8 3879489SN/A 38810216Sandreas.hansson@arm.com # 533 MHz 38910216Sandreas.hansson@arm.com tCK = '1.876ns' 39010216Sandreas.hansson@arm.com 3919489SN/A # Fixed at 15 ns 3929489SN/A tRCD = '15ns' 3939489SN/A 3949489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 3959489SN/A tCL = '15ns' 3969489SN/A 3979728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 3989728SN/A tRP = '15ns' 3999489SN/A 4009970SN/A tRAS = '42ns' 40110210Sandreas.hansson@arm.com tWR = '15ns' 4029963SN/A 40310212Sandreas.hansson@arm.com # 6 CK read to precharge delay 40410212Sandreas.hansson@arm.com tRTP = '11.256ns' 40510212Sandreas.hansson@arm.com 4069831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 4079831SN/A # Note this is a BL8 DDR device. 4089831SN/A # Requests larger than 32 bytes are broken down into multiple requests 40910146Sandreas.hansson@arm.com # in the controller 4109831SN/A tBURST = '7.5ns' 4119489SN/A 4129708SN/A # LPDDR2-S4, 4 Gbit 4139489SN/A tRFC = '130ns' 4149489SN/A tREFI = '3.9us' 4159489SN/A 4169489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 4179489SN/A tWTR = '7.5ns' 4189489SN/A 41910206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns 42010206Sandreas.hansson@arm.com tRTW = '3.75ns' 42110206Sandreas.hansson@arm.com 4229971SN/A # Activate to activate irrespective of density and speed grade 4239971SN/A tRRD = '10.0ns' 4249971SN/A 4259708SN/A # Irrespective of density, tFAW is 50 ns 4269489SN/A tXAW = '50ns' 4279489SN/A activation_limit = 4 4289664SN/A 4299728SN/A# A single WideIO x128 interface (one command and address bus), with 4309728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 43110146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 4329831SN/A # 1x128 configuration, 1 device with a 128-bit interface 4339831SN/A device_bus_width = 128 4349831SN/A 4359831SN/A # This is a BL4 device 4369831SN/A burst_length = 4 4379831SN/A 4389831SN/A # Each device has a page (row buffer) size of 4KB 4399831SN/A # (this depends on the memory density) 4409831SN/A device_rowbuffer_size = '4kB' 4419831SN/A 4429831SN/A # 1x128 configuration, so 1 device 4439831SN/A devices_per_rank = 1 4449664SN/A 4459664SN/A # Use one rank for a one-high die stack 4469664SN/A ranks_per_channel = 1 4479664SN/A 4489664SN/A # WideIO has 4 banks in all configurations 4499664SN/A banks_per_rank = 4 4509664SN/A 45110216Sandreas.hansson@arm.com # 200 MHz 45210216Sandreas.hansson@arm.com tCK = '5ns' 45310216Sandreas.hansson@arm.com 4549664SN/A # WIO-200 4559664SN/A tRCD = '18ns' 4569664SN/A tCL = '18ns' 4579664SN/A tRP = '18ns' 4589970SN/A tRAS = '42ns' 45910210Sandreas.hansson@arm.com tWR = '15ns' 46010212Sandreas.hansson@arm.com # Read to precharge is same as the burst 46110212Sandreas.hansson@arm.com tRTP = '20ns' 4629664SN/A 4639831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 4649831SN/A # Note this is a BL4 SDR device. 4659664SN/A tBURST = '20ns' 4669664SN/A 4679664SN/A # WIO 8 Gb 4689664SN/A tRFC = '210ns' 4699664SN/A 4709664SN/A # WIO 8 Gb, <=85C, half for >85C 4719664SN/A tREFI = '3.9us' 4729664SN/A 4739664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 4749664SN/A tWTR = '15ns' 4759664SN/A 47610206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns 47710206Sandreas.hansson@arm.com tRTW = '10ns' 47810206Sandreas.hansson@arm.com 4799971SN/A # Activate to activate irrespective of density and speed grade 4809971SN/A tRRD = '10.0ns' 4819971SN/A 4829664SN/A # Two instead of four activation window 4839664SN/A tXAW = '50ns' 4849664SN/A activation_limit = 2 4859709SN/A 4869728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 4879728SN/A# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 4889728SN/A# configuration 48910146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 4909831SN/A # 1x32 configuration, 1 device with a 32-bit interface 4919831SN/A device_bus_width = 32 4929831SN/A 4939831SN/A # LPDDR3 is a BL8 device 4949831SN/A burst_length = 8 4959831SN/A 4969976SN/A # Each device has a page (row buffer) size of 4KB 4979976SN/A device_rowbuffer_size = '4kB' 4989831SN/A 4999831SN/A # 1x32 configuration, so 1 device 5009831SN/A devices_per_rank = 1 5019709SN/A 5029709SN/A # Use a single rank 5039709SN/A ranks_per_channel = 1 5049709SN/A 5059709SN/A # LPDDR3 has 8 banks in all configurations 5069709SN/A banks_per_rank = 8 5079709SN/A 50810216Sandreas.hansson@arm.com # 800 MHz 50910216Sandreas.hansson@arm.com tCK = '1.25ns' 51010216Sandreas.hansson@arm.com 5119709SN/A # Fixed at 15 ns 5129709SN/A tRCD = '15ns' 5139709SN/A 5149709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 5159709SN/A tCL = '15ns' 5169709SN/A 5179970SN/A tRAS = '42ns' 51810210Sandreas.hansson@arm.com tWR = '15ns' 5199963SN/A 52010212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 52110212Sandreas.hansson@arm.com tRTP = '7.5ns' 52210212Sandreas.hansson@arm.com 5239728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 5249728SN/A tRP = '15ns' 5259709SN/A 5269831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 5279831SN/A # Note this is a BL8 DDR device. 5289831SN/A # Requests larger than 32 bytes are broken down into multiple requests 52910146Sandreas.hansson@arm.com # in the controller 5309831SN/A tBURST = '5ns' 5319709SN/A 5329709SN/A # LPDDR3, 4 Gb 5339709SN/A tRFC = '130ns' 5349709SN/A tREFI = '3.9us' 5359709SN/A 5369709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 5379709SN/A tWTR = '7.5ns' 5389709SN/A 53910206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 54010206Sandreas.hansson@arm.com tRTW = '2.5ns' 54110206Sandreas.hansson@arm.com 5429971SN/A # Activate to activate irrespective of density and speed grade 5439971SN/A tRRD = '10.0ns' 5449971SN/A 5459709SN/A # Irrespective of size, tFAW is 50 ns 5469709SN/A tXAW = '50ns' 5479709SN/A activation_limit = 4 548