DRAMCtrl.py revision 10216
110206Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 149831SN/A# All rights reserved. 159831SN/A# 169243SN/A# Redistribution and use in source and binary forms, with or without 179243SN/A# modification, are permitted provided that the following conditions are 189243SN/A# met: redistributions of source code must retain the above copyright 199243SN/A# notice, this list of conditions and the following disclaimer; 209243SN/A# redistributions in binary form must reproduce the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer in the 229243SN/A# documentation and/or other materials provided with the distribution; 239243SN/A# neither the name of the copyright holders nor the names of its 249243SN/A# contributors may be used to endorse or promote products derived from 259243SN/A# this software without specific prior written permission. 269243SN/A# 279243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 289243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 299243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 309243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 319243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 329243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 339243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 349243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 359243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 369243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389243SN/A# 399243SN/A# Authors: Andreas Hansson 409243SN/A# Ani Udipi 419243SN/A 429243SN/Afrom m5.params import * 439243SN/Afrom AbstractMemory import * 449243SN/A 459243SN/A# Enum for memory scheduling algorithms, currently First-Come 469243SN/A# First-Served and a First-Row Hit then First-Come First-Served 479243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 489243SN/A 4910136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5010136SN/A# channel, rank, bank, row and column, respectively, and going from 5110136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210136SN/A# suitable for an open-page policy, optimising for sequential accesses 5310136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5410136SN/A# maximises parallelism. 5510136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 569243SN/A 5710144SN/A# Enum for the page policy, either open, open_adaptive, close, or 5810144SN/A# close_adaptive. 5910144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6010144SN/A 'close_adaptive'] 619243SN/A 6210146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 639243SN/A# that aims to model the most important system-level performance 649243SN/A# effects of a DRAM without getting into too much detail of the DRAM 659243SN/A# itself. 6610146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 6710146Sandreas.hansson@arm.com type = 'DRAMCtrl' 6810146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 699243SN/A 709243SN/A # single-ported on the system interface side, instantiate with a 719243SN/A # bus in front of the controller for multiple ports 729243SN/A port = SlavePort("Slave port") 739243SN/A 749243SN/A # the basic configuration of the controller architecture 7510145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 769972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 779243SN/A 7810140SN/A # threshold in percent for when to forcefully trigger writes and 7910140SN/A # start emptying the write buffer 8010140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 819972SN/A 8210140SN/A # threshold in percentage for when to start writes if the read 8310140SN/A # queue is empty 8410140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 8510140SN/A 8610140SN/A # minimum write bursts to schedule before switching back to reads 8710140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 8810140SN/A "switching to reads") 899243SN/A 909243SN/A # scheduler, address map and page policy 919489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9210136SN/A addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 9310145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 949243SN/A 9510141SN/A # enforce a limit on the number of accesses per row 9610141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 9710141SN/A "closing"); 9810141SN/A 999726SN/A # pipeline latency of the controller and PHY, split into a 1009726SN/A # frontend part and a backend part, with reads and writes serviced 1019726SN/A # by the queues only seeing the frontend contribution, and reads 1029726SN/A # serviced by the memory seeing the sum of the two 1039726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1049726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1059726SN/A 1069489SN/A # the physical organisation of the DRAM 1079831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1089831SN/A "device/chip") 1099831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1109831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1119831SN/A "device/chip") 1129831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1139489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 1149489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1159566SN/A # only used for the address mapping as the controller by 1169566SN/A # construction is a single channel and multiple controllers have 1179566SN/A # to be instantiated for a multi-channel configuration 1189566SN/A channels = Param.Unsigned(1, "Number of channels") 1199489SN/A 1209243SN/A # timing behaviour and constraints - all in nanoseconds 1219243SN/A 12210216Sandreas.hansson@arm.com # the base clock period of the DRAM 12310216Sandreas.hansson@arm.com tCK = Param.Latency("Clock period") 12410216Sandreas.hansson@arm.com 1259243SN/A # the amount of time in nanoseconds from issuing an activate command 1269243SN/A # to the data being available in the row buffer for a read/write 1279489SN/A tRCD = Param.Latency("RAS to CAS delay") 1289243SN/A 1299243SN/A # the time from issuing a read/write command to seeing the actual data 1309489SN/A tCL = Param.Latency("CAS latency") 1319243SN/A 1329243SN/A # minimum time between a precharge and subsequent activate 1339489SN/A tRP = Param.Latency("Row precharge time") 1349243SN/A 1359963SN/A # minimum time between an activate and a precharge to the same row 1369963SN/A tRAS = Param.Latency("ACT to PRE delay") 1379963SN/A 13810210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 13910210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 14010210Sandreas.hansson@arm.com 14110212Sandreas.hansson@arm.com # minimum time between a read and precharge command 14210212Sandreas.hansson@arm.com tRTP = Param.Latency("Read to precharge") 14310212Sandreas.hansson@arm.com 1449243SN/A # time to complete a burst transfer, typically the burst length 1459243SN/A # divided by two due to the DDR bus, but by making it a parameter 1469243SN/A # it is easier to also evaluate SDR memories like WideIO. 1479831SN/A # This parameter has to account for burst length. 1489831SN/A # Read/Write requests with data size larger than one full burst are broken 14910146Sandreas.hansson@arm.com # down into multiple requests in the controller 1509489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1519243SN/A 1529243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1539489SN/A tRFC = Param.Latency("Refresh cycle time") 1549243SN/A 1559243SN/A # refresh command interval, how often a "ref" command needs 1569243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1579489SN/A tREFI = Param.Latency("Refresh command interval") 1589243SN/A 15910206Sandreas.hansson@arm.com # write-to-read turn around penalty 1609489SN/A tWTR = Param.Latency("Write to read switching time") 1619243SN/A 16210206Sandreas.hansson@arm.com # read-to-write turn around penalty, bus turnaround delay 16310206Sandreas.hansson@arm.com tRTW = Param.Latency("Read to write switching time") 16410206Sandreas.hansson@arm.com 1659971SN/A # minimum row activate to row activate delay time 1669971SN/A tRRD = Param.Latency("ACT to ACT delay") 1679971SN/A 1689488SN/A # time window in which a maximum number of activates are allowed 1699488SN/A # to take place, set to 0 to disable 1709489SN/A tXAW = Param.Latency("X activation window") 1719489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 1729488SN/A 1739488SN/A # Currently rolled into other params 1749243SN/A ###################################################################### 1759243SN/A 1769963SN/A # tRC - assumed to be tRAS + tRP 1779243SN/A 1789728SN/A# A single DDR3 x64 interface (one command and address bus), with 1799728SN/A# default timings based on DDR3-1600 4 Gbit parts in an 8x8 1809728SN/A# configuration, which would amount to 4 Gbyte of memory. 18110146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 1829831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 1839831SN/A device_bus_width = 8 1849831SN/A 1859831SN/A # DDR3 is a BL8 device 1869831SN/A burst_length = 8 1879831SN/A 1889831SN/A # Each device has a page (row buffer) size of 1KB 1899728SN/A # (this depends on the memory density) 1909831SN/A device_rowbuffer_size = '1kB' 1919831SN/A 1929831SN/A # 8x8 configuration, so 8 devices 1939831SN/A devices_per_rank = 8 1949489SN/A 1959489SN/A # Use two ranks 1969489SN/A ranks_per_channel = 2 1979489SN/A 1989489SN/A # DDR3 has 8 banks in all configurations 1999489SN/A banks_per_rank = 8 2009489SN/A 20110216Sandreas.hansson@arm.com # 800 MHz 20210216Sandreas.hansson@arm.com tCK = '1.25ns' 20310216Sandreas.hansson@arm.com 2049970SN/A # DDR3-1600 11-11-11-28 2059489SN/A tRCD = '13.75ns' 2069489SN/A tCL = '13.75ns' 2079489SN/A tRP = '13.75ns' 2089970SN/A tRAS = '35ns' 20910210Sandreas.hansson@arm.com tWR = '15ns' 21010212Sandreas.hansson@arm.com tRTP = '7.5ns' 2119489SN/A 2129831SN/A # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 2139831SN/A # Note this is a BL8 DDR device. 2149489SN/A tBURST = '5ns' 2159489SN/A 2169728SN/A # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 2179489SN/A tRFC = '300ns' 2189489SN/A 2199489SN/A # DDR3, <=85C, half for >85C 2209489SN/A tREFI = '7.8us' 2219489SN/A 2229489SN/A # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 2239489SN/A tWTR = '7.5ns' 2249489SN/A 22510206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 22610206Sandreas.hansson@arm.com tRTW = '2.5ns' 22710206Sandreas.hansson@arm.com 2289971SN/A # Assume 5 CK for activate to activate for different banks 2299971SN/A tRRD = '6.25ns' 2309971SN/A 2319489SN/A # With a 2kbyte page size, DDR3-1600 lands around 40 ns 2329489SN/A tXAW = '40ns' 2339489SN/A activation_limit = 4 2349489SN/A 2359489SN/A 23610137SN/A# A single DDR3 x64 interface (one command and address bus), with 23710137SN/A# default timings based on DDR3-1333 4 Gbit parts in an 8x8 23810137SN/A# configuration, which would amount to 4 GByte of memory. This 23910137SN/A# configuration is primarily for comparing with DRAMSim2, and all the 24010137SN/A# parameters except ranks_per_channel are based on the DRAMSim2 config 24110137SN/A# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 24210137SN/A# to be manually set, depending on size of the memory to be 24310137SN/A# simulated. By default DRAMSim2 has 2048MB of memory with a single 24410137SN/A# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 24510146Sandreas.hansson@arm.comclass DDR3_1333_x64_DRAMSim2(DRAMCtrl): 24610137SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 24710137SN/A device_bus_width = 8 24810137SN/A 24910137SN/A # DDR3 is a BL8 device 25010137SN/A burst_length = 8 25110137SN/A 25210137SN/A # Each device has a page (row buffer) size of 1KB 25310137SN/A # (this depends on the memory density) 25410137SN/A device_rowbuffer_size = '1kB' 25510137SN/A 25610137SN/A # 8x8 configuration, so 8 devices 25710137SN/A devices_per_rank = 8 25810137SN/A 25910137SN/A # Use two ranks 26010137SN/A ranks_per_channel = 2 26110137SN/A 26210137SN/A # DDR3 has 8 banks in all configurations 26310137SN/A banks_per_rank = 8 26410137SN/A 26510216Sandreas.hansson@arm.com # 666 MHs 26610216Sandreas.hansson@arm.com tCK = '1.5ns' 26710216Sandreas.hansson@arm.com 26810137SN/A tRCD = '15ns' 26910137SN/A tCL = '15ns' 27010137SN/A tRP = '15ns' 27110137SN/A tRAS = '36ns' 27210210Sandreas.hansson@arm.com tWR = '15ns' 27310212Sandreas.hansson@arm.com tRTP = '7.5ns' 27410137SN/A 27510137SN/A # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 27610137SN/A # Note this is a BL8 DDR device. 27710137SN/A tBURST = '6ns' 27810137SN/A 27910137SN/A tRFC = '160ns' 28010137SN/A 28110137SN/A # DDR3, <=85C, half for >85C 28210137SN/A tREFI = '7.8us' 28310137SN/A 28410137SN/A # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 28510137SN/A tWTR = '7.5ns' 28610137SN/A 28710206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns 28810206Sandreas.hansson@arm.com tRTW = '3ns' 28910206Sandreas.hansson@arm.com 29010137SN/A tRRD = '6.0ns' 29110137SN/A 29210137SN/A tXAW = '30ns' 29310137SN/A activation_limit = 4 29410137SN/A 29510137SN/A 2969728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 2979728SN/A# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 2989728SN/A# configuration. 29910146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 3009831SN/A # 1x32 configuration, 1 device with a 32-bit interface 3019831SN/A device_bus_width = 32 3029831SN/A 3039831SN/A # LPDDR2_S4 is a BL4 and BL8 device 3049831SN/A burst_length = 8 3059831SN/A 3069831SN/A # Each device has a page (row buffer) size of 1KB 3079831SN/A # (this depends on the memory density) 3089831SN/A device_rowbuffer_size = '1kB' 3099831SN/A 3109831SN/A # 1x32 configuration, so 1 device 3119831SN/A devices_per_rank = 1 3129489SN/A 3139708SN/A # Use a single rank 3149708SN/A ranks_per_channel = 1 3159489SN/A 3169489SN/A # LPDDR2-S4 has 8 banks in all configurations 3179489SN/A banks_per_rank = 8 3189489SN/A 31910216Sandreas.hansson@arm.com # 533 MHz 32010216Sandreas.hansson@arm.com tCK = '1.876ns' 32110216Sandreas.hansson@arm.com 3229489SN/A # Fixed at 15 ns 3239489SN/A tRCD = '15ns' 3249489SN/A 3259489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 3269489SN/A tCL = '15ns' 3279489SN/A 3289728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 3299728SN/A tRP = '15ns' 3309489SN/A 3319970SN/A tRAS = '42ns' 33210210Sandreas.hansson@arm.com tWR = '15ns' 3339963SN/A 33410212Sandreas.hansson@arm.com # 6 CK read to precharge delay 33510212Sandreas.hansson@arm.com tRTP = '11.256ns' 33610212Sandreas.hansson@arm.com 3379831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 3389831SN/A # Note this is a BL8 DDR device. 3399831SN/A # Requests larger than 32 bytes are broken down into multiple requests 34010146Sandreas.hansson@arm.com # in the controller 3419831SN/A tBURST = '7.5ns' 3429489SN/A 3439708SN/A # LPDDR2-S4, 4 Gbit 3449489SN/A tRFC = '130ns' 3459489SN/A tREFI = '3.9us' 3469489SN/A 3479489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 3489489SN/A tWTR = '7.5ns' 3499489SN/A 35010206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns 35110206Sandreas.hansson@arm.com tRTW = '3.75ns' 35210206Sandreas.hansson@arm.com 3539971SN/A # Activate to activate irrespective of density and speed grade 3549971SN/A tRRD = '10.0ns' 3559971SN/A 3569708SN/A # Irrespective of density, tFAW is 50 ns 3579489SN/A tXAW = '50ns' 3589489SN/A activation_limit = 4 3599664SN/A 3609728SN/A# A single WideIO x128 interface (one command and address bus), with 3619728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 36210146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 3639831SN/A # 1x128 configuration, 1 device with a 128-bit interface 3649831SN/A device_bus_width = 128 3659831SN/A 3669831SN/A # This is a BL4 device 3679831SN/A burst_length = 4 3689831SN/A 3699831SN/A # Each device has a page (row buffer) size of 4KB 3709831SN/A # (this depends on the memory density) 3719831SN/A device_rowbuffer_size = '4kB' 3729831SN/A 3739831SN/A # 1x128 configuration, so 1 device 3749831SN/A devices_per_rank = 1 3759664SN/A 3769664SN/A # Use one rank for a one-high die stack 3779664SN/A ranks_per_channel = 1 3789664SN/A 3799664SN/A # WideIO has 4 banks in all configurations 3809664SN/A banks_per_rank = 4 3819664SN/A 38210216Sandreas.hansson@arm.com # 200 MHz 38310216Sandreas.hansson@arm.com tCK = '5ns' 38410216Sandreas.hansson@arm.com 3859664SN/A # WIO-200 3869664SN/A tRCD = '18ns' 3879664SN/A tCL = '18ns' 3889664SN/A tRP = '18ns' 3899970SN/A tRAS = '42ns' 39010210Sandreas.hansson@arm.com tWR = '15ns' 39110212Sandreas.hansson@arm.com # Read to precharge is same as the burst 39210212Sandreas.hansson@arm.com tRTP = '20ns' 3939664SN/A 3949831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 3959831SN/A # Note this is a BL4 SDR device. 3969664SN/A tBURST = '20ns' 3979664SN/A 3989664SN/A # WIO 8 Gb 3999664SN/A tRFC = '210ns' 4009664SN/A 4019664SN/A # WIO 8 Gb, <=85C, half for >85C 4029664SN/A tREFI = '3.9us' 4039664SN/A 4049664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 4059664SN/A tWTR = '15ns' 4069664SN/A 40710206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns 40810206Sandreas.hansson@arm.com tRTW = '10ns' 40910206Sandreas.hansson@arm.com 4109971SN/A # Activate to activate irrespective of density and speed grade 4119971SN/A tRRD = '10.0ns' 4129971SN/A 4139664SN/A # Two instead of four activation window 4149664SN/A tXAW = '50ns' 4159664SN/A activation_limit = 2 4169709SN/A 4179728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 4189728SN/A# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 4199728SN/A# configuration 42010146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 4219831SN/A # 1x32 configuration, 1 device with a 32-bit interface 4229831SN/A device_bus_width = 32 4239831SN/A 4249831SN/A # LPDDR3 is a BL8 device 4259831SN/A burst_length = 8 4269831SN/A 4279976SN/A # Each device has a page (row buffer) size of 4KB 4289976SN/A device_rowbuffer_size = '4kB' 4299831SN/A 4309831SN/A # 1x32 configuration, so 1 device 4319831SN/A devices_per_rank = 1 4329709SN/A 4339709SN/A # Use a single rank 4349709SN/A ranks_per_channel = 1 4359709SN/A 4369709SN/A # LPDDR3 has 8 banks in all configurations 4379709SN/A banks_per_rank = 8 4389709SN/A 43910216Sandreas.hansson@arm.com # 800 MHz 44010216Sandreas.hansson@arm.com tCK = '1.25ns' 44110216Sandreas.hansson@arm.com 4429709SN/A # Fixed at 15 ns 4439709SN/A tRCD = '15ns' 4449709SN/A 4459709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 4469709SN/A tCL = '15ns' 4479709SN/A 4489970SN/A tRAS = '42ns' 44910210Sandreas.hansson@arm.com tWR = '15ns' 4509963SN/A 45110212Sandreas.hansson@arm.com # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 45210212Sandreas.hansson@arm.com tRTP = '7.5ns' 45310212Sandreas.hansson@arm.com 4549728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 4559728SN/A tRP = '15ns' 4569709SN/A 4579831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 4589831SN/A # Note this is a BL8 DDR device. 4599831SN/A # Requests larger than 32 bytes are broken down into multiple requests 46010146Sandreas.hansson@arm.com # in the controller 4619831SN/A tBURST = '5ns' 4629709SN/A 4639709SN/A # LPDDR3, 4 Gb 4649709SN/A tRFC = '130ns' 4659709SN/A tREFI = '3.9us' 4669709SN/A 4679709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 4689709SN/A tWTR = '7.5ns' 4699709SN/A 47010206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 47110206Sandreas.hansson@arm.com tRTW = '2.5ns' 47210206Sandreas.hansson@arm.com 4739971SN/A # Activate to activate irrespective of density and speed grade 4749971SN/A tRRD = '10.0ns' 4759971SN/A 4769709SN/A # Irrespective of size, tFAW is 50 ns 4779709SN/A tXAW = '50ns' 4789709SN/A activation_limit = 4 479