DRAMCtrl.py revision 10210
110206Sandreas.hansson@arm.com# Copyright (c) 2012-2014 ARM Limited 29243SN/A# All rights reserved. 39243SN/A# 49243SN/A# The license below extends only to copyright in the software and shall 59243SN/A# not be construed as granting a license to any other intellectual 69243SN/A# property including but not limited to intellectual property relating 79243SN/A# to a hardware implementation of the functionality of the software 89243SN/A# licensed hereunder. You may use the software subject to the license 99243SN/A# terms below provided that you ensure that this notice is replicated 109243SN/A# unmodified and in its entirety in all distributions of the software, 119243SN/A# modified or unmodified, in source code or in binary form. 129243SN/A# 139831SN/A# Copyright (c) 2013 Amin Farmahini-Farahani 149831SN/A# All rights reserved. 159831SN/A# 169243SN/A# Redistribution and use in source and binary forms, with or without 179243SN/A# modification, are permitted provided that the following conditions are 189243SN/A# met: redistributions of source code must retain the above copyright 199243SN/A# notice, this list of conditions and the following disclaimer; 209243SN/A# redistributions in binary form must reproduce the above copyright 219243SN/A# notice, this list of conditions and the following disclaimer in the 229243SN/A# documentation and/or other materials provided with the distribution; 239243SN/A# neither the name of the copyright holders nor the names of its 249243SN/A# contributors may be used to endorse or promote products derived from 259243SN/A# this software without specific prior written permission. 269243SN/A# 279243SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 289243SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 299243SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 309243SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 319243SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 329243SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 339243SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 349243SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 359243SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 369243SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 379243SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 389243SN/A# 399243SN/A# Authors: Andreas Hansson 409243SN/A# Ani Udipi 419243SN/A 429243SN/Afrom m5.params import * 439243SN/Afrom AbstractMemory import * 449243SN/A 459243SN/A# Enum for memory scheduling algorithms, currently First-Come 469243SN/A# First-Served and a First-Row Hit then First-Come First-Served 479243SN/Aclass MemSched(Enum): vals = ['fcfs', 'frfcfs'] 489243SN/A 4910136SN/A# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 5010136SN/A# channel, rank, bank, row and column, respectively, and going from 5110136SN/A# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 5210136SN/A# suitable for an open-page policy, optimising for sequential accesses 5310136SN/A# hitting in the open row. For a closed-page policy, RoCoRaBaCh 5410136SN/A# maximises parallelism. 5510136SN/Aclass AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 569243SN/A 5710144SN/A# Enum for the page policy, either open, open_adaptive, close, or 5810144SN/A# close_adaptive. 5910144SN/Aclass PageManage(Enum): vals = ['open', 'open_adaptive', 'close', 6010144SN/A 'close_adaptive'] 619243SN/A 6210146Sandreas.hansson@arm.com# DRAMCtrl is a single-channel single-ported DRAM controller model 639243SN/A# that aims to model the most important system-level performance 649243SN/A# effects of a DRAM without getting into too much detail of the DRAM 659243SN/A# itself. 6610146Sandreas.hansson@arm.comclass DRAMCtrl(AbstractMemory): 6710146Sandreas.hansson@arm.com type = 'DRAMCtrl' 6810146Sandreas.hansson@arm.com cxx_header = "mem/dram_ctrl.hh" 699243SN/A 709243SN/A # single-ported on the system interface side, instantiate with a 719243SN/A # bus in front of the controller for multiple ports 729243SN/A port = SlavePort("Slave port") 739243SN/A 749243SN/A # the basic configuration of the controller architecture 7510145SN/A write_buffer_size = Param.Unsigned(64, "Number of write queue entries") 769972SN/A read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 779243SN/A 7810140SN/A # threshold in percent for when to forcefully trigger writes and 7910140SN/A # start emptying the write buffer 8010140SN/A write_high_thresh_perc = Param.Percent(85, "Threshold to force writes") 819972SN/A 8210140SN/A # threshold in percentage for when to start writes if the read 8310140SN/A # queue is empty 8410140SN/A write_low_thresh_perc = Param.Percent(50, "Threshold to start writes") 8510140SN/A 8610140SN/A # minimum write bursts to schedule before switching back to reads 8710140SN/A min_writes_per_switch = Param.Unsigned(16, "Minimum write bursts before " 8810140SN/A "switching to reads") 899243SN/A 909243SN/A # scheduler, address map and page policy 919489SN/A mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 9210136SN/A addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 9310145SN/A page_policy = Param.PageManage('open_adaptive', "Page management policy") 949243SN/A 9510141SN/A # enforce a limit on the number of accesses per row 9610141SN/A max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before " 9710141SN/A "closing"); 9810141SN/A 999726SN/A # pipeline latency of the controller and PHY, split into a 1009726SN/A # frontend part and a backend part, with reads and writes serviced 1019726SN/A # by the queues only seeing the frontend contribution, and reads 1029726SN/A # serviced by the memory seeing the sum of the two 1039726SN/A static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 1049726SN/A static_backend_latency = Param.Latency("10ns", "Static backend latency") 1059726SN/A 1069489SN/A # the physical organisation of the DRAM 1079831SN/A device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 1089831SN/A "device/chip") 1099831SN/A burst_length = Param.Unsigned("Burst lenght (BL) in beats") 1109831SN/A device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 1119831SN/A "device/chip") 1129831SN/A devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 1139489SN/A ranks_per_channel = Param.Unsigned("Number of ranks per channel") 1149489SN/A banks_per_rank = Param.Unsigned("Number of banks per rank") 1159566SN/A # only used for the address mapping as the controller by 1169566SN/A # construction is a single channel and multiple controllers have 1179566SN/A # to be instantiated for a multi-channel configuration 1189566SN/A channels = Param.Unsigned(1, "Number of channels") 1199489SN/A 1209243SN/A # timing behaviour and constraints - all in nanoseconds 1219243SN/A 1229243SN/A # the amount of time in nanoseconds from issuing an activate command 1239243SN/A # to the data being available in the row buffer for a read/write 1249489SN/A tRCD = Param.Latency("RAS to CAS delay") 1259243SN/A 1269243SN/A # the time from issuing a read/write command to seeing the actual data 1279489SN/A tCL = Param.Latency("CAS latency") 1289243SN/A 1299243SN/A # minimum time between a precharge and subsequent activate 1309489SN/A tRP = Param.Latency("Row precharge time") 1319243SN/A 1329963SN/A # minimum time between an activate and a precharge to the same row 1339963SN/A tRAS = Param.Latency("ACT to PRE delay") 1349963SN/A 13510210Sandreas.hansson@arm.com # minimum time between a write data transfer and a precharge 13610210Sandreas.hansson@arm.com tWR = Param.Latency("Write recovery time") 13710210Sandreas.hansson@arm.com 1389243SN/A # time to complete a burst transfer, typically the burst length 1399243SN/A # divided by two due to the DDR bus, but by making it a parameter 1409243SN/A # it is easier to also evaluate SDR memories like WideIO. 1419831SN/A # This parameter has to account for burst length. 1429831SN/A # Read/Write requests with data size larger than one full burst are broken 14310146Sandreas.hansson@arm.com # down into multiple requests in the controller 1449489SN/A tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 1459243SN/A 1469243SN/A # time taken to complete one refresh cycle (N rows in all banks) 1479489SN/A tRFC = Param.Latency("Refresh cycle time") 1489243SN/A 1499243SN/A # refresh command interval, how often a "ref" command needs 1509243SN/A # to be sent. It is 7.8 us for a 64ms refresh requirement 1519489SN/A tREFI = Param.Latency("Refresh command interval") 1529243SN/A 15310206Sandreas.hansson@arm.com # write-to-read turn around penalty 1549489SN/A tWTR = Param.Latency("Write to read switching time") 1559243SN/A 15610206Sandreas.hansson@arm.com # read-to-write turn around penalty, bus turnaround delay 15710206Sandreas.hansson@arm.com tRTW = Param.Latency("Read to write switching time") 15810206Sandreas.hansson@arm.com 1599971SN/A # minimum row activate to row activate delay time 1609971SN/A tRRD = Param.Latency("ACT to ACT delay") 1619971SN/A 1629488SN/A # time window in which a maximum number of activates are allowed 1639488SN/A # to take place, set to 0 to disable 1649489SN/A tXAW = Param.Latency("X activation window") 1659489SN/A activation_limit = Param.Unsigned("Max number of activates in window") 1669488SN/A 1679488SN/A # Currently rolled into other params 1689243SN/A ###################################################################### 1699243SN/A 1709963SN/A # tRC - assumed to be tRAS + tRP 1719243SN/A 1729728SN/A# A single DDR3 x64 interface (one command and address bus), with 1739728SN/A# default timings based on DDR3-1600 4 Gbit parts in an 8x8 1749728SN/A# configuration, which would amount to 4 Gbyte of memory. 17510146Sandreas.hansson@arm.comclass DDR3_1600_x64(DRAMCtrl): 1769831SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 1779831SN/A device_bus_width = 8 1789831SN/A 1799831SN/A # DDR3 is a BL8 device 1809831SN/A burst_length = 8 1819831SN/A 1829831SN/A # Each device has a page (row buffer) size of 1KB 1839728SN/A # (this depends on the memory density) 1849831SN/A device_rowbuffer_size = '1kB' 1859831SN/A 1869831SN/A # 8x8 configuration, so 8 devices 1879831SN/A devices_per_rank = 8 1889489SN/A 1899489SN/A # Use two ranks 1909489SN/A ranks_per_channel = 2 1919489SN/A 1929489SN/A # DDR3 has 8 banks in all configurations 1939489SN/A banks_per_rank = 8 1949489SN/A 1959970SN/A # DDR3-1600 11-11-11-28 1969489SN/A tRCD = '13.75ns' 1979489SN/A tCL = '13.75ns' 1989489SN/A tRP = '13.75ns' 1999970SN/A tRAS = '35ns' 20010210Sandreas.hansson@arm.com tWR = '15ns' 2019489SN/A 2029831SN/A # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 2039831SN/A # Note this is a BL8 DDR device. 2049489SN/A tBURST = '5ns' 2059489SN/A 2069728SN/A # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 2079489SN/A tRFC = '300ns' 2089489SN/A 2099489SN/A # DDR3, <=85C, half for >85C 2109489SN/A tREFI = '7.8us' 2119489SN/A 2129489SN/A # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 2139489SN/A tWTR = '7.5ns' 2149489SN/A 21510206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 21610206Sandreas.hansson@arm.com tRTW = '2.5ns' 21710206Sandreas.hansson@arm.com 2189971SN/A # Assume 5 CK for activate to activate for different banks 2199971SN/A tRRD = '6.25ns' 2209971SN/A 2219489SN/A # With a 2kbyte page size, DDR3-1600 lands around 40 ns 2229489SN/A tXAW = '40ns' 2239489SN/A activation_limit = 4 2249489SN/A 2259489SN/A 22610137SN/A# A single DDR3 x64 interface (one command and address bus), with 22710137SN/A# default timings based on DDR3-1333 4 Gbit parts in an 8x8 22810137SN/A# configuration, which would amount to 4 GByte of memory. This 22910137SN/A# configuration is primarily for comparing with DRAMSim2, and all the 23010137SN/A# parameters except ranks_per_channel are based on the DRAMSim2 config 23110137SN/A# file DDR3_micron_32M_8B_x8_sg15.ini. Note that ranks_per_channel has 23210137SN/A# to be manually set, depending on size of the memory to be 23310137SN/A# simulated. By default DRAMSim2 has 2048MB of memory with a single 23410137SN/A# rank. Therefore for 4 GByte memory, set ranks_per_channel = 2 23510146Sandreas.hansson@arm.comclass DDR3_1333_x64_DRAMSim2(DRAMCtrl): 23610137SN/A # 8x8 configuration, 8 devices each with an 8-bit interface 23710137SN/A device_bus_width = 8 23810137SN/A 23910137SN/A # DDR3 is a BL8 device 24010137SN/A burst_length = 8 24110137SN/A 24210137SN/A # Each device has a page (row buffer) size of 1KB 24310137SN/A # (this depends on the memory density) 24410137SN/A device_rowbuffer_size = '1kB' 24510137SN/A 24610137SN/A # 8x8 configuration, so 8 devices 24710137SN/A devices_per_rank = 8 24810137SN/A 24910137SN/A # Use two ranks 25010137SN/A ranks_per_channel = 2 25110137SN/A 25210137SN/A # DDR3 has 8 banks in all configurations 25310137SN/A banks_per_rank = 8 25410137SN/A 25510137SN/A tRCD = '15ns' 25610137SN/A tCL = '15ns' 25710137SN/A tRP = '15ns' 25810137SN/A tRAS = '36ns' 25910210Sandreas.hansson@arm.com tWR = '15ns' 26010137SN/A 26110137SN/A # 8 beats across an x64 interface translates to 4 clocks @ 666.66 MHz. 26210137SN/A # Note this is a BL8 DDR device. 26310137SN/A tBURST = '6ns' 26410137SN/A 26510137SN/A tRFC = '160ns' 26610137SN/A 26710137SN/A # DDR3, <=85C, half for >85C 26810137SN/A tREFI = '7.8us' 26910137SN/A 27010137SN/A # Greater of 4 CK or 7.5 ns, 4 CK @ 666.66 MHz = 6 ns 27110137SN/A tWTR = '7.5ns' 27210137SN/A 27310206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @666.66 MHz = 3 ns 27410206Sandreas.hansson@arm.com tRTW = '3ns' 27510206Sandreas.hansson@arm.com 27610137SN/A tRRD = '6.0ns' 27710137SN/A 27810137SN/A tXAW = '30ns' 27910137SN/A activation_limit = 4 28010137SN/A 28110137SN/A 2829728SN/A# A single LPDDR2-S4 x32 interface (one command/address bus), with 2839728SN/A# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 2849728SN/A# configuration. 28510146Sandreas.hansson@arm.comclass LPDDR2_S4_1066_x32(DRAMCtrl): 2869831SN/A # 1x32 configuration, 1 device with a 32-bit interface 2879831SN/A device_bus_width = 32 2889831SN/A 2899831SN/A # LPDDR2_S4 is a BL4 and BL8 device 2909831SN/A burst_length = 8 2919831SN/A 2929831SN/A # Each device has a page (row buffer) size of 1KB 2939831SN/A # (this depends on the memory density) 2949831SN/A device_rowbuffer_size = '1kB' 2959831SN/A 2969831SN/A # 1x32 configuration, so 1 device 2979831SN/A devices_per_rank = 1 2989489SN/A 2999708SN/A # Use a single rank 3009708SN/A ranks_per_channel = 1 3019489SN/A 3029489SN/A # LPDDR2-S4 has 8 banks in all configurations 3039489SN/A banks_per_rank = 8 3049489SN/A 3059489SN/A # Fixed at 15 ns 3069489SN/A tRCD = '15ns' 3079489SN/A 3089489SN/A # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 3099489SN/A tCL = '15ns' 3109489SN/A 3119728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 3129728SN/A tRP = '15ns' 3139489SN/A 3149970SN/A tRAS = '42ns' 31510210Sandreas.hansson@arm.com tWR = '15ns' 3169963SN/A 3179831SN/A # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 3189831SN/A # Note this is a BL8 DDR device. 3199831SN/A # Requests larger than 32 bytes are broken down into multiple requests 32010146Sandreas.hansson@arm.com # in the controller 3219831SN/A tBURST = '7.5ns' 3229489SN/A 3239708SN/A # LPDDR2-S4, 4 Gbit 3249489SN/A tRFC = '130ns' 3259489SN/A tREFI = '3.9us' 3269489SN/A 3279489SN/A # Irrespective of speed grade, tWTR is 7.5 ns 3289489SN/A tWTR = '7.5ns' 3299489SN/A 33010206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @533 MHz = 3.75 ns 33110206Sandreas.hansson@arm.com tRTW = '3.75ns' 33210206Sandreas.hansson@arm.com 3339971SN/A # Activate to activate irrespective of density and speed grade 3349971SN/A tRRD = '10.0ns' 3359971SN/A 3369708SN/A # Irrespective of density, tFAW is 50 ns 3379489SN/A tXAW = '50ns' 3389489SN/A activation_limit = 4 3399664SN/A 3409728SN/A# A single WideIO x128 interface (one command and address bus), with 3419728SN/A# default timings based on an estimated WIO-200 8 Gbit part. 34210146Sandreas.hansson@arm.comclass WideIO_200_x128(DRAMCtrl): 3439831SN/A # 1x128 configuration, 1 device with a 128-bit interface 3449831SN/A device_bus_width = 128 3459831SN/A 3469831SN/A # This is a BL4 device 3479831SN/A burst_length = 4 3489831SN/A 3499831SN/A # Each device has a page (row buffer) size of 4KB 3509831SN/A # (this depends on the memory density) 3519831SN/A device_rowbuffer_size = '4kB' 3529831SN/A 3539831SN/A # 1x128 configuration, so 1 device 3549831SN/A devices_per_rank = 1 3559664SN/A 3569664SN/A # Use one rank for a one-high die stack 3579664SN/A ranks_per_channel = 1 3589664SN/A 3599664SN/A # WideIO has 4 banks in all configurations 3609664SN/A banks_per_rank = 4 3619664SN/A 3629664SN/A # WIO-200 3639664SN/A tRCD = '18ns' 3649664SN/A tCL = '18ns' 3659664SN/A tRP = '18ns' 3669970SN/A tRAS = '42ns' 36710210Sandreas.hansson@arm.com tWR = '15ns' 3689664SN/A 3699831SN/A # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 3709831SN/A # Note this is a BL4 SDR device. 3719664SN/A tBURST = '20ns' 3729664SN/A 3739664SN/A # WIO 8 Gb 3749664SN/A tRFC = '210ns' 3759664SN/A 3769664SN/A # WIO 8 Gb, <=85C, half for >85C 3779664SN/A tREFI = '3.9us' 3789664SN/A 3799664SN/A # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 3809664SN/A tWTR = '15ns' 3819664SN/A 38210206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @200 MHz = 10 ns 38310206Sandreas.hansson@arm.com tRTW = '10ns' 38410206Sandreas.hansson@arm.com 3859971SN/A # Activate to activate irrespective of density and speed grade 3869971SN/A tRRD = '10.0ns' 3879971SN/A 3889664SN/A # Two instead of four activation window 3899664SN/A tXAW = '50ns' 3909664SN/A activation_limit = 2 3919709SN/A 3929728SN/A# A single LPDDR3 x32 interface (one command/address bus), with 3939728SN/A# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 3949728SN/A# configuration 39510146Sandreas.hansson@arm.comclass LPDDR3_1600_x32(DRAMCtrl): 3969831SN/A # 1x32 configuration, 1 device with a 32-bit interface 3979831SN/A device_bus_width = 32 3989831SN/A 3999831SN/A # LPDDR3 is a BL8 device 4009831SN/A burst_length = 8 4019831SN/A 4029976SN/A # Each device has a page (row buffer) size of 4KB 4039976SN/A device_rowbuffer_size = '4kB' 4049831SN/A 4059831SN/A # 1x32 configuration, so 1 device 4069831SN/A devices_per_rank = 1 4079709SN/A 4089709SN/A # Use a single rank 4099709SN/A ranks_per_channel = 1 4109709SN/A 4119709SN/A # LPDDR3 has 8 banks in all configurations 4129709SN/A banks_per_rank = 8 4139709SN/A 4149709SN/A # Fixed at 15 ns 4159709SN/A tRCD = '15ns' 4169709SN/A 4179709SN/A # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 4189709SN/A tCL = '15ns' 4199709SN/A 4209970SN/A tRAS = '42ns' 42110210Sandreas.hansson@arm.com tWR = '15ns' 4229963SN/A 4239728SN/A # Pre-charge one bank 15 ns (all banks 18 ns) 4249728SN/A tRP = '15ns' 4259709SN/A 4269831SN/A # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 4279831SN/A # Note this is a BL8 DDR device. 4289831SN/A # Requests larger than 32 bytes are broken down into multiple requests 42910146Sandreas.hansson@arm.com # in the controller 4309831SN/A tBURST = '5ns' 4319709SN/A 4329709SN/A # LPDDR3, 4 Gb 4339709SN/A tRFC = '130ns' 4349709SN/A tREFI = '3.9us' 4359709SN/A 4369709SN/A # Irrespective of speed grade, tWTR is 7.5 ns 4379709SN/A tWTR = '7.5ns' 4389709SN/A 43910206Sandreas.hansson@arm.com # Default read-to-write bus around to 2 CK, @800 MHz = 2.5 ns 44010206Sandreas.hansson@arm.com tRTW = '2.5ns' 44110206Sandreas.hansson@arm.com 4429971SN/A # Activate to activate irrespective of density and speed grade 4439971SN/A tRRD = '10.0ns' 4449971SN/A 4459709SN/A # Irrespective of size, tFAW is 50 ns 4469709SN/A tXAW = '50ns' 4479709SN/A activation_limit = 4 448