DRAMCtrl.py revision 10136
1# Copyright (c) 2012-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2013 Amin Farmahini-Farahani 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Andreas Hansson 40# Ani Udipi 41 42from m5.params import * 43from AbstractMemory import * 44 45# Enum for memory scheduling algorithms, currently First-Come 46# First-Served and a First-Row Hit then First-Come First-Served 47class MemSched(Enum): vals = ['fcfs', 'frfcfs'] 48 49# Enum for the address mapping. With Ch, Ra, Ba, Ro and Co denoting 50# channel, rank, bank, row and column, respectively, and going from 51# MSB to LSB. Available are RoRaBaChCo and RoRaBaCoCh, that are 52# suitable for an open-page policy, optimising for sequential accesses 53# hitting in the open row. For a closed-page policy, RoCoRaBaCh 54# maximises parallelism. 55class AddrMap(Enum): vals = ['RoRaBaChCo', 'RoRaBaCoCh', 'RoCoRaBaCh'] 56 57# Enum for the page policy, either open, open_adaptive or close. 58class PageManage(Enum): vals = ['open', 'open_adaptive', 'close'] 59 60# SimpleDRAM is a single-channel single-ported DRAM controller model 61# that aims to model the most important system-level performance 62# effects of a DRAM without getting into too much detail of the DRAM 63# itself. 64class SimpleDRAM(AbstractMemory): 65 type = 'SimpleDRAM' 66 cxx_header = "mem/simple_dram.hh" 67 68 # single-ported on the system interface side, instantiate with a 69 # bus in front of the controller for multiple ports 70 port = SlavePort("Slave port") 71 72 # the basic configuration of the controller architecture 73 write_buffer_size = Param.Unsigned(32, "Number of write queue entries") 74 read_buffer_size = Param.Unsigned(32, "Number of read queue entries") 75 76 # threshold in percent for when to trigger writes and start 77 # emptying the write buffer as it starts to get full 78 write_high_thresh_perc = Param.Percent(70, "Threshold to trigger writes") 79 80 # threshold in percentage for when to stop writes if the read 81 # queue has an entry. An optimisaton to give reads priority if 82 # sufficient number of writes are scheduled and write queue has 83 # sufficient number of free entries 84 write_low_thresh_perc = Param.Percent(0, "Threshold to stop writes") 85 86 # scheduler, address map and page policy 87 mem_sched_policy = Param.MemSched('frfcfs', "Memory scheduling policy") 88 addr_mapping = Param.AddrMap('RoRaBaChCo', "Address mapping policy") 89 page_policy = Param.PageManage('open', "Page closure management policy") 90 91 # pipeline latency of the controller and PHY, split into a 92 # frontend part and a backend part, with reads and writes serviced 93 # by the queues only seeing the frontend contribution, and reads 94 # serviced by the memory seeing the sum of the two 95 static_frontend_latency = Param.Latency("10ns", "Static frontend latency") 96 static_backend_latency = Param.Latency("10ns", "Static backend latency") 97 98 # the physical organisation of the DRAM 99 device_bus_width = Param.Unsigned("data bus width in bits for each DRAM "\ 100 "device/chip") 101 burst_length = Param.Unsigned("Burst lenght (BL) in beats") 102 device_rowbuffer_size = Param.MemorySize("Page (row buffer) size per "\ 103 "device/chip") 104 devices_per_rank = Param.Unsigned("Number of devices/chips per rank") 105 ranks_per_channel = Param.Unsigned("Number of ranks per channel") 106 banks_per_rank = Param.Unsigned("Number of banks per rank") 107 # only used for the address mapping as the controller by 108 # construction is a single channel and multiple controllers have 109 # to be instantiated for a multi-channel configuration 110 channels = Param.Unsigned(1, "Number of channels") 111 112 # timing behaviour and constraints - all in nanoseconds 113 114 # the amount of time in nanoseconds from issuing an activate command 115 # to the data being available in the row buffer for a read/write 116 tRCD = Param.Latency("RAS to CAS delay") 117 118 # the time from issuing a read/write command to seeing the actual data 119 tCL = Param.Latency("CAS latency") 120 121 # minimum time between a precharge and subsequent activate 122 tRP = Param.Latency("Row precharge time") 123 124 # minimum time between an activate and a precharge to the same row 125 tRAS = Param.Latency("ACT to PRE delay") 126 127 # time to complete a burst transfer, typically the burst length 128 # divided by two due to the DDR bus, but by making it a parameter 129 # it is easier to also evaluate SDR memories like WideIO. 130 # This parameter has to account for burst length. 131 # Read/Write requests with data size larger than one full burst are broken 132 # down into multiple requests in the SimpleDRAM controller 133 tBURST = Param.Latency("Burst duration (for DDR burst length / 2 cycles)") 134 135 # time taken to complete one refresh cycle (N rows in all banks) 136 tRFC = Param.Latency("Refresh cycle time") 137 138 # refresh command interval, how often a "ref" command needs 139 # to be sent. It is 7.8 us for a 64ms refresh requirement 140 tREFI = Param.Latency("Refresh command interval") 141 142 # write-to-read turn around penalty, assumed same as read-to-write 143 tWTR = Param.Latency("Write to read switching time") 144 145 # minimum row activate to row activate delay time 146 tRRD = Param.Latency("ACT to ACT delay") 147 148 # time window in which a maximum number of activates are allowed 149 # to take place, set to 0 to disable 150 tXAW = Param.Latency("X activation window") 151 activation_limit = Param.Unsigned("Max number of activates in window") 152 153 # Currently rolled into other params 154 ###################################################################### 155 156 # tRC - assumed to be tRAS + tRP 157 158# A single DDR3 x64 interface (one command and address bus), with 159# default timings based on DDR3-1600 4 Gbit parts in an 8x8 160# configuration, which would amount to 4 Gbyte of memory. 161class DDR3_1600_x64(SimpleDRAM): 162 # 8x8 configuration, 8 devices each with an 8-bit interface 163 device_bus_width = 8 164 165 # DDR3 is a BL8 device 166 burst_length = 8 167 168 # Each device has a page (row buffer) size of 1KB 169 # (this depends on the memory density) 170 device_rowbuffer_size = '1kB' 171 172 # 8x8 configuration, so 8 devices 173 devices_per_rank = 8 174 175 # Use two ranks 176 ranks_per_channel = 2 177 178 # DDR3 has 8 banks in all configurations 179 banks_per_rank = 8 180 181 # DDR3-1600 11-11-11-28 182 tRCD = '13.75ns' 183 tCL = '13.75ns' 184 tRP = '13.75ns' 185 tRAS = '35ns' 186 187 # 8 beats across an x64 interface translates to 4 clocks @ 800 MHz. 188 # Note this is a BL8 DDR device. 189 tBURST = '5ns' 190 191 # DDR3, 4 Gbit has a tRFC of 240 CK and tCK = 1.25 ns 192 tRFC = '300ns' 193 194 # DDR3, <=85C, half for >85C 195 tREFI = '7.8us' 196 197 # Greater of 4 CK or 7.5 ns, 4 CK @ 800 MHz = 5 ns 198 tWTR = '7.5ns' 199 200 # Assume 5 CK for activate to activate for different banks 201 tRRD = '6.25ns' 202 203 # With a 2kbyte page size, DDR3-1600 lands around 40 ns 204 tXAW = '40ns' 205 activation_limit = 4 206 207 208# A single LPDDR2-S4 x32 interface (one command/address bus), with 209# default timings based on a LPDDR2-1066 4 Gbit part in a 1x32 210# configuration. 211class LPDDR2_S4_1066_x32(SimpleDRAM): 212 # 1x32 configuration, 1 device with a 32-bit interface 213 device_bus_width = 32 214 215 # LPDDR2_S4 is a BL4 and BL8 device 216 burst_length = 8 217 218 # Each device has a page (row buffer) size of 1KB 219 # (this depends on the memory density) 220 device_rowbuffer_size = '1kB' 221 222 # 1x32 configuration, so 1 device 223 devices_per_rank = 1 224 225 # Use a single rank 226 ranks_per_channel = 1 227 228 # LPDDR2-S4 has 8 banks in all configurations 229 banks_per_rank = 8 230 231 # Fixed at 15 ns 232 tRCD = '15ns' 233 234 # 8 CK read latency, 4 CK write latency @ 533 MHz, 1.876 ns cycle time 235 tCL = '15ns' 236 237 # Pre-charge one bank 15 ns (all banks 18 ns) 238 tRP = '15ns' 239 240 tRAS = '42ns' 241 242 # 8 beats across an x32 DDR interface translates to 4 clocks @ 533 MHz. 243 # Note this is a BL8 DDR device. 244 # Requests larger than 32 bytes are broken down into multiple requests 245 # in the SimpleDRAM controller 246 tBURST = '7.5ns' 247 248 # LPDDR2-S4, 4 Gbit 249 tRFC = '130ns' 250 tREFI = '3.9us' 251 252 # Irrespective of speed grade, tWTR is 7.5 ns 253 tWTR = '7.5ns' 254 255 # Activate to activate irrespective of density and speed grade 256 tRRD = '10.0ns' 257 258 # Irrespective of density, tFAW is 50 ns 259 tXAW = '50ns' 260 activation_limit = 4 261 262# A single WideIO x128 interface (one command and address bus), with 263# default timings based on an estimated WIO-200 8 Gbit part. 264class WideIO_200_x128(SimpleDRAM): 265 # 1x128 configuration, 1 device with a 128-bit interface 266 device_bus_width = 128 267 268 # This is a BL4 device 269 burst_length = 4 270 271 # Each device has a page (row buffer) size of 4KB 272 # (this depends on the memory density) 273 device_rowbuffer_size = '4kB' 274 275 # 1x128 configuration, so 1 device 276 devices_per_rank = 1 277 278 # Use one rank for a one-high die stack 279 ranks_per_channel = 1 280 281 # WideIO has 4 banks in all configurations 282 banks_per_rank = 4 283 284 # WIO-200 285 tRCD = '18ns' 286 tCL = '18ns' 287 tRP = '18ns' 288 tRAS = '42ns' 289 290 # 4 beats across an x128 SDR interface translates to 4 clocks @ 200 MHz. 291 # Note this is a BL4 SDR device. 292 tBURST = '20ns' 293 294 # WIO 8 Gb 295 tRFC = '210ns' 296 297 # WIO 8 Gb, <=85C, half for >85C 298 tREFI = '3.9us' 299 300 # Greater of 2 CK or 15 ns, 2 CK @ 200 MHz = 10 ns 301 tWTR = '15ns' 302 303 # Activate to activate irrespective of density and speed grade 304 tRRD = '10.0ns' 305 306 # Two instead of four activation window 307 tXAW = '50ns' 308 activation_limit = 2 309 310# A single LPDDR3 x32 interface (one command/address bus), with 311# default timings based on a LPDDR3-1600 4 Gbit part in a 1x32 312# configuration 313class LPDDR3_1600_x32(SimpleDRAM): 314 # 1x32 configuration, 1 device with a 32-bit interface 315 device_bus_width = 32 316 317 # LPDDR3 is a BL8 device 318 burst_length = 8 319 320 # Each device has a page (row buffer) size of 4KB 321 device_rowbuffer_size = '4kB' 322 323 # 1x32 configuration, so 1 device 324 devices_per_rank = 1 325 326 # Use a single rank 327 ranks_per_channel = 1 328 329 # LPDDR3 has 8 banks in all configurations 330 banks_per_rank = 8 331 332 # Fixed at 15 ns 333 tRCD = '15ns' 334 335 # 12 CK read latency, 6 CK write latency @ 800 MHz, 1.25 ns cycle time 336 tCL = '15ns' 337 338 tRAS = '42ns' 339 340 # Pre-charge one bank 15 ns (all banks 18 ns) 341 tRP = '15ns' 342 343 # 8 beats across a x32 DDR interface translates to 4 clocks @ 800 MHz. 344 # Note this is a BL8 DDR device. 345 # Requests larger than 32 bytes are broken down into multiple requests 346 # in the SimpleDRAM controller 347 tBURST = '5ns' 348 349 # LPDDR3, 4 Gb 350 tRFC = '130ns' 351 tREFI = '3.9us' 352 353 # Irrespective of speed grade, tWTR is 7.5 ns 354 tWTR = '7.5ns' 355 356 # Activate to activate irrespective of density and speed grade 357 tRRD = '10.0ns' 358 359 # Irrespective of size, tFAW is 50 ns 360 tXAW = '50ns' 361 activation_limit = 4 362