1/*
2 * Copyright (c) 2017 Jason Lowe-Power
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/**
30 * This file contains the messages and other types for a simple MSI protocol.
31 *
32 * The protocol in this file is based off of the MSI protocol found in
33 * A Primer on Memory Consistency and Cache Coherence
34 *      Daniel J. Sorin, Mark D. Hill, and David A. Wood
35 *      Synthesis Lectures on Computer Architecture 2011 6:3, 141-149
36 *
37 * See Learning gem5 Part 3: Ruby for more details.
38 *
39 * Authors: Jason Lowe-Power
40 */
41
42enumeration(CoherenceRequestType, desc="Types of request messages") {
43    GetS,       desc="Request from cache for a block with read permission";
44    GetM,       desc="Request from cache for a block with write permission";
45    PutS,       desc="Sent to directory when evicting a block in S (clean WB)";
46    PutM,       desc="Sent to directory when evicting a block in M";
47
48    // "Requests" from the directory to the caches on the fwd network
49    Inv,        desc="Probe the cache and invalidate any matching blocks";
50    PutAck,     desc="The put request has been processed.";
51}
52
53enumeration(CoherenceResponseType, desc="Types of response messages") {
54    Data,       desc="Contains the most up-to-date data";
55    InvAck,     desc="Message from another cache that they have inv. the blk";
56}
57
58structure(RequestMsg, desc="Used for Cache->Dir and Fwd messages",
59          interface="Message") {
60    // NOTE: You can't name addr "Addr" because it would conflict with the
61    // Addr *type*.
62    Addr addr,                   desc="Physical address for this request";
63    CoherenceRequestType Type,   desc="Type of request";
64    MachineID Requestor,         desc="Node who initiated the request";
65    NetDest Destination,         desc="Multicast destination mask";
66    DataBlock DataBlk,           desc="data for the cache line";
67    // NOTE: You *must* use MessageSize as the name of this variable, and it's
68    // required that you have a MessageSize for each type of message. You will
69    // the the error "panic: MessageSizeType() called on wrong message!"
70    MessageSizeType MessageSize, desc="size category of the message";
71
72    // This must be overridden here to support functional accesses
73    bool functionalRead(Packet *pkt) {
74        // Requests should never have the only copy of the most up-to-date data
75        return false;
76    }
77
78    bool functionalWrite(Packet *pkt) {
79        // No check on message type required since the protocol should read
80        // data block from only those messages that contain valid data
81        return testAndWrite(addr, DataBlk, pkt);
82    }
83}
84
85structure(ResponseMsg, desc="Used for Cache->Dir and Fwd messages",
86          interface="Message") {
87    Addr addr,                   desc="Physical address for this response";
88    CoherenceResponseType Type,  desc="Type of response";
89    MachineID Sender,            desc="Node who is responding to the request";
90    NetDest Destination,         desc="Multicast destination mask";
91    DataBlock DataBlk,           desc="data for the cache line";
92    MessageSizeType MessageSize, desc="size category of the message";
93    int Acks,                    desc="Number of acks required from others";
94
95    // This must be overridden here to support functional accesses
96    bool functionalRead(Packet *pkt) {
97        if (Type == CoherenceResponseType:Data) {
98            return testAndRead(addr, DataBlk, pkt);
99        }
100        return false;
101    }
102
103    bool functionalWrite(Packet *pkt) {
104        // No check on message type required since the protocol should read
105        // data block from only those messages that contain valid data
106        return testAndWrite(addr, DataBlk, pkt);
107    }
108}
109