wavefront.hh revision 11641
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. Redistributions in binary form must reproduce the above copyright notice, 1411308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer in the documentation 1511308Santhony.gutierrez@amd.com * and/or other materials provided with the distribution. 1611308Santhony.gutierrez@amd.com * 1711308Santhony.gutierrez@amd.com * 3. Neither the name of the copyright holder nor the names of its contributors 1811308Santhony.gutierrez@amd.com * may be used to endorse or promote products derived from this software 1911308Santhony.gutierrez@amd.com * without specific prior written permission. 2011308Santhony.gutierrez@amd.com * 2111308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2211308Santhony.gutierrez@amd.com * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2311308Santhony.gutierrez@amd.com * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2411308Santhony.gutierrez@amd.com * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3311308Santhony.gutierrez@amd.com * Author: Lisa Hsu 3411308Santhony.gutierrez@amd.com */ 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.com#ifndef __WAVEFRONT_HH__ 3711308Santhony.gutierrez@amd.com#define __WAVEFRONT_HH__ 3811308Santhony.gutierrez@amd.com 3911308Santhony.gutierrez@amd.com#include <cassert> 4011308Santhony.gutierrez@amd.com#include <deque> 4111308Santhony.gutierrez@amd.com#include <memory> 4211308Santhony.gutierrez@amd.com#include <stack> 4311308Santhony.gutierrez@amd.com#include <vector> 4411308Santhony.gutierrez@amd.com 4511308Santhony.gutierrez@amd.com#include "base/misc.hh" 4611308Santhony.gutierrez@amd.com#include "base/types.hh" 4711308Santhony.gutierrez@amd.com#include "gpu-compute/condition_register_state.hh" 4811308Santhony.gutierrez@amd.com#include "gpu-compute/lds_state.hh" 4911308Santhony.gutierrez@amd.com#include "gpu-compute/misc.hh" 5011308Santhony.gutierrez@amd.com#include "params/Wavefront.hh" 5111308Santhony.gutierrez@amd.com#include "sim/sim_object.hh" 5211308Santhony.gutierrez@amd.com 5311308Santhony.gutierrez@amd.comstatic const int MAX_NUM_INSTS_PER_WF = 12; 5411308Santhony.gutierrez@amd.com 5511641Salexandru.dutu@amd.com/** 5611641Salexandru.dutu@amd.com * A reconvergence stack entry conveys the necessary state to implement 5711641Salexandru.dutu@amd.com * control flow divergence. 5811641Salexandru.dutu@amd.com */ 5911641Salexandru.dutu@amd.comstruct ReconvergenceStackEntry { 6011641Salexandru.dutu@amd.com /** 6111641Salexandru.dutu@amd.com * PC of current instruction. 6211641Salexandru.dutu@amd.com */ 6311641Salexandru.dutu@amd.com uint32_t pc; 6411641Salexandru.dutu@amd.com /** 6511641Salexandru.dutu@amd.com * PC of the immediate post-dominator instruction, i.e., the value of 6611641Salexandru.dutu@amd.com * @a pc for the first instruction that will be executed by the wavefront 6711641Salexandru.dutu@amd.com * when a reconvergence point is reached. 6811641Salexandru.dutu@amd.com */ 6911641Salexandru.dutu@amd.com uint32_t rpc; 7011641Salexandru.dutu@amd.com /** 7111641Salexandru.dutu@amd.com * Execution mask. 7211641Salexandru.dutu@amd.com */ 7311641Salexandru.dutu@amd.com VectorMask execMask; 7411641Salexandru.dutu@amd.com}; 7511641Salexandru.dutu@amd.com 7611308Santhony.gutierrez@amd.com/* 7711308Santhony.gutierrez@amd.com * Arguments for the hsail opcode call, are user defined and variable length. 7811308Santhony.gutierrez@amd.com * The hardware/finalizer can support arguments in hardware or use memory to 7911308Santhony.gutierrez@amd.com * pass arguments. For now, let's assume that an unlimited number of arguments 8011308Santhony.gutierrez@amd.com * are supported in hardware (the compiler inlines functions whenver it can 8111308Santhony.gutierrez@amd.com * anyways, so unless someone is interested in the implications of linking/ 8211308Santhony.gutierrez@amd.com * library functions, I think this is a reasonable assumption given the typical 8311308Santhony.gutierrez@amd.com * size of an OpenCL kernel). 8411308Santhony.gutierrez@amd.com * 8511308Santhony.gutierrez@amd.com * Note that call args are different than kernel arguments: 8611308Santhony.gutierrez@amd.com * * All work-items in a kernel refer the same set of kernel arguments 8711308Santhony.gutierrez@amd.com * * Each work-item has it's on set of call args. So a call argument at 8811308Santhony.gutierrez@amd.com * address 0x4 is different for work-item 0 and work-item 1. 8911308Santhony.gutierrez@amd.com * 9011308Santhony.gutierrez@amd.com * Ok, the table below shows an example of how we organize the call arguments in 9111308Santhony.gutierrez@amd.com * the CallArgMem class. 9211308Santhony.gutierrez@amd.com * 9311308Santhony.gutierrez@amd.com * int foo(int arg1, double arg2) 9411308Santhony.gutierrez@amd.com * ___________________________________________________ 9511308Santhony.gutierrez@amd.com * | 0: return.0 | 4: return.1 | ... | 252: return.63 | 9611308Santhony.gutierrez@amd.com * |---------------------------------------------------| 9711308Santhony.gutierrez@amd.com * | 256: arg1.0 | 260: arg1.1 | ... | 508: arg1.63 | 9811308Santhony.gutierrez@amd.com * |---------------------------------------------------| 9911308Santhony.gutierrez@amd.com * | 512: arg2.0 | 520: arg2.1 | ... | 1016: arg2.63 | 10011308Santhony.gutierrez@amd.com * ___________________________________________________ 10111308Santhony.gutierrez@amd.com */ 10211308Santhony.gutierrez@amd.comclass CallArgMem 10311308Santhony.gutierrez@amd.com{ 10411308Santhony.gutierrez@amd.com public: 10511308Santhony.gutierrez@amd.com // pointer to buffer for storing function arguments 10611308Santhony.gutierrez@amd.com uint8_t *mem; 10711534Sjohn.kalamatianos@amd.com int wfSize; 10811308Santhony.gutierrez@amd.com // size of function args 10911308Santhony.gutierrez@amd.com int funcArgsSizePerItem; 11011308Santhony.gutierrez@amd.com 11111308Santhony.gutierrez@amd.com template<typename CType> 11211308Santhony.gutierrez@amd.com int 11311308Santhony.gutierrez@amd.com getLaneOffset(int lane, int addr) 11411308Santhony.gutierrez@amd.com { 11511534Sjohn.kalamatianos@amd.com return addr * wfSize + sizeof(CType) * lane; 11611308Santhony.gutierrez@amd.com } 11711308Santhony.gutierrez@amd.com 11811534Sjohn.kalamatianos@amd.com CallArgMem(int func_args_size_per_item, int wf_size) 11911534Sjohn.kalamatianos@amd.com : wfSize(wf_size), funcArgsSizePerItem(func_args_size_per_item) 12011308Santhony.gutierrez@amd.com { 12111534Sjohn.kalamatianos@amd.com mem = (uint8_t*)malloc(funcArgsSizePerItem * wfSize); 12211308Santhony.gutierrez@amd.com } 12311308Santhony.gutierrez@amd.com 12411308Santhony.gutierrez@amd.com ~CallArgMem() 12511308Santhony.gutierrez@amd.com { 12611308Santhony.gutierrez@amd.com free(mem); 12711308Santhony.gutierrez@amd.com } 12811308Santhony.gutierrez@amd.com 12911308Santhony.gutierrez@amd.com template<typename CType> 13011308Santhony.gutierrez@amd.com uint8_t* 13111308Santhony.gutierrez@amd.com getLaneAddr(int lane, int addr) 13211308Santhony.gutierrez@amd.com { 13311308Santhony.gutierrez@amd.com return mem + getLaneOffset<CType>(lane, addr); 13411308Santhony.gutierrez@amd.com } 13511308Santhony.gutierrez@amd.com 13611308Santhony.gutierrez@amd.com template<typename CType> 13711308Santhony.gutierrez@amd.com void 13811308Santhony.gutierrez@amd.com setLaneAddr(int lane, int addr, CType val) 13911308Santhony.gutierrez@amd.com { 14011308Santhony.gutierrez@amd.com *((CType*)(mem + getLaneOffset<CType>(lane, addr))) = val; 14111308Santhony.gutierrez@amd.com } 14211308Santhony.gutierrez@amd.com}; 14311308Santhony.gutierrez@amd.com 14411308Santhony.gutierrez@amd.comclass Wavefront : public SimObject 14511308Santhony.gutierrez@amd.com{ 14611308Santhony.gutierrez@amd.com public: 14711308Santhony.gutierrez@amd.com enum itype_e {I_ALU,I_GLOBAL,I_SHARED,I_FLAT,I_PRIVATE}; 14811308Santhony.gutierrez@amd.com enum status_e {S_STOPPED,S_RETURNING,S_RUNNING}; 14911308Santhony.gutierrez@amd.com 15011308Santhony.gutierrez@amd.com // Base pointer for array of instruction pointers 15111639Salexandru.dutu@amd.com uint64_t basePtr; 15211308Santhony.gutierrez@amd.com 15311639Salexandru.dutu@amd.com uint32_t oldBarrierCnt; 15411639Salexandru.dutu@amd.com uint32_t barrierCnt; 15511639Salexandru.dutu@amd.com uint32_t barrierId; 15611639Salexandru.dutu@amd.com uint32_t barrierSlots; 15711308Santhony.gutierrez@amd.com status_e status; 15811308Santhony.gutierrez@amd.com // HW slot id where the WF is mapped to inside a SIMD unit 15911308Santhony.gutierrez@amd.com int wfSlotId; 16011639Salexandru.dutu@amd.com int kernId; 16111308Santhony.gutierrez@amd.com // SIMD unit where the WV has been scheduled 16211308Santhony.gutierrez@amd.com int simdId; 16311308Santhony.gutierrez@amd.com // pointer to parent CU 16411308Santhony.gutierrez@amd.com ComputeUnit *computeUnit; 16511308Santhony.gutierrez@amd.com 16611308Santhony.gutierrez@amd.com std::deque<GPUDynInstPtr> instructionBuffer; 16711308Santhony.gutierrez@amd.com 16811308Santhony.gutierrez@amd.com bool pendingFetch; 16911308Santhony.gutierrez@amd.com bool dropFetch; 17011308Santhony.gutierrez@amd.com 17111308Santhony.gutierrez@amd.com // Condition Register State (for HSAIL simulations only) 17211308Santhony.gutierrez@amd.com class ConditionRegisterState *condRegState; 17311308Santhony.gutierrez@amd.com // number of single precision VGPRs required by WF 17411308Santhony.gutierrez@amd.com uint32_t maxSpVgprs; 17511308Santhony.gutierrez@amd.com // number of double precision VGPRs required by WF 17611308Santhony.gutierrez@amd.com uint32_t maxDpVgprs; 17711308Santhony.gutierrez@amd.com // map virtual to physical vector register 17811308Santhony.gutierrez@amd.com uint32_t remap(uint32_t vgprIndex, uint32_t size, uint8_t mode=0); 17911308Santhony.gutierrez@amd.com void resizeRegFiles(int num_cregs, int num_sregs, int num_dregs); 18011308Santhony.gutierrez@amd.com bool isGmInstruction(GPUDynInstPtr ii); 18111308Santhony.gutierrez@amd.com bool isLmInstruction(GPUDynInstPtr ii); 18211308Santhony.gutierrez@amd.com bool isOldestInstGMem(); 18311308Santhony.gutierrez@amd.com bool isOldestInstLMem(); 18411308Santhony.gutierrez@amd.com bool isOldestInstPrivMem(); 18511308Santhony.gutierrez@amd.com bool isOldestInstFlatMem(); 18611308Santhony.gutierrez@amd.com bool isOldestInstALU(); 18711308Santhony.gutierrez@amd.com bool isOldestInstBarrier(); 18811308Santhony.gutierrez@amd.com // used for passing spill address to DDInstGPU 18911639Salexandru.dutu@amd.com std::vector<Addr> lastAddr; 19011639Salexandru.dutu@amd.com std::vector<uint32_t> workItemId[3]; 19111639Salexandru.dutu@amd.com std::vector<uint32_t> workItemFlatId; 19211639Salexandru.dutu@amd.com uint32_t workGroupId[3]; 19311639Salexandru.dutu@amd.com uint32_t workGroupSz[3]; 19411639Salexandru.dutu@amd.com uint32_t gridSz[3]; 19511639Salexandru.dutu@amd.com uint32_t wgId; 19611639Salexandru.dutu@amd.com uint32_t wgSz; 19711639Salexandru.dutu@amd.com uint32_t dynWaveId; 19811639Salexandru.dutu@amd.com uint32_t maxDynWaveId; 19911639Salexandru.dutu@amd.com uint32_t dispatchId; 20011308Santhony.gutierrez@amd.com // outstanding global+local memory requests 20111639Salexandru.dutu@amd.com uint32_t outstandingReqs; 20211308Santhony.gutierrez@amd.com // memory requests between scoreboard 20311308Santhony.gutierrez@amd.com // and execute stage not yet executed 20411639Salexandru.dutu@amd.com uint32_t memReqsInPipe; 20511308Santhony.gutierrez@amd.com // outstanding global memory write requests 20611639Salexandru.dutu@amd.com uint32_t outstandingReqsWrGm; 20711308Santhony.gutierrez@amd.com // outstanding local memory write requests 20811639Salexandru.dutu@amd.com uint32_t outstandingReqsWrLm; 20911308Santhony.gutierrez@amd.com // outstanding global memory read requests 21011639Salexandru.dutu@amd.com uint32_t outstandingReqsRdGm; 21111308Santhony.gutierrez@amd.com // outstanding local memory read requests 21211639Salexandru.dutu@amd.com uint32_t outstandingReqsRdLm; 21311639Salexandru.dutu@amd.com uint32_t rdLmReqsInPipe; 21411639Salexandru.dutu@amd.com uint32_t rdGmReqsInPipe; 21511639Salexandru.dutu@amd.com uint32_t wrLmReqsInPipe; 21611639Salexandru.dutu@amd.com uint32_t wrGmReqsInPipe; 21711308Santhony.gutierrez@amd.com 21811639Salexandru.dutu@amd.com int memTraceBusy; 21911639Salexandru.dutu@amd.com uint64_t lastTrace; 22011308Santhony.gutierrez@amd.com // number of vector registers reserved by WF 22111308Santhony.gutierrez@amd.com int reservedVectorRegs; 22211308Santhony.gutierrez@amd.com // Index into the Vector Register File's namespace where the WF's registers 22311308Santhony.gutierrez@amd.com // will live while the WF is executed 22411308Santhony.gutierrez@amd.com uint32_t startVgprIndex; 22511308Santhony.gutierrez@amd.com 22611308Santhony.gutierrez@amd.com // Old value of destination gpr (for trace) 22711639Salexandru.dutu@amd.com std::vector<uint32_t> oldVgpr; 22811308Santhony.gutierrez@amd.com // Id of destination gpr (for trace) 22911639Salexandru.dutu@amd.com uint32_t oldVgprId; 23011308Santhony.gutierrez@amd.com // Tick count of last old_vgpr copy 23111639Salexandru.dutu@amd.com uint64_t oldVgprTcnt; 23211308Santhony.gutierrez@amd.com 23311308Santhony.gutierrez@amd.com // Old value of destination gpr (for trace) 23411639Salexandru.dutu@amd.com std::vector<uint64_t> oldDgpr; 23511308Santhony.gutierrez@amd.com // Id of destination gpr (for trace) 23611639Salexandru.dutu@amd.com uint32_t oldDgprId; 23711308Santhony.gutierrez@amd.com // Tick count of last old_vgpr copy 23811639Salexandru.dutu@amd.com uint64_t oldDgprTcnt; 23911308Santhony.gutierrez@amd.com 24011308Santhony.gutierrez@amd.com // Execution mask at wavefront start 24111639Salexandru.dutu@amd.com VectorMask initMask; 24211308Santhony.gutierrez@amd.com 24311308Santhony.gutierrez@amd.com // number of barriers this WF has joined 24411639Salexandru.dutu@amd.com std::vector<int> barCnt; 24511639Salexandru.dutu@amd.com int maxBarCnt; 24611308Santhony.gutierrez@amd.com // Flag to stall a wave on barrier 24711308Santhony.gutierrez@amd.com bool stalledAtBarrier; 24811308Santhony.gutierrez@amd.com 24911308Santhony.gutierrez@amd.com // a pointer to the fraction of the LDS allocated 25011308Santhony.gutierrez@amd.com // to this workgroup (thus this wavefront) 25111308Santhony.gutierrez@amd.com LdsChunk *ldsChunk; 25211308Santhony.gutierrez@amd.com 25311308Santhony.gutierrez@amd.com // A pointer to the spill area 25411308Santhony.gutierrez@amd.com Addr spillBase; 25511308Santhony.gutierrez@amd.com // The size of the spill area 25611308Santhony.gutierrez@amd.com uint32_t spillSizePerItem; 25711308Santhony.gutierrez@amd.com // The vector width of the spill area 25811308Santhony.gutierrez@amd.com uint32_t spillWidth; 25911308Santhony.gutierrez@amd.com 26011308Santhony.gutierrez@amd.com // A pointer to the private memory area 26111308Santhony.gutierrez@amd.com Addr privBase; 26211308Santhony.gutierrez@amd.com // The size of the private memory area 26311308Santhony.gutierrez@amd.com uint32_t privSizePerItem; 26411308Santhony.gutierrez@amd.com 26511308Santhony.gutierrez@amd.com // A pointer ot the read-only memory area 26611308Santhony.gutierrez@amd.com Addr roBase; 26711308Santhony.gutierrez@amd.com // size of the read-only memory area 26811308Santhony.gutierrez@amd.com uint32_t roSize; 26911308Santhony.gutierrez@amd.com 27011308Santhony.gutierrez@amd.com // pointer to buffer for storing kernel arguments 27111308Santhony.gutierrez@amd.com uint8_t *kernelArgs; 27211308Santhony.gutierrez@amd.com // unique WF id over all WFs executed across all CUs 27311308Santhony.gutierrez@amd.com uint64_t wfDynId; 27411308Santhony.gutierrez@amd.com 27511308Santhony.gutierrez@amd.com // number of times instruction issue for this wavefront is blocked 27611308Santhony.gutierrez@amd.com // due to VRF port availability 27711308Santhony.gutierrez@amd.com Stats::Scalar numTimesBlockedDueVrfPortAvail; 27811308Santhony.gutierrez@amd.com // number of times an instruction of a WF is blocked from being issued 27911308Santhony.gutierrez@amd.com // due to WAR and WAW dependencies 28011308Santhony.gutierrez@amd.com Stats::Scalar numTimesBlockedDueWAXDependencies; 28111308Santhony.gutierrez@amd.com // number of times an instruction of a WF is blocked from being issued 28211308Santhony.gutierrez@amd.com // due to WAR and WAW dependencies 28311308Santhony.gutierrez@amd.com Stats::Scalar numTimesBlockedDueRAWDependencies; 28411308Santhony.gutierrez@amd.com // distribution of executed instructions based on their register 28511308Santhony.gutierrez@amd.com // operands; this is used to highlight the load on the VRF 28611308Santhony.gutierrez@amd.com Stats::Distribution srcRegOpDist; 28711308Santhony.gutierrez@amd.com Stats::Distribution dstRegOpDist; 28811308Santhony.gutierrez@amd.com 28911308Santhony.gutierrez@amd.com // Functions to operate on call argument memory 29011308Santhony.gutierrez@amd.com // argument memory for hsail call instruction 29111308Santhony.gutierrez@amd.com CallArgMem *callArgMem; 29211308Santhony.gutierrez@amd.com void 29311534Sjohn.kalamatianos@amd.com initCallArgMem(int func_args_size_per_item, int wf_size) 29411308Santhony.gutierrez@amd.com { 29511534Sjohn.kalamatianos@amd.com callArgMem = new CallArgMem(func_args_size_per_item, wf_size); 29611308Santhony.gutierrez@amd.com } 29711308Santhony.gutierrez@amd.com 29811308Santhony.gutierrez@amd.com template<typename CType> 29911308Santhony.gutierrez@amd.com CType 30011308Santhony.gutierrez@amd.com readCallArgMem(int lane, int addr) 30111308Santhony.gutierrez@amd.com { 30211308Santhony.gutierrez@amd.com return *((CType*)(callArgMem->getLaneAddr<CType>(lane, addr))); 30311308Santhony.gutierrez@amd.com } 30411308Santhony.gutierrez@amd.com 30511308Santhony.gutierrez@amd.com template<typename CType> 30611308Santhony.gutierrez@amd.com void 30711308Santhony.gutierrez@amd.com writeCallArgMem(int lane, int addr, CType val) 30811308Santhony.gutierrez@amd.com { 30911308Santhony.gutierrez@amd.com callArgMem->setLaneAddr<CType>(lane, addr, val); 31011308Santhony.gutierrez@amd.com } 31111308Santhony.gutierrez@amd.com 31211308Santhony.gutierrez@amd.com typedef WavefrontParams Params; 31311308Santhony.gutierrez@amd.com Wavefront(const Params *p); 31411308Santhony.gutierrez@amd.com ~Wavefront(); 31511308Santhony.gutierrez@amd.com virtual void init(); 31611308Santhony.gutierrez@amd.com 31711308Santhony.gutierrez@amd.com void 31811308Santhony.gutierrez@amd.com setParent(ComputeUnit *cu) 31911308Santhony.gutierrez@amd.com { 32011308Santhony.gutierrez@amd.com computeUnit = cu; 32111308Santhony.gutierrez@amd.com } 32211308Santhony.gutierrez@amd.com 32311308Santhony.gutierrez@amd.com void start(uint64_t _wfDynId, uint64_t _base_ptr); 32411308Santhony.gutierrez@amd.com void exec(); 32511308Santhony.gutierrez@amd.com void updateResources(); 32611308Santhony.gutierrez@amd.com int ready(itype_e type); 32711308Santhony.gutierrez@amd.com bool instructionBufferHasBranch(); 32811308Santhony.gutierrez@amd.com void regStats(); 32911639Salexandru.dutu@amd.com VectorMask getPred() { return execMask() & initMask; } 33011308Santhony.gutierrez@amd.com 33111308Santhony.gutierrez@amd.com bool waitingAtBarrier(int lane); 33211308Santhony.gutierrez@amd.com 33311308Santhony.gutierrez@amd.com void pushToReconvergenceStack(uint32_t pc, uint32_t rpc, 33411308Santhony.gutierrez@amd.com const VectorMask& exec_mask); 33511308Santhony.gutierrez@amd.com 33611308Santhony.gutierrez@amd.com void popFromReconvergenceStack(); 33711308Santhony.gutierrez@amd.com 33811308Santhony.gutierrez@amd.com uint32_t pc() const; 33911308Santhony.gutierrez@amd.com 34011308Santhony.gutierrez@amd.com uint32_t rpc() const; 34111308Santhony.gutierrez@amd.com 34211308Santhony.gutierrez@amd.com VectorMask execMask() const; 34311308Santhony.gutierrez@amd.com 34411308Santhony.gutierrez@amd.com bool execMask(int lane) const; 34511308Santhony.gutierrez@amd.com 34611308Santhony.gutierrez@amd.com void pc(uint32_t new_pc); 34711308Santhony.gutierrez@amd.com 34811308Santhony.gutierrez@amd.com void discardFetch(); 34911308Santhony.gutierrez@amd.com 35011640Salexandru.dutu@amd.com /** 35111640Salexandru.dutu@amd.com * Returns the size of the static hardware context of a particular wavefront 35211640Salexandru.dutu@amd.com * This should be updated everytime the context is changed 35311640Salexandru.dutu@amd.com */ 35411640Salexandru.dutu@amd.com uint32_t getStaticContextSize() const; 35511640Salexandru.dutu@amd.com 35611308Santhony.gutierrez@amd.com private: 35711308Santhony.gutierrez@amd.com /** 35811308Santhony.gutierrez@amd.com * Stack containing Control Flow Graph nodes (i.e., kernel instructions) 35911308Santhony.gutierrez@amd.com * to be visited by the wavefront, and the associated execution masks. The 36011308Santhony.gutierrez@amd.com * reconvergence stack grows every time the wavefront reaches a divergence 36111308Santhony.gutierrez@amd.com * point (branch instruction), and shrinks every time the wavefront 36211308Santhony.gutierrez@amd.com * reaches a reconvergence point (immediate post-dominator instruction). 36311308Santhony.gutierrez@amd.com */ 36411641Salexandru.dutu@amd.com std::deque<std::unique_ptr<ReconvergenceStackEntry>> reconvergenceStack; 36511308Santhony.gutierrez@amd.com}; 36611308Santhony.gutierrez@amd.com 36711308Santhony.gutierrez@amd.com#endif // __WAVEFRONT_HH__ 368