vector_register_file.hh revision 11800
1/* 2 * Copyright (c) 2015 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * For use for simulation and test purposes only 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * 3. Neither the name of the copyright holder nor the names of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Author: John Kalamatianos 34 */ 35 36#ifndef __VECTOR_REGISTER_FILE_HH__ 37#define __VECTOR_REGISTER_FILE_HH__ 38 39#include <list> 40 41#include "base/statistics.hh" 42#include "base/trace.hh" 43#include "base/types.hh" 44#include "debug/GPUVRF.hh" 45#include "gpu-compute/vector_register_state.hh" 46#include "sim/sim_object.hh" 47 48class ComputeUnit; 49class Shader; 50class SimplePoolManager; 51class Wavefront; 52 53struct VectorRegisterFileParams; 54 55enum class VrfAccessType : uint8_t 56{ 57 READ = 0x01, 58 WRITE = 0x02, 59 RD_WR = READ | WRITE 60}; 61 62// Vector Register File 63class VectorRegisterFile : public SimObject 64{ 65 public: 66 VectorRegisterFile(const VectorRegisterFileParams *p); 67 68 void setParent(ComputeUnit *_computeUnit); 69 70 // Read a register 71 template<typename T> 72 T 73 read(int regIdx, int threadId=0) 74 { 75 T p0 = vgprState->read<T>(regIdx, threadId); 76 DPRINTF(GPUVRF, "reading vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)p0); 77 78 return p0; 79 } 80 81 // Write a register 82 template<typename T> 83 void 84 write(int regIdx, T value, int threadId=0) 85 { 86 DPRINTF(GPUVRF, "writing vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)value); 87 vgprState->write<T>(regIdx, value, threadId); 88 } 89 90 uint8_t regBusy(int idx, uint32_t operandSize) const; 91 uint8_t regNxtBusy(int idx, uint32_t operandSize) const; 92 93 int numRegs() const { return numRegsPerSimd; } 94 95 void markReg(int regIdx, uint32_t operandSize, uint8_t value); 96 void preMarkReg(int regIdx, uint32_t operandSize, uint8_t value); 97 98 virtual void exec(GPUDynInstPtr ii, Wavefront *w); 99 100 virtual int exec(uint64_t dynamic_id, Wavefront *w, 101 std::vector<uint32_t> ®Vec, uint32_t operandSize, 102 uint64_t timestamp); 103 104 bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const; 105 virtual void updateEvents() { } 106 virtual void updateResources(Wavefront *w, GPUDynInstPtr ii); 107 108 virtual bool 109 isReadConflict(int memWfId, int exeWfId) const 110 { 111 return false; 112 } 113 114 virtual bool 115 isWriteConflict(int memWfId, int exeWfId) const 116 { 117 return false; 118 } 119 120 virtual bool vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w, 121 GPUDynInstPtr ii, 122 VrfAccessType accessType); 123 124 virtual bool vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii, 125 VrfAccessType accessType); 126 127 SimplePoolManager *manager; 128 129 protected: 130 ComputeUnit* computeUnit; 131 int simdId; 132 133 // flag indicating if a register is busy 134 std::vector<uint8_t> busy; 135 // flag indicating if a register will be busy (by instructions 136 // in the SIMD pipeline) 137 std::vector<uint8_t> nxtBusy; 138 139 // numer of registers (bank size) per simd unit (bank) 140 int numRegsPerSimd; 141 142 // vector register state 143 VecRegisterState *vgprState; 144}; 145 146#endif // __VECTOR_REGISTER_FILE_HH__ 147