vector_register_file.hh revision 11642:46cffde5d8a6 
1/*
2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Author: John Kalamatianos
34 */
35
36#ifndef __VECTOR_REGISTER_FILE_HH__
37#define __VECTOR_REGISTER_FILE_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "base/types.hh"
43#include "debug/GPUVRF.hh"
44#include "gpu-compute/vector_register_state.hh"
45#include "sim/sim_object.hh"
46
47class ComputeUnit;
48class Shader;
49class SimplePoolManager;
50class Wavefront;
51
52struct VectorRegisterFileParams;
53
54enum class VrfAccessType : uint8_t
55{
56    READ = 0x01,
57    WRITE = 0x02,
58    RD_WR = READ | WRITE
59};
60
61// Vector Register File
62class VectorRegisterFile : public SimObject
63{
64  public:
65    VectorRegisterFile(const VectorRegisterFileParams *p);
66
67    void setParent(ComputeUnit *_computeUnit);
68
69    // Read a register
70    template<typename T>
71    T
72    read(int regIdx, int threadId=0)
73    {
74        T p0 = vgprState->read<T>(regIdx, threadId);
75        DPRINTF(GPUVRF, "reading vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)p0);
76
77        return p0;
78    }
79
80    // Write a register
81    template<typename T>
82    void
83    write(int regIdx, T value, int threadId=0)
84    {
85        DPRINTF(GPUVRF, "writing vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)value);
86        vgprState->write<T>(regIdx, value, threadId);
87    }
88
89    uint8_t regBusy(int idx, uint32_t operandSize) const;
90    uint8_t regNxtBusy(int idx, uint32_t operandSize) const;
91
92    int numRegs() const { return numRegsPerSimd; }
93
94    void markReg(int regIdx, uint32_t operandSize, uint8_t value);
95    void preMarkReg(int regIdx, uint32_t operandSize, uint8_t value);
96
97    virtual void exec(GPUDynInstPtr ii, Wavefront *w);
98
99    virtual int exec(uint64_t dynamic_id, Wavefront *w,
100                     std::vector<uint32_t> &regVec, uint32_t operandSize,
101                     uint64_t timestamp);
102
103    bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const;
104    virtual void updateEvents() { }
105    virtual void updateResources(Wavefront *w, GPUDynInstPtr ii);
106
107    virtual bool
108    isReadConflict(int memWfId, int exeWfId) const
109    {
110        return false;
111    }
112
113    virtual bool
114    isWriteConflict(int memWfId, int exeWfId) const
115    {
116        return false;
117    }
118
119    virtual bool vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w,
120                                       GPUDynInstPtr ii,
121                                       VrfAccessType accessType);
122
123    virtual bool vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii,
124                                       VrfAccessType accessType);
125
126    SimplePoolManager *manager;
127
128  protected:
129    ComputeUnit* computeUnit;
130    int simdId;
131
132    // flag indicating if a register is busy
133    std::vector<uint8_t> busy;
134    // flag indicating if a register will be busy (by instructions
135    // in the SIMD pipeline)
136    std::vector<uint8_t> nxtBusy;
137
138    // numer of registers (bank size) per simd unit (bank)
139    int numRegsPerSimd;
140
141    // vector register state
142    VecRegisterState *vgprState;
143};
144
145#endif // __VECTOR_REGISTER_FILE_HH__
146