vector_register_file.hh revision 11642
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. 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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3311308Santhony.gutierrez@amd.com * Author: John Kalamatianos 3411308Santhony.gutierrez@amd.com */ 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.com#ifndef __VECTOR_REGISTER_FILE_HH__ 3711308Santhony.gutierrez@amd.com#define __VECTOR_REGISTER_FILE_HH__ 3811308Santhony.gutierrez@amd.com 3911308Santhony.gutierrez@amd.com#include <list> 4011308Santhony.gutierrez@amd.com 4111308Santhony.gutierrez@amd.com#include "base/statistics.hh" 4211308Santhony.gutierrez@amd.com#include "base/types.hh" 4311642Salexandru.dutu@amd.com#include "debug/GPUVRF.hh" 4411308Santhony.gutierrez@amd.com#include "gpu-compute/vector_register_state.hh" 4511308Santhony.gutierrez@amd.com#include "sim/sim_object.hh" 4611308Santhony.gutierrez@amd.com 4711308Santhony.gutierrez@amd.comclass ComputeUnit; 4811308Santhony.gutierrez@amd.comclass Shader; 4911308Santhony.gutierrez@amd.comclass SimplePoolManager; 5011308Santhony.gutierrez@amd.comclass Wavefront; 5111308Santhony.gutierrez@amd.com 5211308Santhony.gutierrez@amd.comstruct VectorRegisterFileParams; 5311308Santhony.gutierrez@amd.com 5411308Santhony.gutierrez@amd.comenum class VrfAccessType : uint8_t 5511308Santhony.gutierrez@amd.com{ 5611308Santhony.gutierrez@amd.com READ = 0x01, 5711308Santhony.gutierrez@amd.com WRITE = 0x02, 5811308Santhony.gutierrez@amd.com RD_WR = READ | WRITE 5911308Santhony.gutierrez@amd.com}; 6011308Santhony.gutierrez@amd.com 6111308Santhony.gutierrez@amd.com// Vector Register File 6211308Santhony.gutierrez@amd.comclass VectorRegisterFile : public SimObject 6311308Santhony.gutierrez@amd.com{ 6411308Santhony.gutierrez@amd.com public: 6511308Santhony.gutierrez@amd.com VectorRegisterFile(const VectorRegisterFileParams *p); 6611308Santhony.gutierrez@amd.com 6711308Santhony.gutierrez@amd.com void setParent(ComputeUnit *_computeUnit); 6811308Santhony.gutierrez@amd.com 6911308Santhony.gutierrez@amd.com // Read a register 7011308Santhony.gutierrez@amd.com template<typename T> 7111308Santhony.gutierrez@amd.com T 7211308Santhony.gutierrez@amd.com read(int regIdx, int threadId=0) 7311308Santhony.gutierrez@amd.com { 7411308Santhony.gutierrez@amd.com T p0 = vgprState->read<T>(regIdx, threadId); 7511642Salexandru.dutu@amd.com DPRINTF(GPUVRF, "reading vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)p0); 7611308Santhony.gutierrez@amd.com 7711308Santhony.gutierrez@amd.com return p0; 7811308Santhony.gutierrez@amd.com } 7911308Santhony.gutierrez@amd.com 8011308Santhony.gutierrez@amd.com // Write a register 8111308Santhony.gutierrez@amd.com template<typename T> 8211308Santhony.gutierrez@amd.com void 8311308Santhony.gutierrez@amd.com write(int regIdx, T value, int threadId=0) 8411308Santhony.gutierrez@amd.com { 8511642Salexandru.dutu@amd.com DPRINTF(GPUVRF, "writing vreg[%d][%d] = %u\n", regIdx, threadId, (uint64_t)value); 8611308Santhony.gutierrez@amd.com vgprState->write<T>(regIdx, value, threadId); 8711308Santhony.gutierrez@amd.com } 8811308Santhony.gutierrez@amd.com 8911308Santhony.gutierrez@amd.com uint8_t regBusy(int idx, uint32_t operandSize) const; 9011308Santhony.gutierrez@amd.com uint8_t regNxtBusy(int idx, uint32_t operandSize) const; 9111308Santhony.gutierrez@amd.com 9211308Santhony.gutierrez@amd.com int numRegs() const { return numRegsPerSimd; } 9311308Santhony.gutierrez@amd.com 9411308Santhony.gutierrez@amd.com void markReg(int regIdx, uint32_t operandSize, uint8_t value); 9511308Santhony.gutierrez@amd.com void preMarkReg(int regIdx, uint32_t operandSize, uint8_t value); 9611308Santhony.gutierrez@amd.com 9711308Santhony.gutierrez@amd.com virtual void exec(GPUDynInstPtr ii, Wavefront *w); 9811308Santhony.gutierrez@amd.com 9911308Santhony.gutierrez@amd.com virtual int exec(uint64_t dynamic_id, Wavefront *w, 10011308Santhony.gutierrez@amd.com std::vector<uint32_t> ®Vec, uint32_t operandSize, 10111308Santhony.gutierrez@amd.com uint64_t timestamp); 10211308Santhony.gutierrez@amd.com 10311308Santhony.gutierrez@amd.com bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const; 10411308Santhony.gutierrez@amd.com virtual void updateEvents() { } 10511308Santhony.gutierrez@amd.com virtual void updateResources(Wavefront *w, GPUDynInstPtr ii); 10611308Santhony.gutierrez@amd.com 10711308Santhony.gutierrez@amd.com virtual bool 10811308Santhony.gutierrez@amd.com isReadConflict(int memWfId, int exeWfId) const 10911308Santhony.gutierrez@amd.com { 11011308Santhony.gutierrez@amd.com return false; 11111308Santhony.gutierrez@amd.com } 11211308Santhony.gutierrez@amd.com 11311308Santhony.gutierrez@amd.com virtual bool 11411308Santhony.gutierrez@amd.com isWriteConflict(int memWfId, int exeWfId) const 11511308Santhony.gutierrez@amd.com { 11611308Santhony.gutierrez@amd.com return false; 11711308Santhony.gutierrez@amd.com } 11811308Santhony.gutierrez@amd.com 11911308Santhony.gutierrez@amd.com virtual bool vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w, 12011308Santhony.gutierrez@amd.com GPUDynInstPtr ii, 12111308Santhony.gutierrez@amd.com VrfAccessType accessType); 12211308Santhony.gutierrez@amd.com 12311308Santhony.gutierrez@amd.com virtual bool vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii, 12411308Santhony.gutierrez@amd.com VrfAccessType accessType); 12511308Santhony.gutierrez@amd.com 12611308Santhony.gutierrez@amd.com SimplePoolManager *manager; 12711308Santhony.gutierrez@amd.com 12811308Santhony.gutierrez@amd.com protected: 12911308Santhony.gutierrez@amd.com ComputeUnit* computeUnit; 13011308Santhony.gutierrez@amd.com int simdId; 13111308Santhony.gutierrez@amd.com 13211308Santhony.gutierrez@amd.com // flag indicating if a register is busy 13311308Santhony.gutierrez@amd.com std::vector<uint8_t> busy; 13411308Santhony.gutierrez@amd.com // flag indicating if a register will be busy (by instructions 13511308Santhony.gutierrez@amd.com // in the SIMD pipeline) 13611308Santhony.gutierrez@amd.com std::vector<uint8_t> nxtBusy; 13711308Santhony.gutierrez@amd.com 13811308Santhony.gutierrez@amd.com // numer of registers (bank size) per simd unit (bank) 13911308Santhony.gutierrez@amd.com int numRegsPerSimd; 14011308Santhony.gutierrez@amd.com 14111308Santhony.gutierrez@amd.com // vector register state 14211308Santhony.gutierrez@amd.com VecRegisterState *vgprState; 14311308Santhony.gutierrez@amd.com}; 14411308Santhony.gutierrez@amd.com 14511308Santhony.gutierrez@amd.com#endif // __VECTOR_REGISTER_FILE_HH__ 146