vector_register_file.hh revision 11308
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2513771Sgabeblack@google.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2613771Sgabeblack@google.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2713771Sgabeblack@google.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2813771Sgabeblack@google.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2913771Sgabeblack@google.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3013771Sgabeblack@google.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3113771Sgabeblack@google.com * POSSIBILITY OF SUCH DAMAGE. 3213771Sgabeblack@google.com * 3313771Sgabeblack@google.com * Author: John Kalamatianos 3413771Sgabeblack@google.com */ 3513771Sgabeblack@google.com 3613771Sgabeblack@google.com#ifndef __VECTOR_REGISTER_FILE_HH__ 3713771Sgabeblack@google.com#define __VECTOR_REGISTER_FILE_HH__ 3813771Sgabeblack@google.com 3913771Sgabeblack@google.com#include <list> 4013771Sgabeblack@google.com 4113771Sgabeblack@google.com#include "base/statistics.hh" 4213771Sgabeblack@google.com#include "base/types.hh" 4313771Sgabeblack@google.com#include "gpu-compute/vector_register_state.hh" 4413771Sgabeblack@google.com#include "sim/sim_object.hh" 4513771Sgabeblack@google.com 4613771Sgabeblack@google.comclass ComputeUnit; 4713771Sgabeblack@google.comclass Shader; 4813771Sgabeblack@google.comclass SimplePoolManager; 4913771Sgabeblack@google.comclass Wavefront; 5013771Sgabeblack@google.com 5113771Sgabeblack@google.comstruct VectorRegisterFileParams; 5213782Sgabeblack@google.com 5313782Sgabeblack@google.comenum class VrfAccessType : uint8_t 5413782Sgabeblack@google.com{ 5513771Sgabeblack@google.com READ = 0x01, 56 WRITE = 0x02, 57 RD_WR = READ | WRITE 58}; 59 60// Vector Register File 61class VectorRegisterFile : public SimObject 62{ 63 public: 64 VectorRegisterFile(const VectorRegisterFileParams *p); 65 66 void setParent(ComputeUnit *_computeUnit); 67 68 // Read a register 69 template<typename T> 70 T 71 read(int regIdx, int threadId=0) 72 { 73 T p0 = vgprState->read<T>(regIdx, threadId); 74 75 return p0; 76 } 77 78 // Write a register 79 template<typename T> 80 void 81 write(int regIdx, T value, int threadId=0) 82 { 83 vgprState->write<T>(regIdx, value, threadId); 84 } 85 86 uint8_t regBusy(int idx, uint32_t operandSize) const; 87 uint8_t regNxtBusy(int idx, uint32_t operandSize) const; 88 89 int numRegs() const { return numRegsPerSimd; } 90 91 void markReg(int regIdx, uint32_t operandSize, uint8_t value); 92 void preMarkReg(int regIdx, uint32_t operandSize, uint8_t value); 93 94 virtual void exec(GPUDynInstPtr ii, Wavefront *w); 95 96 virtual int exec(uint64_t dynamic_id, Wavefront *w, 97 std::vector<uint32_t> ®Vec, uint32_t operandSize, 98 uint64_t timestamp); 99 100 bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const; 101 virtual void updateEvents() { } 102 virtual void updateResources(Wavefront *w, GPUDynInstPtr ii); 103 104 virtual bool 105 isReadConflict(int memWfId, int exeWfId) const 106 { 107 return false; 108 } 109 110 virtual bool 111 isWriteConflict(int memWfId, int exeWfId) const 112 { 113 return false; 114 } 115 116 virtual bool vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w, 117 GPUDynInstPtr ii, 118 VrfAccessType accessType); 119 120 virtual bool vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii, 121 VrfAccessType accessType); 122 123 SimplePoolManager *manager; 124 125 protected: 126 ComputeUnit* computeUnit; 127 int simdId; 128 129 // flag indicating if a register is busy 130 std::vector<uint8_t> busy; 131 // flag indicating if a register will be busy (by instructions 132 // in the SIMD pipeline) 133 std::vector<uint8_t> nxtBusy; 134 135 // numer of registers (bank size) per simd unit (bank) 136 int numRegsPerSimd; 137 138 // vector register state 139 VecRegisterState *vgprState; 140}; 141 142#endif // __VECTOR_REGISTER_FILE_HH__ 143