exec_stage.hh revision 11308:7d8836fd043d
14269SN/A/* 24269SN/A * Copyright (c) 2014-2015 Advanced Micro Devices, Inc. 34269SN/A * All rights reserved. 44269SN/A * 54269SN/A * For use for simulation and test purposes only 64269SN/A * 74269SN/A * Redistribution and use in source and binary forms, with or without 84269SN/A * modification, are permitted provided that the following conditions are met: 94269SN/A * 104269SN/A * 1. Redistributions of source code must retain the above copyright notice, 114269SN/A * this list of conditions and the following disclaimer. 124269SN/A * 134269SN/A * 2. Redistributions in binary form must reproduce the above copyright notice, 144269SN/A * this list of conditions and the following disclaimer in the documentation 154269SN/A * and/or other materials provided with the distribution. 164269SN/A * 174269SN/A * 3. Neither the name of the copyright holder nor the names of its contributors 184269SN/A * may be used to endorse or promote products derived from this software 194269SN/A * without specific prior written permission. 204269SN/A * 214269SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 224269SN/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 234269SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 244269SN/A * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 254269SN/A * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 264269SN/A * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 274269SN/A * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 284269SN/A * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 294269SN/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 304269SN/A * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 314269SN/A * POSSIBILITY OF SUCH DAMAGE. 324269SN/A * 334269SN/A * Author: John Kalamatianos, Sooraj Puthoor 344269SN/A */ 354269SN/A 364269SN/A#ifndef __EXEC_STAGE_HH__ 374269SN/A#define __EXEC_STAGE_HH__ 384269SN/A 394269SN/A#include <string> 404269SN/A#include <utility> 414269SN/A#include <vector> 424269SN/A 434269SN/A#include "sim/stats.hh" 444269SN/A 454269SN/Aclass ComputeUnit; 464269SN/Aclass Wavefront; 474269SN/Astruct ComputeUnitParams; 484269SN/A 494269SN/Aenum STAT_STATUS 504269SN/A{ 514269SN/A IdleExec, 524269SN/A BusyExec, 534269SN/A PostExec 544269SN/A}; 554269SN/A 564269SN/Aenum DISPATCH_STATUS 574269SN/A{ 584269SN/A EMPTY = 0, 594269SN/A FILLED 604269SN/A}; 614269SN/A 624269SN/A// Execution stage. 634269SN/A// Each execution resource executes the 644269SN/A// wave which is in its dispatch list. 654269SN/A// The schedule stage is responsible for 664269SN/A// adding a wave into each execution resource's 674269SN/A// dispatch list. 684269SN/A 694269SN/Aclass ExecStage 704269SN/A{ 714269SN/A public: 724269SN/A ExecStage(const ComputeUnitParams* params); 734269SN/A ~ExecStage() { } 744269SN/A void init(ComputeUnit *cu); 754269SN/A void exec(); 764269SN/A 774269SN/A std::string name() { return _name; } 784269SN/A void regStats(); 794269SN/A // number of idle cycles 804269SN/A Stats::Scalar numCyclesWithNoIssue; 814269SN/A // number of busy cycles 824269SN/A Stats::Scalar numCyclesWithInstrIssued; 834269SN/A // number of cycles (per execution unit) during which at least one 844269SN/A // instruction was issued to that unit 854269SN/A Stats::Vector numCyclesWithInstrTypeIssued; 864269SN/A // number of idle cycles (per execution unit) during which the unit issued 874269SN/A // no instruction targeting that unit, even though there is at least one 884269SN/A // Wavefront with such an instruction as the oldest 894269SN/A Stats::Vector numCyclesWithNoInstrTypeIssued; 904269SN/A // SIMDs active per cycle 914269SN/A Stats::Distribution spc; 924269SN/A 934269SN/A private: 944269SN/A void collectStatistics(enum STAT_STATUS stage, int unitId); 954269SN/A void initStatistics(); 964269SN/A ComputeUnit *computeUnit; 974269SN/A uint32_t numSIMDs; 984269SN/A 994269SN/A // Number of memory execution resources; 1004269SN/A // both global and local memory execution resources in CU 1014269SN/A uint32_t numMemUnits; 1024269SN/A 1034269SN/A // List of waves which will be dispatched to 1044269SN/A // each execution resource. A FILLED implies 1054269SN/A // dispatch list is non-empty and 1064269SN/A // execution unit has something to execute 1074269SN/A // this cycle. Currently, the dispatch list of 1084269SN/A // an execution resource can hold only one wave because 1094269SN/A // an execution resource can execute only one wave in a cycle. 1104269SN/A // dispatchList is used to communicate between schedule 1114269SN/A // and exec stage 1124269SN/A std::vector<std::pair<Wavefront*, DISPATCH_STATUS>> *dispatchList; 1134269SN/A // flag per vector SIMD unit that is set when there is at least one 1144269SN/A // WV that has a vector ALU instruction as the oldest in its 1154269SN/A // Instruction Buffer 1164269SN/A std::vector<bool> *vectorAluInstAvail; 1174269SN/A int *glbMemInstAvail; 1184269SN/A int *shrMemInstAvail; 1194269SN/A bool lastTimeInstExecuted; 1204269SN/A bool thisTimeInstExecuted; 1214269SN/A bool instrExecuted; 1224269SN/A Stats::Scalar numTransActiveIdle; 1234269SN/A Stats::Distribution idleDur; 1244269SN/A uint32_t executionResourcesUsed; 1254269SN/A uint64_t idle_dur; 1264269SN/A std::string _name; 1274269SN/A}; 1284269SN/A 1294269SN/A#endif // __EXEC_STAGE_HH__ 1304269SN/A