i8259.cc revision 7903:7fcfb515d7bf
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "base/bitfield.hh" 32#include "dev/x86/i82094aa.hh" 33#include "dev/x86/i8259.hh" 34#include "mem/packet.hh" 35#include "mem/packet_access.hh" 36 37X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this), 38 latency(p->pio_latency), output(p->output), 39 mode(p->mode), slave(p->slave), 40 IRR(0), ISR(0), IMR(0), 41 readIRR(true), initControlWord(0), autoEOI(false) 42{ 43 for (int i = 0; i < NumLines; i++) 44 pinStates[i] = false; 45 pioSize = 2; 46} 47 48Tick 49X86ISA::I8259::read(PacketPtr pkt) 50{ 51 assert(pkt->getSize() == 1); 52 switch(pkt->getAddr() - pioAddr) 53 { 54 case 0x0: 55 if (readIRR) { 56 DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 57 pkt->set(IRR); 58 } else { 59 DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 60 pkt->set(ISR); 61 } 62 break; 63 case 0x1: 64 DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 65 pkt->set(IMR); 66 break; 67 } 68 pkt->makeAtomicResponse(); 69 return latency; 70} 71 72Tick 73X86ISA::I8259::write(PacketPtr pkt) 74{ 75 assert(pkt->getSize() == 1); 76 uint8_t val = pkt->get<uint8_t>(); 77 switch (pkt->getAddr() - pioAddr) { 78 case 0x0: 79 if (bits(val, 4)) { 80 DPRINTF(I8259, "Received initialization command word 1.\n"); 81 IMR = 0; 82 edgeTriggered = bits(val, 3); 83 DPRINTF(I8259, "%s triggered mode.\n", 84 edgeTriggered ? "Edge" : "Level"); 85 cascadeMode = !bits(val, 1); 86 DPRINTF(I8259, "%s mode.\n", 87 cascadeMode ? "Cascade" : "Single"); 88 expectICW4 = bits(val, 0); 89 if (!expectICW4) { 90 autoEOI = false; 91 } 92 initControlWord = 1; 93 DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 94 } else if (bits(val, 4, 3) == 0) { 95 DPRINTF(I8259, "Received operation command word 2.\n"); 96 switch (bits(val, 7, 5)) { 97 case 0x0: 98 DPRINTF(I8259, 99 "Subcommand: Rotate in auto-EOI mode (clear).\n"); 100 break; 101 case 0x1: 102 { 103 int line = findMsbSet(ISR); 104 DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 105 line); 106 handleEOI(line); 107 } 108 break; 109 case 0x2: 110 DPRINTF(I8259, "Subcommand: No operation.\n"); 111 break; 112 case 0x3: 113 { 114 int line = bits(val, 2, 0); 115 DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 116 line); 117 handleEOI(line); 118 } 119 break; 120 case 0x4: 121 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 122 break; 123 case 0x5: 124 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 125 break; 126 case 0x6: 127 DPRINTF(I8259, "Subcommand: Set priority command.\n"); 128 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 129 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 130 break; 131 case 0x7: 132 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 133 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 134 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 135 break; 136 } 137 } else if (bits(val, 4, 3) == 1) { 138 DPRINTF(I8259, "Received operation command word 3.\n"); 139 if (bits(val, 7)) { 140 DPRINTF(I8259, "%s special mask mode.\n", 141 bits(val, 6) ? "Set" : "Clear"); 142 } 143 if (bits(val, 1)) { 144 readIRR = bits(val, 0); 145 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 146 } 147 } 148 break; 149 case 0x1: 150 switch (initControlWord) { 151 case 0x0: 152 DPRINTF(I8259, "Received operation command word 1.\n"); 153 DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 154 IMR = val; 155 break; 156 case 0x1: 157 DPRINTF(I8259, "Received initialization command word 2.\n"); 158 vectorOffset = val & ~mask(3); 159 DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 160 vectorOffset, vectorOffset | mask(3)); 161 if (cascadeMode) { 162 initControlWord++; 163 } else { 164 cascadeBits = 0; 165 initControlWord = 0; 166 } 167 break; 168 case 0x2: 169 DPRINTF(I8259, "Received initialization command word 3.\n"); 170 if (mode == Enums::I8259Master) { 171 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 172 bits(val, 0) ? " 0" : "", 173 bits(val, 1) ? " 1" : "", 174 bits(val, 2) ? " 2" : "", 175 bits(val, 3) ? " 3" : "", 176 bits(val, 4) ? " 4" : "", 177 bits(val, 5) ? " 5" : "", 178 bits(val, 6) ? " 6" : "", 179 bits(val, 7) ? " 7" : ""); 180 cascadeBits = val; 181 } else { 182 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 183 cascadeBits = val & mask(3); 184 } 185 if (expectICW4) 186 initControlWord++; 187 else 188 initControlWord = 0; 189 break; 190 case 0x3: 191 DPRINTF(I8259, "Received initialization command word 4.\n"); 192 if (bits(val, 4)) { 193 DPRINTF(I8259, "Special fully nested mode.\n"); 194 } else { 195 DPRINTF(I8259, "Not special fully nested mode.\n"); 196 } 197 if (bits(val, 3) == 0) { 198 DPRINTF(I8259, "Nonbuffered.\n"); 199 } else if (bits(val, 2) == 0) { 200 DPRINTF(I8259, "Buffered.\n"); 201 } else { 202 DPRINTF(I8259, "Unrecognized buffer mode.\n"); 203 } 204 autoEOI = bits(val, 1); 205 DPRINTF(I8259, "%s End Of Interrupt.\n", 206 autoEOI ? "Automatic" : "Normal"); 207 208 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 209 initControlWord = 0; 210 break; 211 } 212 break; 213 } 214 pkt->makeAtomicResponse(); 215 return latency; 216} 217 218void 219X86ISA::I8259::handleEOI(int line) 220{ 221 ISR &= ~(1 << line); 222 // There may be an interrupt that was waiting which can 223 // now be sent. 224 if (IRR) 225 requestInterrupt(findMsbSet(IRR)); 226} 227 228void 229X86ISA::I8259::requestInterrupt(int line) 230{ 231 if (bits(ISR, 7, line) == 0) { 232 if (output) { 233 DPRINTF(I8259, "Propogating interrupt.\n"); 234 output->raise(); 235 //XXX This is a hack. 236 output->lower(); 237 } else { 238 warn("Received interrupt but didn't have " 239 "anyone to tell about it.\n"); 240 } 241 } 242} 243 244void 245X86ISA::I8259::signalInterrupt(int line) 246{ 247 DPRINTF(I8259, "Interrupt requested for line %d.\n", line); 248 if (line >= NumLines) 249 fatal("Line number %d doesn't exist. The max is %d.\n", 250 line, NumLines - 1); 251 if (bits(IMR, line)) { 252 DPRINTF(I8259, "Interrupt %d was masked.\n", line); 253 } else { 254 IRR |= 1 << line; 255 requestInterrupt(line); 256 } 257} 258 259void 260X86ISA::I8259::raiseInterruptPin(int number) 261{ 262 DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number); 263 if (number >= NumLines) 264 fatal("Line number %d doesn't exist. The max is %d.\n", 265 number, NumLines - 1); 266 if (!pinStates[number]) 267 signalInterrupt(number); 268 pinStates[number] = true; 269} 270 271void 272X86ISA::I8259::lowerInterruptPin(int number) 273{ 274 DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number); 275 if (number >= NumLines) 276 fatal("Line number %d doesn't exist. The max is %d.\n", 277 number, NumLines - 1); 278 pinStates[number] = false; 279} 280 281int 282X86ISA::I8259::getVector() 283{ 284 /* 285 * This code only handles one slave. Since that's how the PC platform 286 * always uses the 8259 PIC, there shouldn't be any need for more. If 287 * there -is- a need for more for some reason, "slave" can become a 288 * vector of slaves. 289 */ 290 int line = findMsbSet(IRR); 291 IRR &= ~(1 << line); 292 DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 293 if (autoEOI) { 294 handleEOI(line); 295 } else { 296 ISR |= 1 << line; 297 } 298 if (slave && bits(cascadeBits, line)) { 299 DPRINTF(I8259, "Interrupt was from slave who will " 300 "provide the vector.\n"); 301 return slave->getVector(); 302 } 303 return line | vectorOffset; 304} 305 306void 307X86ISA::I8259::serialize(std::ostream &os) 308{ 309 SERIALIZE_ARRAY(pinStates, NumLines); 310 SERIALIZE_ENUM(mode); 311 SERIALIZE_SCALAR(IRR); 312 SERIALIZE_SCALAR(ISR); 313 SERIALIZE_SCALAR(IMR); 314 SERIALIZE_SCALAR(vectorOffset); 315 SERIALIZE_SCALAR(cascadeMode); 316 SERIALIZE_SCALAR(cascadeBits); 317 SERIALIZE_SCALAR(edgeTriggered); 318 SERIALIZE_SCALAR(readIRR); 319 SERIALIZE_SCALAR(expectICW4); 320 SERIALIZE_SCALAR(initControlWord); 321 SERIALIZE_SCALAR(autoEOI); 322} 323 324void 325X86ISA::I8259::unserialize(Checkpoint *cp, const std::string §ion) 326{ 327 UNSERIALIZE_ARRAY(pinStates, NumLines); 328 UNSERIALIZE_ENUM(mode); 329 UNSERIALIZE_SCALAR(IRR); 330 UNSERIALIZE_SCALAR(ISR); 331 UNSERIALIZE_SCALAR(IMR); 332 UNSERIALIZE_SCALAR(vectorOffset); 333 UNSERIALIZE_SCALAR(cascadeMode); 334 UNSERIALIZE_SCALAR(cascadeBits); 335 UNSERIALIZE_SCALAR(edgeTriggered); 336 UNSERIALIZE_SCALAR(readIRR); 337 UNSERIALIZE_SCALAR(expectICW4); 338 UNSERIALIZE_SCALAR(initControlWord); 339 UNSERIALIZE_SCALAR(autoEOI); 340} 341 342X86ISA::I8259 * 343I8259Params::create() 344{ 345 return new X86ISA::I8259(this); 346} 347