i8259.cc revision 5827:ac2c268bf4f1 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "base/bitfield.hh"
32#include "dev/x86/i82094aa.hh"
33#include "dev/x86/i8259.hh"
34#include "mem/packet.hh"
35#include "mem/packet_access.hh"
36
37X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
38                    latency(p->pio_latency), output(p->output),
39                    mode(p->mode), slave(p->slave),
40                    IRR(0), ISR(0), IMR(0),
41                    readIRR(true), initControlWord(0), autoEOI(false)
42{
43    for (int i = 0; i < NumLines; i++)
44        pinStates[i] = false;
45    pioSize = 2;
46}
47
48Tick
49X86ISA::I8259::read(PacketPtr pkt)
50{
51    assert(pkt->getSize() == 1);
52    switch(pkt->getAddr() - pioAddr)
53    {
54      case 0x0:
55        if (readIRR) {
56            DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
57            pkt->set(IRR);
58        } else {
59            DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
60            pkt->set(ISR);
61        }
62        break;
63      case 0x1:
64        DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
65        pkt->set(IMR);
66        break;
67    }
68    return latency;
69}
70
71Tick
72X86ISA::I8259::write(PacketPtr pkt)
73{
74    assert(pkt->getSize() == 1);
75    uint8_t val = pkt->get<uint8_t>();
76    switch (pkt->getAddr() - pioAddr) {
77      case 0x0:
78        if (bits(val, 4)) {
79            DPRINTF(I8259, "Received initialization command word 1.\n");
80            IMR = 0;
81            edgeTriggered = bits(val, 3);
82            DPRINTF(I8259, "%s triggered mode.\n",
83                    edgeTriggered ? "Edge" : "Level");
84            cascadeMode = !bits(val, 1);
85            DPRINTF(I8259, "%s mode.\n",
86                    cascadeMode ? "Cascade" : "Single");
87            expectICW4 = bits(val, 0);
88            if (!expectICW4) {
89                autoEOI = false;
90            }
91            initControlWord = 1;
92            DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
93        } else if (bits(val, 4, 3) == 0) {
94            DPRINTF(I8259, "Received operation command word 2.\n");
95            switch (bits(val, 7, 5)) {
96              case 0x0:
97                DPRINTF(I8259,
98                        "Subcommand: Rotate in auto-EOI mode (clear).\n");
99                break;
100              case 0x1:
101                {
102                    int line = findMsbSet(ISR);
103                    DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n",
104                            line);
105                    handleEOI(line);
106                }
107                break;
108              case 0x2:
109                DPRINTF(I8259, "Subcommand: No operation.\n");
110                break;
111              case 0x3:
112                {
113                    int line = bits(val, 2, 0);
114                    DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
115                            line);
116                    handleEOI(line);
117                }
118                break;
119              case 0x4:
120                DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
121                break;
122              case 0x5:
123                DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
124                break;
125              case 0x6:
126                DPRINTF(I8259, "Subcommand: Set priority command.\n");
127                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
128                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
129                break;
130              case 0x7:
131                DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
132                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
133                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
134                break;
135            }
136        } else if (bits(val, 4, 3) == 1) {
137            DPRINTF(I8259, "Received operation command word 3.\n");
138            if (bits(val, 7)) {
139                DPRINTF(I8259, "%s special mask mode.\n",
140                        bits(val, 6) ? "Set" : "Clear");
141            }
142            if (bits(val, 1)) {
143                readIRR = bits(val, 0);
144                DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
145            }
146        }
147        break;
148      case 0x1:
149        switch (initControlWord) {
150          case 0x0:
151            DPRINTF(I8259, "Received operation command word 1.\n");
152            DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
153            IMR = val;
154            break;
155          case 0x1:
156            DPRINTF(I8259, "Received initialization command word 2.\n");
157            vectorOffset = val & ~mask(3);
158            DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
159                    vectorOffset, vectorOffset | mask(3));
160            if (cascadeMode) {
161                initControlWord++;
162            } else {
163                cascadeBits = 0;
164                initControlWord = 0;
165            }
166            break;
167          case 0x2:
168            DPRINTF(I8259, "Received initialization command word 3.\n");
169            if (mode == Enums::I8259Master) {
170                DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
171                        bits(val, 0) ? " 0" : "",
172                        bits(val, 1) ? " 1" : "",
173                        bits(val, 2) ? " 2" : "",
174                        bits(val, 3) ? " 3" : "",
175                        bits(val, 4) ? " 4" : "",
176                        bits(val, 5) ? " 5" : "",
177                        bits(val, 6) ? " 6" : "",
178                        bits(val, 7) ? " 7" : "");
179                cascadeBits = val;
180            } else {
181                DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
182                cascadeBits = val & mask(3);
183            }
184            if (expectICW4)
185                initControlWord++;
186            else
187                initControlWord = 0;
188            break;
189          case 0x3:
190            DPRINTF(I8259, "Received initialization command word 4.\n");
191            if (bits(val, 4)) {
192                DPRINTF(I8259, "Special fully nested mode.\n");
193            } else {
194                DPRINTF(I8259, "Not special fully nested mode.\n");
195            }
196            if (bits(val, 3) == 0) {
197                DPRINTF(I8259, "Nonbuffered.\n");
198            } else if (bits(val, 2) == 0) {
199                DPRINTF(I8259, "Buffered.\n");
200            } else {
201                DPRINTF(I8259, "Unrecognized buffer mode.\n");
202            }
203            autoEOI = bits(val, 1);
204            DPRINTF(I8259, "%s End Of Interrupt.\n",
205                    autoEOI ? "Automatic" : "Normal");
206
207            DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
208            initControlWord = 0;
209            break;
210        }
211        break;
212    }
213    return latency;
214}
215
216void
217X86ISA::I8259::handleEOI(int line)
218{
219    ISR &= ~(1 << line);
220    // There may be an interrupt that was waiting which can
221    // now be sent.
222    if (IRR)
223        requestInterrupt(findMsbSet(IRR));
224}
225
226void
227X86ISA::I8259::requestInterrupt(int line)
228{
229    if (bits(ISR, 7, line) == 0) {
230        if (output) {
231            DPRINTF(I8259, "Propogating interrupt.\n");
232            output->raise();
233            //XXX This is a hack.
234            output->lower();
235        } else {
236            warn("Received interrupt but didn't have "
237                    "anyone to tell about it.\n");
238        }
239    }
240}
241
242void
243X86ISA::I8259::signalInterrupt(int line)
244{
245    DPRINTF(I8259, "Interrupt raised on line %d.\n", line);
246    if (line >= NumLines)
247        fatal("Line number %d doesn't exist. The max is %d.\n",
248                line, NumLines - 1);
249    if (bits(IMR, line)) {
250        DPRINTF(I8259, "Interrupt %d was masked.\n", line);
251    } else {
252        IRR |= 1 << line;
253        requestInterrupt(line);
254    }
255}
256
257void
258X86ISA::I8259::raiseInterruptPin(int number)
259{
260    if (number >= NumLines)
261        fatal("Line number %d doesn't exist. The max is %d.\n",
262                number, NumLines - 1);
263    if (!pinStates[number])
264        signalInterrupt(number);
265    pinStates[number] = true;
266}
267
268void
269X86ISA::I8259::lowerInterruptPin(int number)
270{
271    if (number >= NumLines)
272        fatal("Line number %d doesn't exist. The max is %d.\n",
273                number, NumLines - 1);
274    pinStates[number] = false;
275}
276
277int
278X86ISA::I8259::getVector()
279{
280    /*
281     * This code only handles one slave. Since that's how the PC platform
282     * always uses the 8259 PIC, there shouldn't be any need for more. If
283     * there -is- a need for more for some reason, "slave" can become a
284     * vector of slaves.
285     */
286    int line = findMsbSet(IRR);
287    IRR &= ~(1 << line);
288    DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
289    if (autoEOI) {
290        handleEOI(line);
291    } else {
292        ISR |= 1 << line;
293    }
294    if (slave && bits(cascadeBits, line)) {
295        DPRINTF(I8259, "Interrupt was from slave who will "
296                "provide the vector.\n");
297        return slave->getVector();
298    }
299    return line | vectorOffset;
300}
301
302X86ISA::I8259 *
303I8259Params::create()
304{
305    return new X86ISA::I8259(this);
306}
307