i8259.cc revision 5657:7539092b28ac 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "base/bitfield.hh"
32#include "dev/x86/i82094aa.hh"
33#include "dev/x86/i8259.hh"
34
35X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
36                    latency(p->pio_latency), output(p->output),
37                    mode(p->mode), slave(NULL),
38                    IRR(0), ISR(0), IMR(0),
39                    readIRR(true), initControlWord(0)
40{
41    if (output) {
42        I8259 * master;
43        master = dynamic_cast<I8259 *>(output->getDevice());
44        if (master)
45            master->setSlave(this);
46        I82094AA * ioApic;
47        ioApic = dynamic_cast<I82094AA *>(output->getDevice());
48        if (ioApic)
49            ioApic->setExtIntPic(this);
50    }
51    pioSize = 2;
52}
53
54Tick
55X86ISA::I8259::read(PacketPtr pkt)
56{
57    assert(pkt->getSize() == 1);
58    switch(pkt->getAddr() - pioAddr)
59    {
60      case 0x0:
61        if (readIRR) {
62            DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
63            pkt->set(IRR);
64        } else {
65            DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
66            pkt->set(ISR);
67        }
68        break;
69      case 0x1:
70        DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
71        pkt->set(IMR);
72        break;
73    }
74    return latency;
75}
76
77Tick
78X86ISA::I8259::write(PacketPtr pkt)
79{
80    assert(pkt->getSize() == 1);
81    uint8_t val = pkt->get<uint8_t>();
82    switch (pkt->getAddr() - pioAddr) {
83      case 0x0:
84        if (bits(val, 4)) {
85            DPRINTF(I8259, "Received initialization command word 1.\n");
86            IMR = 0;
87            edgeTriggered = bits(val, 3);
88            DPRINTF(I8259, "%s triggered mode.\n",
89                    edgeTriggered ? "Edge" : "Level");
90            cascadeMode = !bits(val, 1);
91            DPRINTF(I8259, "%s mode.\n",
92                    cascadeMode ? "Cascade" : "Single");
93            expectICW4 = bits(val, 0);
94            initControlWord = 1;
95            DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
96        } else if (bits(val, 4, 3) == 0) {
97            DPRINTF(I8259, "Received operation command word 2.\n");
98            switch (bits(val, 7, 5)) {
99              case 0x0:
100                DPRINTF(I8259,
101                        "Subcommand: Rotate in auto-EOI mode (clear).\n");
102                break;
103              case 0x1:
104                DPRINTF(I8259, "Subcommand: Nonspecific EOI.\n");
105                break;
106              case 0x2:
107                DPRINTF(I8259, "Subcommand: No operation.\n");
108                break;
109              case 0x3:
110                DPRINTF(I8259, "Subcommand: Specific EIO.");
111                DPRINTF(I8259, "Reset In-Service bit %d.\n", bits(val, 2, 0));
112                break;
113              case 0x4:
114                DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
115                break;
116              case 0x5:
117                DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
118                break;
119              case 0x6:
120                DPRINTF(I8259, "Subcommand: Set priority command.\n");
121                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
122                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
123                break;
124              case 0x7:
125                DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
126                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
127                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
128                break;
129            }
130        } else if (bits(val, 4, 3) == 1) {
131            DPRINTF(I8259, "Received operation command word 3.\n");
132            if (bits(val, 7)) {
133                DPRINTF(I8259, "%s special mask mode.\n",
134                        bits(val, 6) ? "Set" : "Clear");
135            }
136            if (bits(val, 1)) {
137                readIRR = bits(val, 0);
138                DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
139            }
140        }
141        break;
142      case 0x1:
143        switch (initControlWord) {
144          case 0x0:
145            DPRINTF(I8259, "Received operation command word 1.\n");
146            DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
147            IMR = val;
148            break;
149          case 0x1:
150            DPRINTF(I8259, "Received initialization command word 2.\n");
151            vectorOffset = val & ~mask(3);
152            DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
153                    vectorOffset, vectorOffset | mask(3));
154            if (cascadeMode) {
155                initControlWord++;
156            } else {
157                cascadeBits = 0;
158                initControlWord = 0;
159            }
160            break;
161          case 0x2:
162            DPRINTF(I8259, "Received initialization command word 3.\n");
163            if (mode == Enums::I8259Master) {
164                DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
165                        bits(val, 0) ? " 0" : "",
166                        bits(val, 1) ? " 1" : "",
167                        bits(val, 2) ? " 2" : "",
168                        bits(val, 3) ? " 3" : "",
169                        bits(val, 4) ? " 4" : "",
170                        bits(val, 5) ? " 5" : "",
171                        bits(val, 6) ? " 6" : "",
172                        bits(val, 7) ? " 7" : "");
173                cascadeBits = val;
174            } else {
175                DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
176                cascadeBits = val & mask(3);
177            }
178            if (expectICW4)
179                initControlWord++;
180            else
181                initControlWord = 0;
182            break;
183          case 0x3:
184            DPRINTF(I8259, "Received initialization command word 4.\n");
185            if (bits(val, 4)) {
186                DPRINTF(I8259, "Special fully nested mode.\n");
187            } else {
188                DPRINTF(I8259, "Not special fully nested mode.\n");
189            }
190            if (bits(val, 3) == 0) {
191                DPRINTF(I8259, "Nonbuffered.\n");
192            } else if (bits(val, 2) == 0) {
193                DPRINTF(I8259, "Buffered.\n");
194            } else {
195                DPRINTF(I8259, "Unrecognized buffer mode.\n");
196            }
197            DPRINTF(I8259, "%s End Of Interrupt.\n",
198                    bits(val, 1) ? "Automatic" : "Normal");
199            DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
200            initControlWord = 0;
201            break;
202        }
203        break;
204    }
205    return latency;
206}
207
208void
209X86ISA::I8259::signalInterrupt(int line)
210{
211    DPRINTF(I8259, "Interrupt raised on line %d.\n", line);
212    if (line >= NumLines)
213        fatal("Line number %d doesn't exist. The max is %d.\n",
214                line, NumLines - 1);
215    if (bits(IMR, line)) {
216        DPRINTF(I8259, "Interrupt %d was masked.\n", line);
217    } else {
218        IRR |= 1 << line;
219        if (bits(ISR, 7, line) == 0) {
220            if (output) {
221                DPRINTF(I8259, "Propogating interrupt.\n");
222                output->signalInterrupt();
223            } else {
224                warn("Received interrupt but didn't have "
225                        "anyone to tell about it.\n");
226            }
227        }
228    }
229}
230
231int
232X86ISA::I8259::getVector()
233{
234    /*
235     * This code only handles one slave. Since that's how the PC platform
236     * always uses the 8259 PIC, there shouldn't be any need for more. If
237     * there -is- a need for more for some reason, "slave" can become a
238     * vector of slaves.
239     */
240    int line = findMsbSet(IRR);
241    IRR &= ~(1 << line);
242    DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
243    ISR |= 1 << line;
244    if (slave && bits(cascadeBits, line)) {
245        DPRINTF(I8259, "Interrupt was from slave who will "
246                "provide the vector.\n");
247        return slave->getVector();
248    }
249    return line | vectorOffset;
250}
251
252X86ISA::I8259 *
253I8259Params::create()
254{
255    return new X86ISA::I8259(this);
256}
257