i8259.cc revision 5632:65132fd646c6
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "base/bitfield.hh" 32#include "dev/x86/i8259.hh" 33 34Tick 35X86ISA::I8259::read(PacketPtr pkt) 36{ 37 assert(pkt->getSize() == 1); 38 switch(pkt->getAddr() - pioAddr) 39 { 40 case 0x0: 41 if (readIRR) { 42 DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 43 pkt->set(IRR); 44 } else { 45 DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 46 pkt->set(ISR); 47 } 48 break; 49 case 0x1: 50 DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 51 pkt->set(IMR); 52 break; 53 } 54 return latency; 55} 56 57Tick 58X86ISA::I8259::write(PacketPtr pkt) 59{ 60 assert(pkt->getSize() == 1); 61 uint8_t val = pkt->get<uint8_t>(); 62 switch (pkt->getAddr() - pioAddr) { 63 case 0x0: 64 if (bits(val, 4)) { 65 DPRINTF(I8259, "Received initialization command word 1.\n"); 66 IMR = 0; 67 edgeTriggered = bits(val, 3); 68 DPRINTF(I8259, "%s triggered mode.\n", 69 edgeTriggered ? "Edge" : "Level"); 70 cascadeMode = !bits(val, 1); 71 DPRINTF(I8259, "%s mode.\n", 72 cascadeMode ? "Cascade" : "Single"); 73 expectICW4 = bits(val, 0); 74 initControlWord = 1; 75 DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 76 } else if (bits(val, 4, 3) == 0) { 77 DPRINTF(I8259, "Received operation command word 2.\n"); 78 switch (bits(val, 7, 5)) { 79 case 0x0: 80 DPRINTF(I8259, 81 "Subcommand: Rotate in auto-EOI mode (clear).\n"); 82 break; 83 case 0x1: 84 DPRINTF(I8259, "Subcommand: Nonspecific EOI.\n"); 85 break; 86 case 0x2: 87 DPRINTF(I8259, "Subcommand: No operation.\n"); 88 break; 89 case 0x3: 90 DPRINTF(I8259, "Subcommand: Specific EIO."); 91 DPRINTF(I8259, "Reset In-Service bit %d.\n", bits(val, 2, 0)); 92 break; 93 case 0x4: 94 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 95 break; 96 case 0x5: 97 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 98 break; 99 case 0x6: 100 DPRINTF(I8259, "Subcommand: Set priority command.\n"); 101 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 102 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 103 break; 104 case 0x7: 105 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 106 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 107 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 108 break; 109 } 110 } else if (bits(val, 4, 3) == 1) { 111 DPRINTF(I8259, "Received operation command word 3.\n"); 112 if (bits(val, 7)) { 113 DPRINTF(I8259, "%s special mask mode.\n", 114 bits(val, 6) ? "Set" : "Clear"); 115 } 116 if (bits(val, 1)) { 117 readIRR = bits(val, 0); 118 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 119 } 120 } 121 break; 122 case 0x1: 123 switch (initControlWord) { 124 case 0x0: 125 DPRINTF(I8259, "Received operation command word 1.\n"); 126 DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 127 IMR = val; 128 break; 129 case 0x1: 130 DPRINTF(I8259, "Received initialization command word 2.\n"); 131 DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 132 val & ~mask(3), val | mask(3)); 133 if (cascadeMode) { 134 initControlWord++; 135 } else { 136 cascadeBits = 0; 137 initControlWord = 0; 138 } 139 break; 140 case 0x2: 141 DPRINTF(I8259, "Received initialization command word 3.\n"); 142 if (master == NULL) { 143 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 144 bits(val, 0) ? " 0" : "", 145 bits(val, 1) ? " 1" : "", 146 bits(val, 2) ? " 2" : "", 147 bits(val, 3) ? " 3" : "", 148 bits(val, 4) ? " 4" : "", 149 bits(val, 5) ? " 5" : "", 150 bits(val, 6) ? " 6" : "", 151 bits(val, 7) ? " 7" : ""); 152 cascadeBits = val; 153 } else { 154 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 155 cascadeBits = val & mask(3); 156 } 157 if (expectICW4) 158 initControlWord++; 159 else 160 initControlWord = 0; 161 break; 162 case 0x3: 163 DPRINTF(I8259, "Received initialization command word 4.\n"); 164 if (bits(val, 4)) { 165 DPRINTF(I8259, "Special fully nested mode.\n"); 166 } else { 167 DPRINTF(I8259, "Not special fully nested mode.\n"); 168 } 169 if (bits(val, 3) == 0) { 170 DPRINTF(I8259, "Nonbuffered.\n"); 171 } else if (bits(val, 2) == 0) { 172 DPRINTF(I8259, "Buffered.\n"); 173 } else { 174 DPRINTF(I8259, "Unrecognized buffer mode.\n"); 175 } 176 DPRINTF(I8259, "%s End Of Interrupt.\n", 177 bits(val, 1) ? "Automatic" : "Normal"); 178 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 179 initControlWord = 0; 180 break; 181 } 182 break; 183 } 184 return latency; 185} 186 187void 188X86ISA::I8259::signalInterrupt(int line) 189{ 190 DPRINTF(I8259, "Interrupt raised on line %d.\n", line); 191 if (line > 7) 192 fatal("Line number %d doesn't exist. The max is 7.\n"); 193 if (bits(IMR, line)) { 194 DPRINTF(I8259, "Interrupt %d was masked.\n", line); 195 } else if (master != NULL) { 196 DPRINTF(I8259, "Propogating interrupt to master.\n"); 197 master->signalInterrupt(cascadeBits); 198 } 199} 200 201X86ISA::I8259 * 202I8259Params::create() 203{ 204 return new X86ISA::I8259(this); 205} 206