i8259.cc revision 9808
111663Stushar@ece.gatech.edu/* 211663Stushar@ece.gatech.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 311663Stushar@ece.gatech.edu * All rights reserved. 411663Stushar@ece.gatech.edu * 511663Stushar@ece.gatech.edu * Redistribution and use in source and binary forms, with or without 611663Stushar@ece.gatech.edu * modification, are permitted provided that the following conditions are 711663Stushar@ece.gatech.edu * met: redistributions of source code must retain the above copyright 811663Stushar@ece.gatech.edu * notice, this list of conditions and the following disclaimer; 911663Stushar@ece.gatech.edu * redistributions in binary form must reproduce the above copyright 1011663Stushar@ece.gatech.edu * notice, this list of conditions and the following disclaimer in the 1111663Stushar@ece.gatech.edu * documentation and/or other materials provided with the distribution; 1211663Stushar@ece.gatech.edu * neither the name of the copyright holders nor the names of its 1311663Stushar@ece.gatech.edu * contributors may be used to endorse or promote products derived from 1411663Stushar@ece.gatech.edu * this software without specific prior written permission. 1511663Stushar@ece.gatech.edu * 1611663Stushar@ece.gatech.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1711663Stushar@ece.gatech.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1811663Stushar@ece.gatech.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1911663Stushar@ece.gatech.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2011663Stushar@ece.gatech.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2111663Stushar@ece.gatech.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2211663Stushar@ece.gatech.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2311663Stushar@ece.gatech.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2411663Stushar@ece.gatech.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2511663Stushar@ece.gatech.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2611663Stushar@ece.gatech.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2711663Stushar@ece.gatech.edu * 2811663Stushar@ece.gatech.edu * Authors: Gabe Black 2911663Stushar@ece.gatech.edu */ 3011663Stushar@ece.gatech.edu 3111663Stushar@ece.gatech.edu#include "base/bitfield.hh" 3211663Stushar@ece.gatech.edu#include "debug/I8259.hh" 3311663Stushar@ece.gatech.edu#include "dev/x86/i82094aa.hh" 3411663Stushar@ece.gatech.edu#include "dev/x86/i8259.hh" 3511663Stushar@ece.gatech.edu#include "mem/packet.hh" 3611663Stushar@ece.gatech.edu#include "mem/packet_access.hh" 3711663Stushar@ece.gatech.edu 3811663Stushar@ece.gatech.eduX86ISA::I8259::I8259(Params * p) 3911663Stushar@ece.gatech.edu : BasicPioDevice(p, 2), IntDevice(this), 4011663Stushar@ece.gatech.edu latency(p->pio_latency), output(p->output), 4111663Stushar@ece.gatech.edu mode(p->mode), slave(p->slave), 4211663Stushar@ece.gatech.edu IRR(0), ISR(0), IMR(0), 4311663Stushar@ece.gatech.edu readIRR(true), initControlWord(0), autoEOI(false) 4411663Stushar@ece.gatech.edu{ 4511663Stushar@ece.gatech.edu for (int i = 0; i < NumLines; i++) 4611663Stushar@ece.gatech.edu pinStates[i] = false; 4711663Stushar@ece.gatech.edu} 4811663Stushar@ece.gatech.edu 4911663Stushar@ece.gatech.eduTick 5011666Stushar@ece.gatech.eduX86ISA::I8259::read(PacketPtr pkt) 5111666Stushar@ece.gatech.edu{ 5211666Stushar@ece.gatech.edu assert(pkt->getSize() == 1); 5311666Stushar@ece.gatech.edu switch(pkt->getAddr() - pioAddr) 5411666Stushar@ece.gatech.edu { 5511666Stushar@ece.gatech.edu case 0x0: 5611663Stushar@ece.gatech.edu if (readIRR) { 5711663Stushar@ece.gatech.edu DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 5811663Stushar@ece.gatech.edu pkt->set(IRR); 5911663Stushar@ece.gatech.edu } else { 6011663Stushar@ece.gatech.edu DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 6111663Stushar@ece.gatech.edu pkt->set(ISR); 6211663Stushar@ece.gatech.edu } 6311663Stushar@ece.gatech.edu break; 6411663Stushar@ece.gatech.edu case 0x1: 6511663Stushar@ece.gatech.edu DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 6611663Stushar@ece.gatech.edu pkt->set(IMR); 6711663Stushar@ece.gatech.edu break; 6811663Stushar@ece.gatech.edu } 6911663Stushar@ece.gatech.edu pkt->makeAtomicResponse(); 7011663Stushar@ece.gatech.edu return latency; 7111663Stushar@ece.gatech.edu} 7211663Stushar@ece.gatech.edu 7311666Stushar@ece.gatech.eduTick 7411663Stushar@ece.gatech.eduX86ISA::I8259::write(PacketPtr pkt) 7511663Stushar@ece.gatech.edu{ 7611663Stushar@ece.gatech.edu assert(pkt->getSize() == 1); 7711663Stushar@ece.gatech.edu uint8_t val = pkt->get<uint8_t>(); 7811663Stushar@ece.gatech.edu switch (pkt->getAddr() - pioAddr) { 7911663Stushar@ece.gatech.edu case 0x0: 8011663Stushar@ece.gatech.edu if (bits(val, 4)) { 8111666Stushar@ece.gatech.edu DPRINTF(I8259, "Received initialization command word 1.\n"); 8211666Stushar@ece.gatech.edu IMR = 0; 8311663Stushar@ece.gatech.edu edgeTriggered = bits(val, 3); 8411663Stushar@ece.gatech.edu DPRINTF(I8259, "%s triggered mode.\n", 8511663Stushar@ece.gatech.edu edgeTriggered ? "Edge" : "Level"); 8611663Stushar@ece.gatech.edu cascadeMode = !bits(val, 1); 8711663Stushar@ece.gatech.edu DPRINTF(I8259, "%s mode.\n", 8811663Stushar@ece.gatech.edu cascadeMode ? "Cascade" : "Single"); 8911663Stushar@ece.gatech.edu expectICW4 = bits(val, 0); 9011663Stushar@ece.gatech.edu if (!expectICW4) { 9111663Stushar@ece.gatech.edu autoEOI = false; 9211663Stushar@ece.gatech.edu } 9311663Stushar@ece.gatech.edu initControlWord = 1; 9411666Stushar@ece.gatech.edu DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 9511666Stushar@ece.gatech.edu } else if (bits(val, 4, 3) == 0) { 9611663Stushar@ece.gatech.edu DPRINTF(I8259, "Received operation command word 2.\n"); 9711663Stushar@ece.gatech.edu switch (bits(val, 7, 5)) { 9811663Stushar@ece.gatech.edu case 0x0: 9911663Stushar@ece.gatech.edu DPRINTF(I8259, 10011666Stushar@ece.gatech.edu "Subcommand: Rotate in auto-EOI mode (clear).\n"); 10111666Stushar@ece.gatech.edu break; 10211663Stushar@ece.gatech.edu case 0x1: 10311663Stushar@ece.gatech.edu { 10411666Stushar@ece.gatech.edu int line = findMsbSet(ISR); 10511666Stushar@ece.gatech.edu DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 10611663Stushar@ece.gatech.edu line); 10711663Stushar@ece.gatech.edu handleEOI(line); 10811666Stushar@ece.gatech.edu } 10911666Stushar@ece.gatech.edu break; 11011663Stushar@ece.gatech.edu case 0x2: 11111663Stushar@ece.gatech.edu DPRINTF(I8259, "Subcommand: No operation.\n"); 11211666Stushar@ece.gatech.edu break; 11311666Stushar@ece.gatech.edu case 0x3: 11411663Stushar@ece.gatech.edu { 11511663Stushar@ece.gatech.edu int line = bits(val, 2, 0); 11611663Stushar@ece.gatech.edu DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 11711663Stushar@ece.gatech.edu line); 11811663Stushar@ece.gatech.edu handleEOI(line); 11911663Stushar@ece.gatech.edu } 12011666Stushar@ece.gatech.edu break; 12111666Stushar@ece.gatech.edu case 0x4: 12211663Stushar@ece.gatech.edu DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 12311663Stushar@ece.gatech.edu break; 12411663Stushar@ece.gatech.edu case 0x5: 12511663Stushar@ece.gatech.edu DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 12611663Stushar@ece.gatech.edu break; 12711663Stushar@ece.gatech.edu case 0x6: 12811663Stushar@ece.gatech.edu DPRINTF(I8259, "Subcommand: Set priority command.\n"); 12911663Stushar@ece.gatech.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 13011663Stushar@ece.gatech.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 13111663Stushar@ece.gatech.edu break; 13211663Stushar@ece.gatech.edu case 0x7: 13311663Stushar@ece.gatech.edu DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 13411663Stushar@ece.gatech.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 13511663Stushar@ece.gatech.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 13611663Stushar@ece.gatech.edu break; 13711666Stushar@ece.gatech.edu } 13811666Stushar@ece.gatech.edu } else if (bits(val, 4, 3) == 1) { 13911666Stushar@ece.gatech.edu DPRINTF(I8259, "Received operation command word 3.\n"); 14011663Stushar@ece.gatech.edu if (bits(val, 7)) { 14111663Stushar@ece.gatech.edu DPRINTF(I8259, "%s special mask mode.\n", 14211663Stushar@ece.gatech.edu bits(val, 6) ? "Set" : "Clear"); 14311663Stushar@ece.gatech.edu } 14411663Stushar@ece.gatech.edu if (bits(val, 1)) { 14511663Stushar@ece.gatech.edu readIRR = bits(val, 0); 14611663Stushar@ece.gatech.edu DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 14711663Stushar@ece.gatech.edu } 14811663Stushar@ece.gatech.edu } 14911663Stushar@ece.gatech.edu break; 15011663Stushar@ece.gatech.edu case 0x1: 15111663Stushar@ece.gatech.edu switch (initControlWord) { 15211666Stushar@ece.gatech.edu case 0x0: 15311666Stushar@ece.gatech.edu DPRINTF(I8259, "Received operation command word 1.\n"); 15411666Stushar@ece.gatech.edu DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 15511663Stushar@ece.gatech.edu IMR = val; 15611663Stushar@ece.gatech.edu break; 15711663Stushar@ece.gatech.edu case 0x1: 15811663Stushar@ece.gatech.edu DPRINTF(I8259, "Received initialization command word 2.\n"); 15911663Stushar@ece.gatech.edu vectorOffset = val & ~mask(3); 16011663Stushar@ece.gatech.edu DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 16111663Stushar@ece.gatech.edu vectorOffset, vectorOffset | mask(3)); 16211663Stushar@ece.gatech.edu if (cascadeMode) { 16311663Stushar@ece.gatech.edu initControlWord++; 16411663Stushar@ece.gatech.edu } else { 16511663Stushar@ece.gatech.edu cascadeBits = 0; 16611663Stushar@ece.gatech.edu initControlWord = 0; 16711666Stushar@ece.gatech.edu } 16811666Stushar@ece.gatech.edu break; 16911666Stushar@ece.gatech.edu case 0x2: 17011663Stushar@ece.gatech.edu DPRINTF(I8259, "Received initialization command word 3.\n"); 17111663Stushar@ece.gatech.edu if (mode == Enums::I8259Master) { 17211663Stushar@ece.gatech.edu DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 17311663Stushar@ece.gatech.edu bits(val, 0) ? " 0" : "", 17411663Stushar@ece.gatech.edu bits(val, 1) ? " 1" : "", 17511663Stushar@ece.gatech.edu bits(val, 2) ? " 2" : "", 17611663Stushar@ece.gatech.edu bits(val, 3) ? " 3" : "", 17711663Stushar@ece.gatech.edu bits(val, 4) ? " 4" : "", 17811663Stushar@ece.gatech.edu bits(val, 5) ? " 5" : "", 17911663Stushar@ece.gatech.edu bits(val, 6) ? " 6" : "", 18011663Stushar@ece.gatech.edu bits(val, 7) ? " 7" : ""); 18111663Stushar@ece.gatech.edu cascadeBits = val; 18211666Stushar@ece.gatech.edu } else { 18311666Stushar@ece.gatech.edu DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 18411666Stushar@ece.gatech.edu cascadeBits = val & mask(3); 18511663Stushar@ece.gatech.edu } 18611663Stushar@ece.gatech.edu if (expectICW4) 18711663Stushar@ece.gatech.edu initControlWord++; 18811663Stushar@ece.gatech.edu else 18911663Stushar@ece.gatech.edu initControlWord = 0; 190 break; 191 case 0x3: 192 DPRINTF(I8259, "Received initialization command word 4.\n"); 193 if (bits(val, 4)) { 194 DPRINTF(I8259, "Special fully nested mode.\n"); 195 } else { 196 DPRINTF(I8259, "Not special fully nested mode.\n"); 197 } 198 if (bits(val, 3) == 0) { 199 DPRINTF(I8259, "Nonbuffered.\n"); 200 } else if (bits(val, 2) == 0) { 201 DPRINTF(I8259, "Buffered.\n"); 202 } else { 203 DPRINTF(I8259, "Unrecognized buffer mode.\n"); 204 } 205 autoEOI = bits(val, 1); 206 DPRINTF(I8259, "%s End Of Interrupt.\n", 207 autoEOI ? "Automatic" : "Normal"); 208 209 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 210 initControlWord = 0; 211 break; 212 } 213 break; 214 } 215 pkt->makeAtomicResponse(); 216 return latency; 217} 218 219void 220X86ISA::I8259::handleEOI(int line) 221{ 222 ISR &= ~(1 << line); 223 // There may be an interrupt that was waiting which can 224 // now be sent. 225 if (IRR) 226 requestInterrupt(findMsbSet(IRR)); 227} 228 229void 230X86ISA::I8259::requestInterrupt(int line) 231{ 232 if (bits(ISR, 7, line) == 0) { 233 if (output) { 234 DPRINTF(I8259, "Propogating interrupt.\n"); 235 output->raise(); 236 //XXX This is a hack. 237 output->lower(); 238 } else { 239 warn("Received interrupt but didn't have " 240 "anyone to tell about it.\n"); 241 } 242 } 243} 244 245void 246X86ISA::I8259::signalInterrupt(int line) 247{ 248 DPRINTF(I8259, "Interrupt requested for line %d.\n", line); 249 if (line >= NumLines) 250 fatal("Line number %d doesn't exist. The max is %d.\n", 251 line, NumLines - 1); 252 if (bits(IMR, line)) { 253 DPRINTF(I8259, "Interrupt %d was masked.\n", line); 254 } else { 255 IRR |= 1 << line; 256 requestInterrupt(line); 257 } 258} 259 260void 261X86ISA::I8259::raiseInterruptPin(int number) 262{ 263 DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number); 264 if (number >= NumLines) 265 fatal("Line number %d doesn't exist. The max is %d.\n", 266 number, NumLines - 1); 267 if (!pinStates[number]) 268 signalInterrupt(number); 269 pinStates[number] = true; 270} 271 272void 273X86ISA::I8259::lowerInterruptPin(int number) 274{ 275 DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number); 276 if (number >= NumLines) 277 fatal("Line number %d doesn't exist. The max is %d.\n", 278 number, NumLines - 1); 279 pinStates[number] = false; 280} 281 282int 283X86ISA::I8259::getVector() 284{ 285 /* 286 * This code only handles one slave. Since that's how the PC platform 287 * always uses the 8259 PIC, there shouldn't be any need for more. If 288 * there -is- a need for more for some reason, "slave" can become a 289 * vector of slaves. 290 */ 291 int line = findMsbSet(IRR); 292 IRR &= ~(1 << line); 293 DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 294 if (autoEOI) { 295 handleEOI(line); 296 } else { 297 ISR |= 1 << line; 298 } 299 if (slave && bits(cascadeBits, line)) { 300 DPRINTF(I8259, "Interrupt was from slave who will " 301 "provide the vector.\n"); 302 return slave->getVector(); 303 } 304 return line | vectorOffset; 305} 306 307void 308X86ISA::I8259::serialize(std::ostream &os) 309{ 310 SERIALIZE_ARRAY(pinStates, NumLines); 311 SERIALIZE_ENUM(mode); 312 SERIALIZE_SCALAR(IRR); 313 SERIALIZE_SCALAR(ISR); 314 SERIALIZE_SCALAR(IMR); 315 SERIALIZE_SCALAR(vectorOffset); 316 SERIALIZE_SCALAR(cascadeMode); 317 SERIALIZE_SCALAR(cascadeBits); 318 SERIALIZE_SCALAR(edgeTriggered); 319 SERIALIZE_SCALAR(readIRR); 320 SERIALIZE_SCALAR(expectICW4); 321 SERIALIZE_SCALAR(initControlWord); 322 SERIALIZE_SCALAR(autoEOI); 323} 324 325void 326X86ISA::I8259::unserialize(Checkpoint *cp, const std::string §ion) 327{ 328 UNSERIALIZE_ARRAY(pinStates, NumLines); 329 UNSERIALIZE_ENUM(mode); 330 UNSERIALIZE_SCALAR(IRR); 331 UNSERIALIZE_SCALAR(ISR); 332 UNSERIALIZE_SCALAR(IMR); 333 UNSERIALIZE_SCALAR(vectorOffset); 334 UNSERIALIZE_SCALAR(cascadeMode); 335 UNSERIALIZE_SCALAR(cascadeBits); 336 UNSERIALIZE_SCALAR(edgeTriggered); 337 UNSERIALIZE_SCALAR(readIRR); 338 UNSERIALIZE_SCALAR(expectICW4); 339 UNSERIALIZE_SCALAR(initControlWord); 340 UNSERIALIZE_SCALAR(autoEOI); 341} 342 343X86ISA::I8259 * 344I8259Params::create() 345{ 346 return new X86ISA::I8259(this); 347} 348