i8259.cc revision 8232
17404SAli.Saidi@ARM.com/* 210324SCurtis.Dunham@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 37404SAli.Saidi@ARM.com * All rights reserved. 47404SAli.Saidi@ARM.com * 57404SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67404SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77404SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97404SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107404SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117404SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127404SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137404SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147404SAli.Saidi@ARM.com * this software without specific prior written permission. 157404SAli.Saidi@ARM.com * 167404SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177404SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187404SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197404SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207404SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217404SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227404SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237404SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247404SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257404SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267404SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277404SAli.Saidi@ARM.com * 287404SAli.Saidi@ARM.com * Authors: Gabe Black 297404SAli.Saidi@ARM.com */ 307404SAli.Saidi@ARM.com 317404SAli.Saidi@ARM.com#include "base/bitfield.hh" 327404SAli.Saidi@ARM.com#include "debug/I8259.hh" 337404SAli.Saidi@ARM.com#include "dev/x86/i82094aa.hh" 347404SAli.Saidi@ARM.com#include "dev/x86/i8259.hh" 357404SAli.Saidi@ARM.com#include "mem/packet.hh" 367404SAli.Saidi@ARM.com#include "mem/packet_access.hh" 377404SAli.Saidi@ARM.com 3810037SARM gem5 DevelopersX86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this), 397404SAli.Saidi@ARM.com latency(p->pio_latency), output(p->output), 407404SAli.Saidi@ARM.com mode(p->mode), slave(p->slave), 417404SAli.Saidi@ARM.com IRR(0), ISR(0), IMR(0), 4210037SARM gem5 Developers readIRR(true), initControlWord(0), autoEOI(false) 4310037SARM gem5 Developers{ 447404SAli.Saidi@ARM.com for (int i = 0; i < NumLines; i++) 457404SAli.Saidi@ARM.com pinStates[i] = false; 467728SAli.Saidi@ARM.com pioSize = 2; 477404SAli.Saidi@ARM.com} 488245Snate@binkert.org 499152Satgutier@umich.eduTick 508245Snate@binkert.orgX86ISA::I8259::read(PacketPtr pkt) 518245Snate@binkert.org{ 527748SAli.Saidi@ARM.com assert(pkt->getSize() == 1); 537404SAli.Saidi@ARM.com switch(pkt->getAddr() - pioAddr) 547404SAli.Saidi@ARM.com { 557404SAli.Saidi@ARM.com case 0x0: 567404SAli.Saidi@ARM.com if (readIRR) { 5710037SARM gem5 Developers DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 5810037SARM gem5 Developers pkt->set(IRR); 5910037SARM gem5 Developers } else { 609258SAli.Saidi@ARM.com DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 6110037SARM gem5 Developers pkt->set(ISR); 6210037SARM gem5 Developers } 6310037SARM gem5 Developers break; 6410037SARM gem5 Developers case 0x1: 657439Sdam.sunwoo@arm.com DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 667576SAli.Saidi@ARM.com pkt->set(IMR); 6710037SARM gem5 Developers break; 6810037SARM gem5 Developers } 6910037SARM gem5 Developers pkt->makeAtomicResponse(); 7010037SARM gem5 Developers return latency; 7110037SARM gem5 Developers} 7210037SARM gem5 Developers 7310037SARM gem5 DevelopersTick 7410037SARM gem5 DevelopersX86ISA::I8259::write(PacketPtr pkt) 7510037SARM gem5 Developers{ 7610037SARM gem5 Developers assert(pkt->getSize() == 1); 7710037SARM gem5 Developers uint8_t val = pkt->get<uint8_t>(); 7810037SARM gem5 Developers switch (pkt->getAddr() - pioAddr) { 7910037SARM gem5 Developers case 0x0: 8010037SARM gem5 Developers if (bits(val, 4)) { 8110037SARM gem5 Developers DPRINTF(I8259, "Received initialization command word 1.\n"); 8210037SARM gem5 Developers IMR = 0; 8310037SARM gem5 Developers edgeTriggered = bits(val, 3); 847439Sdam.sunwoo@arm.com DPRINTF(I8259, "%s triggered mode.\n", 857404SAli.Saidi@ARM.com edgeTriggered ? "Edge" : "Level"); 867404SAli.Saidi@ARM.com cascadeMode = !bits(val, 1); 877404SAli.Saidi@ARM.com DPRINTF(I8259, "%s mode.\n", 887404SAli.Saidi@ARM.com cascadeMode ? "Cascade" : "Single"); 897404SAli.Saidi@ARM.com expectICW4 = bits(val, 0); 907404SAli.Saidi@ARM.com if (!expectICW4) { 9110037SARM gem5 Developers autoEOI = false; 9210037SARM gem5 Developers } 9310037SARM gem5 Developers initControlWord = 1; 9410037SARM gem5 Developers DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 959152Satgutier@umich.edu } else if (bits(val, 4, 3) == 0) { 969152Satgutier@umich.edu DPRINTF(I8259, "Received operation command word 2.\n"); 979152Satgutier@umich.edu switch (bits(val, 7, 5)) { 9810037SARM gem5 Developers case 0x0: 999152Satgutier@umich.edu DPRINTF(I8259, 1009342SAndreas.Sandberg@arm.com "Subcommand: Rotate in auto-EOI mode (clear).\n"); 1019152Satgutier@umich.edu break; 1029342SAndreas.Sandberg@arm.com case 0x1: 1039342SAndreas.Sandberg@arm.com { 1049152Satgutier@umich.edu int line = findMsbSet(ISR); 1059152Satgutier@umich.edu DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 1069152Satgutier@umich.edu line); 1077748SAli.Saidi@ARM.com handleEOI(line); 1089342SAndreas.Sandberg@arm.com } 1097404SAli.Saidi@ARM.com break; 1109342SAndreas.Sandberg@arm.com case 0x2: 1119152Satgutier@umich.edu DPRINTF(I8259, "Subcommand: No operation.\n"); 11210037SARM gem5 Developers break; 1139152Satgutier@umich.edu case 0x3: 11410037SARM gem5 Developers { 11510037SARM gem5 Developers int line = bits(val, 2, 0); 11610037SARM gem5 Developers DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 11710037SARM gem5 Developers line); 11810037SARM gem5 Developers handleEOI(line); 11910037SARM gem5 Developers } 12010037SARM gem5 Developers break; 12110037SARM gem5 Developers case 0x4: 1229342SAndreas.Sandberg@arm.com DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 1239342SAndreas.Sandberg@arm.com break; 1249152Satgutier@umich.edu case 0x5: 1259152Satgutier@umich.edu DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 1269152Satgutier@umich.edu break; 1279152Satgutier@umich.edu case 0x6: 12810037SARM gem5 Developers DPRINTF(I8259, "Subcommand: Set priority command.\n"); 12910037SARM gem5 Developers DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 13010037SARM gem5 Developers bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1319152Satgutier@umich.edu break; 13210037SARM gem5 Developers case 0x7: 13310037SARM gem5 Developers DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 1347733SAli.Saidi@ARM.com DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1357404SAli.Saidi@ARM.com bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1367404SAli.Saidi@ARM.com break; 1377748SAli.Saidi@ARM.com } 1389342SAndreas.Sandberg@arm.com } else if (bits(val, 4, 3) == 1) { 1397748SAli.Saidi@ARM.com DPRINTF(I8259, "Received operation command word 3.\n"); 1409342SAndreas.Sandberg@arm.com if (bits(val, 7)) { 1419524SAndreas.Sandberg@ARM.com DPRINTF(I8259, "%s special mask mode.\n", 1429152Satgutier@umich.edu bits(val, 6) ? "Set" : "Clear"); 1439152Satgutier@umich.edu } 1447748SAli.Saidi@ARM.com if (bits(val, 1)) { 1457748SAli.Saidi@ARM.com readIRR = bits(val, 0); 1467748SAli.Saidi@ARM.com DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 1479294Sandreas.hansson@arm.com } 1489294Sandreas.hansson@arm.com } 1497404SAli.Saidi@ARM.com break; 1507404SAli.Saidi@ARM.com case 0x1: 1518922Swilliam.wang@arm.com switch (initControlWord) { 1527404SAli.Saidi@ARM.com case 0x0: 1538922Swilliam.wang@arm.com DPRINTF(I8259, "Received operation command word 1.\n"); 1547404SAli.Saidi@ARM.com DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 1557404SAli.Saidi@ARM.com IMR = val; 1567404SAli.Saidi@ARM.com break; 15710037SARM gem5 Developers case 0x1: 15810037SARM gem5 Developers DPRINTF(I8259, "Received initialization command word 2.\n"); 15910037SARM gem5 Developers vectorOffset = val & ~mask(3); 16010037SARM gem5 Developers DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 1617404SAli.Saidi@ARM.com vectorOffset, vectorOffset | mask(3)); 1628733Sgeoffrey.blake@arm.com if (cascadeMode) { 16310109SGeoffrey.Blake@arm.com initControlWord++; 16410037SARM gem5 Developers } else { 16510109SGeoffrey.Blake@arm.com cascadeBits = 0; 1667439Sdam.sunwoo@arm.com initControlWord = 0; 1677439Sdam.sunwoo@arm.com } 1687439Sdam.sunwoo@arm.com break; 1697439Sdam.sunwoo@arm.com case 0x2: 1707404SAli.Saidi@ARM.com DPRINTF(I8259, "Received initialization command word 3.\n"); 1717439Sdam.sunwoo@arm.com if (mode == Enums::I8259Master) { 1727439Sdam.sunwoo@arm.com DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 17310109SGeoffrey.Blake@arm.com bits(val, 0) ? " 0" : "", 17410109SGeoffrey.Blake@arm.com bits(val, 1) ? " 1" : "", 17510109SGeoffrey.Blake@arm.com bits(val, 2) ? " 2" : "", 17610109SGeoffrey.Blake@arm.com bits(val, 3) ? " 3" : "", 17710109SGeoffrey.Blake@arm.com bits(val, 4) ? " 4" : "", 17810109SGeoffrey.Blake@arm.com bits(val, 5) ? " 5" : "", 17910109SGeoffrey.Blake@arm.com bits(val, 6) ? " 6" : "", 18010109SGeoffrey.Blake@arm.com bits(val, 7) ? " 7" : ""); 1818202SAli.Saidi@ARM.com cascadeBits = val; 1828202SAli.Saidi@ARM.com } else { 1838202SAli.Saidi@ARM.com DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 1848202SAli.Saidi@ARM.com cascadeBits = val & mask(3); 1858202SAli.Saidi@ARM.com } 1868202SAli.Saidi@ARM.com if (expectICW4) 1878202SAli.Saidi@ARM.com initControlWord++; 18810037SARM gem5 Developers else 1898202SAli.Saidi@ARM.com initControlWord = 0; 1908202SAli.Saidi@ARM.com break; 1917439Sdam.sunwoo@arm.com case 0x3: 1927439Sdam.sunwoo@arm.com DPRINTF(I8259, "Received initialization command word 4.\n"); 1937439Sdam.sunwoo@arm.com if (bits(val, 4)) { 19410037SARM gem5 Developers DPRINTF(I8259, "Special fully nested mode.\n"); 19510037SARM gem5 Developers } else { 1967439Sdam.sunwoo@arm.com DPRINTF(I8259, "Not special fully nested mode.\n"); 1977439Sdam.sunwoo@arm.com } 1987439Sdam.sunwoo@arm.com if (bits(val, 3) == 0) { 19910037SARM gem5 Developers DPRINTF(I8259, "Nonbuffered.\n"); 20010037SARM gem5 Developers } else if (bits(val, 2) == 0) { 20110037SARM gem5 Developers DPRINTF(I8259, "Buffered.\n"); 2027439Sdam.sunwoo@arm.com } else { 2038733Sgeoffrey.blake@arm.com DPRINTF(I8259, "Unrecognized buffer mode.\n"); 2047439Sdam.sunwoo@arm.com } 20510037SARM gem5 Developers autoEOI = bits(val, 1); 20610037SARM gem5 Developers DPRINTF(I8259, "%s End Of Interrupt.\n", 20710037SARM gem5 Developers autoEOI ? "Automatic" : "Normal"); 2087404SAli.Saidi@ARM.com 2097436Sdam.sunwoo@arm.com DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 2107436Sdam.sunwoo@arm.com initControlWord = 0; 21110037SARM gem5 Developers break; 21210037SARM gem5 Developers } 21310037SARM gem5 Developers break; 21410037SARM gem5 Developers } 21510037SARM gem5 Developers pkt->makeAtomicResponse(); 21610037SARM gem5 Developers return latency; 21710037SARM gem5 Developers} 21810037SARM gem5 Developers 21910037SARM gem5 Developersvoid 22010037SARM gem5 DevelopersX86ISA::I8259::handleEOI(int line) 22110037SARM gem5 Developers{ 22210037SARM gem5 Developers ISR &= ~(1 << line); 22310324SCurtis.Dunham@arm.com // There may be an interrupt that was waiting which can 22410037SARM gem5 Developers // now be sent. 22510037SARM gem5 Developers if (IRR) 22610037SARM gem5 Developers requestInterrupt(findMsbSet(IRR)); 22710037SARM gem5 Developers} 22810037SARM gem5 Developers 22910324SCurtis.Dunham@arm.comvoid 23010037SARM gem5 DevelopersX86ISA::I8259::requestInterrupt(int line) 23110037SARM gem5 Developers{ 23210037SARM gem5 Developers if (bits(ISR, 7, line) == 0) { 23310037SARM gem5 Developers if (output) { 23410324SCurtis.Dunham@arm.com DPRINTF(I8259, "Propogating interrupt.\n"); 23510037SARM gem5 Developers output->raise(); 23610037SARM gem5 Developers //XXX This is a hack. 23710037SARM gem5 Developers output->lower(); 23810037SARM gem5 Developers } else { 23910037SARM gem5 Developers warn("Received interrupt but didn't have " 24010037SARM gem5 Developers "anyone to tell about it.\n"); 24110037SARM gem5 Developers } 24210037SARM gem5 Developers } 24310037SARM gem5 Developers} 24410037SARM gem5 Developers 24510037SARM gem5 Developersvoid 24610037SARM gem5 DevelopersX86ISA::I8259::signalInterrupt(int line) 24710037SARM gem5 Developers{ 24810037SARM gem5 Developers DPRINTF(I8259, "Interrupt requested for line %d.\n", line); 2497439Sdam.sunwoo@arm.com if (line >= NumLines) 2507439Sdam.sunwoo@arm.com fatal("Line number %d doesn't exist. The max is %d.\n", 2517439Sdam.sunwoo@arm.com line, NumLines - 1); 2527439Sdam.sunwoo@arm.com if (bits(IMR, line)) { 2537439Sdam.sunwoo@arm.com DPRINTF(I8259, "Interrupt %d was masked.\n", line); 25410037SARM gem5 Developers } else { 25510037SARM gem5 Developers IRR |= 1 << line; 25610037SARM gem5 Developers requestInterrupt(line); 25710037SARM gem5 Developers } 25810037SARM gem5 Developers} 25910037SARM gem5 Developers 26010037SARM gem5 Developersvoid 2617728SAli.Saidi@ARM.comX86ISA::I8259::raiseInterruptPin(int number) 26210037SARM gem5 Developers{ 26310037SARM gem5 Developers DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number); 26410037SARM gem5 Developers if (number >= NumLines) 26510037SARM gem5 Developers fatal("Line number %d doesn't exist. The max is %d.\n", 26610037SARM gem5 Developers number, NumLines - 1); 26710037SARM gem5 Developers if (!pinStates[number]) 26810037SARM gem5 Developers signalInterrupt(number); 26910037SARM gem5 Developers pinStates[number] = true; 27010037SARM gem5 Developers} 27110037SARM gem5 Developers 27210037SARM gem5 Developersvoid 27310037SARM gem5 DevelopersX86ISA::I8259::lowerInterruptPin(int number) 27410037SARM gem5 Developers{ 27510037SARM gem5 Developers DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number); 27610109SGeoffrey.Blake@arm.com if (number >= NumLines) 27710037SARM gem5 Developers fatal("Line number %d doesn't exist. The max is %d.\n", 27810109SGeoffrey.Blake@arm.com number, NumLines - 1); 27910037SARM gem5 Developers pinStates[number] = false; 28010109SGeoffrey.Blake@arm.com} 28110037SARM gem5 Developers 28210109SGeoffrey.Blake@arm.comint 28310109SGeoffrey.Blake@arm.comX86ISA::I8259::getVector() 28410109SGeoffrey.Blake@arm.com{ 28510109SGeoffrey.Blake@arm.com /* 28610109SGeoffrey.Blake@arm.com * This code only handles one slave. Since that's how the PC platform 28710109SGeoffrey.Blake@arm.com * always uses the 8259 PIC, there shouldn't be any need for more. If 28810109SGeoffrey.Blake@arm.com * there -is- a need for more for some reason, "slave" can become a 28910109SGeoffrey.Blake@arm.com * vector of slaves. 29010109SGeoffrey.Blake@arm.com */ 29110037SARM gem5 Developers int line = findMsbSet(IRR); 2927728SAli.Saidi@ARM.com IRR &= ~(1 << line); 2938067SAli.Saidi@ARM.com DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 2947728SAli.Saidi@ARM.com if (autoEOI) { 2957728SAli.Saidi@ARM.com handleEOI(line); 2967728SAli.Saidi@ARM.com } else { 2977728SAli.Saidi@ARM.com ISR |= 1 << line; 29810037SARM gem5 Developers } 29910037SARM gem5 Developers if (slave && bits(cascadeBits, line)) { 30010037SARM gem5 Developers DPRINTF(I8259, "Interrupt was from slave who will " 30110037SARM gem5 Developers "provide the vector.\n"); 30210037SARM gem5 Developers return slave->getVector(); 30310037SARM gem5 Developers } 3047728SAli.Saidi@ARM.com return line | vectorOffset; 3057728SAli.Saidi@ARM.com} 3067728SAli.Saidi@ARM.com 3077728SAli.Saidi@ARM.comvoid 3087728SAli.Saidi@ARM.comX86ISA::I8259::serialize(std::ostream &os) 3097728SAli.Saidi@ARM.com{ 3107728SAli.Saidi@ARM.com SERIALIZE_ARRAY(pinStates, NumLines); 3117728SAli.Saidi@ARM.com SERIALIZE_ENUM(mode); 3127728SAli.Saidi@ARM.com SERIALIZE_SCALAR(IRR); 3137728SAli.Saidi@ARM.com SERIALIZE_SCALAR(ISR); 3147728SAli.Saidi@ARM.com SERIALIZE_SCALAR(IMR); 3159258SAli.Saidi@ARM.com SERIALIZE_SCALAR(vectorOffset); 31610037SARM gem5 Developers SERIALIZE_SCALAR(cascadeMode); 31710037SARM gem5 Developers SERIALIZE_SCALAR(cascadeBits); 31810037SARM gem5 Developers SERIALIZE_SCALAR(edgeTriggered); 31910037SARM gem5 Developers SERIALIZE_SCALAR(readIRR); 32010037SARM gem5 Developers SERIALIZE_SCALAR(expectICW4); 32110037SARM gem5 Developers SERIALIZE_SCALAR(initControlWord); 3229535Smrinmoy.ghosh@arm.com SERIALIZE_SCALAR(autoEOI); 32310037SARM gem5 Developers} 32410037SARM gem5 Developers 32510037SARM gem5 Developersvoid 32610037SARM gem5 DevelopersX86ISA::I8259::unserialize(Checkpoint *cp, const std::string §ion) 3279258SAli.Saidi@ARM.com{ 3289535Smrinmoy.ghosh@arm.com UNSERIALIZE_ARRAY(pinStates, NumLines); 3299535Smrinmoy.ghosh@arm.com UNSERIALIZE_ENUM(mode); 3309535Smrinmoy.ghosh@arm.com UNSERIALIZE_SCALAR(IRR); 3319535Smrinmoy.ghosh@arm.com UNSERIALIZE_SCALAR(ISR); 3329535Smrinmoy.ghosh@arm.com UNSERIALIZE_SCALAR(IMR); 3339535Smrinmoy.ghosh@arm.com UNSERIALIZE_SCALAR(vectorOffset); 3349258SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(cascadeMode); 3359258SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(cascadeBits); 3369258SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(edgeTriggered); 33710037SARM gem5 Developers UNSERIALIZE_SCALAR(readIRR); 33810037SARM gem5 Developers UNSERIALIZE_SCALAR(expectICW4); 33910037SARM gem5 Developers UNSERIALIZE_SCALAR(initControlWord); 34010037SARM gem5 Developers UNSERIALIZE_SCALAR(autoEOI); 34110037SARM gem5 Developers} 34210037SARM gem5 Developers 3439258SAli.Saidi@ARM.comX86ISA::I8259 * 3449258SAli.Saidi@ARM.comI8259Params::create() 3459258SAli.Saidi@ARM.com{ 3469258SAli.Saidi@ARM.com return new X86ISA::I8259(this); 3479258SAli.Saidi@ARM.com} 3489258SAli.Saidi@ARM.com