i8259.cc revision 5898
15390SN/A/* 25390SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Gabe Black 295390SN/A */ 305390SN/A 315631Sgblack@eecs.umich.edu#include "base/bitfield.hh" 325657Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 335630Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 345698Snate@binkert.org#include "mem/packet.hh" 355698Snate@binkert.org#include "mem/packet_access.hh" 365390SN/A 375657Sgblack@eecs.umich.eduX86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this), 385657Sgblack@eecs.umich.edu latency(p->pio_latency), output(p->output), 395827Sgblack@eecs.umich.edu mode(p->mode), slave(p->slave), 405657Sgblack@eecs.umich.edu IRR(0), ISR(0), IMR(0), 415688Sgblack@eecs.umich.edu readIRR(true), initControlWord(0), autoEOI(false) 425657Sgblack@eecs.umich.edu{ 435827Sgblack@eecs.umich.edu for (int i = 0; i < NumLines; i++) 445827Sgblack@eecs.umich.edu pinStates[i] = false; 455657Sgblack@eecs.umich.edu pioSize = 2; 465657Sgblack@eecs.umich.edu} 475657Sgblack@eecs.umich.edu 485390SN/ATick 495390SN/AX86ISA::I8259::read(PacketPtr pkt) 505390SN/A{ 515631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 525631Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 535631Sgblack@eecs.umich.edu { 545631Sgblack@eecs.umich.edu case 0x0: 555631Sgblack@eecs.umich.edu if (readIRR) { 565631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 575631Sgblack@eecs.umich.edu pkt->set(IRR); 585631Sgblack@eecs.umich.edu } else { 595631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 605631Sgblack@eecs.umich.edu pkt->set(ISR); 615631Sgblack@eecs.umich.edu } 625631Sgblack@eecs.umich.edu break; 635631Sgblack@eecs.umich.edu case 0x1: 645631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 655631Sgblack@eecs.umich.edu pkt->set(IMR); 665631Sgblack@eecs.umich.edu break; 675631Sgblack@eecs.umich.edu } 685898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 695630Sgblack@eecs.umich.edu return latency; 705390SN/A} 715390SN/A 725390SN/ATick 735390SN/AX86ISA::I8259::write(PacketPtr pkt) 745390SN/A{ 755631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 765631Sgblack@eecs.umich.edu uint8_t val = pkt->get<uint8_t>(); 775631Sgblack@eecs.umich.edu switch (pkt->getAddr() - pioAddr) { 785631Sgblack@eecs.umich.edu case 0x0: 795631Sgblack@eecs.umich.edu if (bits(val, 4)) { 805631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 1.\n"); 815631Sgblack@eecs.umich.edu IMR = 0; 825631Sgblack@eecs.umich.edu edgeTriggered = bits(val, 3); 835631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s triggered mode.\n", 845631Sgblack@eecs.umich.edu edgeTriggered ? "Edge" : "Level"); 855631Sgblack@eecs.umich.edu cascadeMode = !bits(val, 1); 865631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", 875631Sgblack@eecs.umich.edu cascadeMode ? "Cascade" : "Single"); 885631Sgblack@eecs.umich.edu expectICW4 = bits(val, 0); 895688Sgblack@eecs.umich.edu if (!expectICW4) { 905688Sgblack@eecs.umich.edu autoEOI = false; 915688Sgblack@eecs.umich.edu } 925631Sgblack@eecs.umich.edu initControlWord = 1; 935631Sgblack@eecs.umich.edu DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 945631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 0) { 955631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 2.\n"); 965631Sgblack@eecs.umich.edu switch (bits(val, 7, 5)) { 975631Sgblack@eecs.umich.edu case 0x0: 985631Sgblack@eecs.umich.edu DPRINTF(I8259, 995631Sgblack@eecs.umich.edu "Subcommand: Rotate in auto-EOI mode (clear).\n"); 1005631Sgblack@eecs.umich.edu break; 1015631Sgblack@eecs.umich.edu case 0x1: 1025687Sgblack@eecs.umich.edu { 1035687Sgblack@eecs.umich.edu int line = findMsbSet(ISR); 1045687Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 1055687Sgblack@eecs.umich.edu line); 1065687Sgblack@eecs.umich.edu handleEOI(line); 1075687Sgblack@eecs.umich.edu } 1085631Sgblack@eecs.umich.edu break; 1095631Sgblack@eecs.umich.edu case 0x2: 1105631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: No operation.\n"); 1115631Sgblack@eecs.umich.edu break; 1125631Sgblack@eecs.umich.edu case 0x3: 1135686Sgblack@eecs.umich.edu { 1145686Sgblack@eecs.umich.edu int line = bits(val, 2, 0); 1155686Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 1165686Sgblack@eecs.umich.edu line); 1175686Sgblack@eecs.umich.edu handleEOI(line); 1185686Sgblack@eecs.umich.edu } 1195631Sgblack@eecs.umich.edu break; 1205631Sgblack@eecs.umich.edu case 0x4: 1215631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 1225631Sgblack@eecs.umich.edu break; 1235631Sgblack@eecs.umich.edu case 0x5: 1245631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 1255631Sgblack@eecs.umich.edu break; 1265631Sgblack@eecs.umich.edu case 0x6: 1275631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Set priority command.\n"); 1285631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1295631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1305631Sgblack@eecs.umich.edu break; 1315631Sgblack@eecs.umich.edu case 0x7: 1325631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 1335631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1345631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1355631Sgblack@eecs.umich.edu break; 1365631Sgblack@eecs.umich.edu } 1375631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 1) { 1385631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 3.\n"); 1395631Sgblack@eecs.umich.edu if (bits(val, 7)) { 1405631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s special mask mode.\n", 1415631Sgblack@eecs.umich.edu bits(val, 6) ? "Set" : "Clear"); 1425631Sgblack@eecs.umich.edu } 1435631Sgblack@eecs.umich.edu if (bits(val, 1)) { 1445631Sgblack@eecs.umich.edu readIRR = bits(val, 0); 1455631Sgblack@eecs.umich.edu DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 1465631Sgblack@eecs.umich.edu } 1475631Sgblack@eecs.umich.edu } 1485631Sgblack@eecs.umich.edu break; 1495631Sgblack@eecs.umich.edu case 0x1: 1505631Sgblack@eecs.umich.edu switch (initControlWord) { 1515631Sgblack@eecs.umich.edu case 0x0: 1525631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 1.\n"); 1535631Sgblack@eecs.umich.edu DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 1545631Sgblack@eecs.umich.edu IMR = val; 1555631Sgblack@eecs.umich.edu break; 1565631Sgblack@eecs.umich.edu case 0x1: 1575631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 2.\n"); 1585656Sgblack@eecs.umich.edu vectorOffset = val & ~mask(3); 1595631Sgblack@eecs.umich.edu DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 1605656Sgblack@eecs.umich.edu vectorOffset, vectorOffset | mask(3)); 1615631Sgblack@eecs.umich.edu if (cascadeMode) { 1625631Sgblack@eecs.umich.edu initControlWord++; 1635631Sgblack@eecs.umich.edu } else { 1645632Sgblack@eecs.umich.edu cascadeBits = 0; 1655631Sgblack@eecs.umich.edu initControlWord = 0; 1665631Sgblack@eecs.umich.edu } 1675631Sgblack@eecs.umich.edu break; 1685631Sgblack@eecs.umich.edu case 0x2: 1695631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 3.\n"); 1705634Sgblack@eecs.umich.edu if (mode == Enums::I8259Master) { 1715631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 1725631Sgblack@eecs.umich.edu bits(val, 0) ? " 0" : "", 1735631Sgblack@eecs.umich.edu bits(val, 1) ? " 1" : "", 1745631Sgblack@eecs.umich.edu bits(val, 2) ? " 2" : "", 1755631Sgblack@eecs.umich.edu bits(val, 3) ? " 3" : "", 1765631Sgblack@eecs.umich.edu bits(val, 4) ? " 4" : "", 1775631Sgblack@eecs.umich.edu bits(val, 5) ? " 5" : "", 1785631Sgblack@eecs.umich.edu bits(val, 6) ? " 6" : "", 1795631Sgblack@eecs.umich.edu bits(val, 7) ? " 7" : ""); 1805632Sgblack@eecs.umich.edu cascadeBits = val; 1815631Sgblack@eecs.umich.edu } else { 1825631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 1835632Sgblack@eecs.umich.edu cascadeBits = val & mask(3); 1845631Sgblack@eecs.umich.edu } 1855631Sgblack@eecs.umich.edu if (expectICW4) 1865631Sgblack@eecs.umich.edu initControlWord++; 1875631Sgblack@eecs.umich.edu else 1885631Sgblack@eecs.umich.edu initControlWord = 0; 1895631Sgblack@eecs.umich.edu break; 1905631Sgblack@eecs.umich.edu case 0x3: 1915631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 4.\n"); 1925631Sgblack@eecs.umich.edu if (bits(val, 4)) { 1935631Sgblack@eecs.umich.edu DPRINTF(I8259, "Special fully nested mode.\n"); 1945631Sgblack@eecs.umich.edu } else { 1955631Sgblack@eecs.umich.edu DPRINTF(I8259, "Not special fully nested mode.\n"); 1965631Sgblack@eecs.umich.edu } 1975631Sgblack@eecs.umich.edu if (bits(val, 3) == 0) { 1985631Sgblack@eecs.umich.edu DPRINTF(I8259, "Nonbuffered.\n"); 1995631Sgblack@eecs.umich.edu } else if (bits(val, 2) == 0) { 2005631Sgblack@eecs.umich.edu DPRINTF(I8259, "Buffered.\n"); 2015631Sgblack@eecs.umich.edu } else { 2025631Sgblack@eecs.umich.edu DPRINTF(I8259, "Unrecognized buffer mode.\n"); 2035631Sgblack@eecs.umich.edu } 2045688Sgblack@eecs.umich.edu autoEOI = bits(val, 1); 2055631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s End Of Interrupt.\n", 2065688Sgblack@eecs.umich.edu autoEOI ? "Automatic" : "Normal"); 2075688Sgblack@eecs.umich.edu 2085631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 2095631Sgblack@eecs.umich.edu initControlWord = 0; 2105631Sgblack@eecs.umich.edu break; 2115631Sgblack@eecs.umich.edu } 2125631Sgblack@eecs.umich.edu break; 2135631Sgblack@eecs.umich.edu } 2145898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2155630Sgblack@eecs.umich.edu return latency; 2165390SN/A} 2175630Sgblack@eecs.umich.edu 2185632Sgblack@eecs.umich.eduvoid 2195686Sgblack@eecs.umich.eduX86ISA::I8259::handleEOI(int line) 2205686Sgblack@eecs.umich.edu{ 2215686Sgblack@eecs.umich.edu ISR &= ~(1 << line); 2225686Sgblack@eecs.umich.edu // There may be an interrupt that was waiting which can 2235686Sgblack@eecs.umich.edu // now be sent. 2245686Sgblack@eecs.umich.edu if (IRR) 2255686Sgblack@eecs.umich.edu requestInterrupt(findMsbSet(IRR)); 2265686Sgblack@eecs.umich.edu} 2275686Sgblack@eecs.umich.edu 2285686Sgblack@eecs.umich.eduvoid 2295686Sgblack@eecs.umich.eduX86ISA::I8259::requestInterrupt(int line) 2305686Sgblack@eecs.umich.edu{ 2315686Sgblack@eecs.umich.edu if (bits(ISR, 7, line) == 0) { 2325686Sgblack@eecs.umich.edu if (output) { 2335686Sgblack@eecs.umich.edu DPRINTF(I8259, "Propogating interrupt.\n"); 2345827Sgblack@eecs.umich.edu output->raise(); 2355827Sgblack@eecs.umich.edu //XXX This is a hack. 2365827Sgblack@eecs.umich.edu output->lower(); 2375686Sgblack@eecs.umich.edu } else { 2385686Sgblack@eecs.umich.edu warn("Received interrupt but didn't have " 2395686Sgblack@eecs.umich.edu "anyone to tell about it.\n"); 2405686Sgblack@eecs.umich.edu } 2415686Sgblack@eecs.umich.edu } 2425686Sgblack@eecs.umich.edu} 2435686Sgblack@eecs.umich.edu 2445686Sgblack@eecs.umich.eduvoid 2455632Sgblack@eecs.umich.eduX86ISA::I8259::signalInterrupt(int line) 2465632Sgblack@eecs.umich.edu{ 2475830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt requested for line %d.\n", line); 2485657Sgblack@eecs.umich.edu if (line >= NumLines) 2495657Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2505657Sgblack@eecs.umich.edu line, NumLines - 1); 2515632Sgblack@eecs.umich.edu if (bits(IMR, line)) { 2525632Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was masked.\n", line); 2535634Sgblack@eecs.umich.edu } else { 2545657Sgblack@eecs.umich.edu IRR |= 1 << line; 2555686Sgblack@eecs.umich.edu requestInterrupt(line); 2565632Sgblack@eecs.umich.edu } 2575632Sgblack@eecs.umich.edu} 2585632Sgblack@eecs.umich.edu 2595827Sgblack@eecs.umich.eduvoid 2605827Sgblack@eecs.umich.eduX86ISA::I8259::raiseInterruptPin(int number) 2615827Sgblack@eecs.umich.edu{ 2625830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number); 2635827Sgblack@eecs.umich.edu if (number >= NumLines) 2645827Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2655827Sgblack@eecs.umich.edu number, NumLines - 1); 2665827Sgblack@eecs.umich.edu if (!pinStates[number]) 2675827Sgblack@eecs.umich.edu signalInterrupt(number); 2685827Sgblack@eecs.umich.edu pinStates[number] = true; 2695827Sgblack@eecs.umich.edu} 2705827Sgblack@eecs.umich.edu 2715827Sgblack@eecs.umich.eduvoid 2725827Sgblack@eecs.umich.eduX86ISA::I8259::lowerInterruptPin(int number) 2735827Sgblack@eecs.umich.edu{ 2745830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number); 2755827Sgblack@eecs.umich.edu if (number >= NumLines) 2765827Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2775827Sgblack@eecs.umich.edu number, NumLines - 1); 2785827Sgblack@eecs.umich.edu pinStates[number] = false; 2795827Sgblack@eecs.umich.edu} 2805827Sgblack@eecs.umich.edu 2815657Sgblack@eecs.umich.eduint 2825657Sgblack@eecs.umich.eduX86ISA::I8259::getVector() 2835657Sgblack@eecs.umich.edu{ 2845657Sgblack@eecs.umich.edu /* 2855657Sgblack@eecs.umich.edu * This code only handles one slave. Since that's how the PC platform 2865657Sgblack@eecs.umich.edu * always uses the 8259 PIC, there shouldn't be any need for more. If 2875657Sgblack@eecs.umich.edu * there -is- a need for more for some reason, "slave" can become a 2885657Sgblack@eecs.umich.edu * vector of slaves. 2895657Sgblack@eecs.umich.edu */ 2905657Sgblack@eecs.umich.edu int line = findMsbSet(IRR); 2915657Sgblack@eecs.umich.edu IRR &= ~(1 << line); 2925657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 2935688Sgblack@eecs.umich.edu if (autoEOI) { 2945688Sgblack@eecs.umich.edu handleEOI(line); 2955688Sgblack@eecs.umich.edu } else { 2965688Sgblack@eecs.umich.edu ISR |= 1 << line; 2975688Sgblack@eecs.umich.edu } 2985657Sgblack@eecs.umich.edu if (slave && bits(cascadeBits, line)) { 2995657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt was from slave who will " 3005657Sgblack@eecs.umich.edu "provide the vector.\n"); 3015657Sgblack@eecs.umich.edu return slave->getVector(); 3025657Sgblack@eecs.umich.edu } 3035657Sgblack@eecs.umich.edu return line | vectorOffset; 3045657Sgblack@eecs.umich.edu} 3055657Sgblack@eecs.umich.edu 3065630Sgblack@eecs.umich.eduX86ISA::I8259 * 3075630Sgblack@eecs.umich.eduI8259Params::create() 3085630Sgblack@eecs.umich.edu{ 3095630Sgblack@eecs.umich.edu return new X86ISA::I8259(this); 3105630Sgblack@eecs.umich.edu} 311