i8259.cc revision 5698
15390SN/A/* 25390SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Gabe Black 295390SN/A */ 305390SN/A 315631Sgblack@eecs.umich.edu#include "base/bitfield.hh" 325657Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 335630Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 345698Snate@binkert.org#include "mem/packet.hh" 355698Snate@binkert.org#include "mem/packet_access.hh" 365390SN/A 375657Sgblack@eecs.umich.eduX86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this), 385657Sgblack@eecs.umich.edu latency(p->pio_latency), output(p->output), 395657Sgblack@eecs.umich.edu mode(p->mode), slave(NULL), 405657Sgblack@eecs.umich.edu IRR(0), ISR(0), IMR(0), 415688Sgblack@eecs.umich.edu readIRR(true), initControlWord(0), autoEOI(false) 425657Sgblack@eecs.umich.edu{ 435657Sgblack@eecs.umich.edu if (output) { 445657Sgblack@eecs.umich.edu I8259 * master; 455657Sgblack@eecs.umich.edu master = dynamic_cast<I8259 *>(output->getDevice()); 465657Sgblack@eecs.umich.edu if (master) 475657Sgblack@eecs.umich.edu master->setSlave(this); 485657Sgblack@eecs.umich.edu I82094AA * ioApic; 495657Sgblack@eecs.umich.edu ioApic = dynamic_cast<I82094AA *>(output->getDevice()); 505657Sgblack@eecs.umich.edu if (ioApic) 515657Sgblack@eecs.umich.edu ioApic->setExtIntPic(this); 525657Sgblack@eecs.umich.edu } 535657Sgblack@eecs.umich.edu pioSize = 2; 545657Sgblack@eecs.umich.edu} 555657Sgblack@eecs.umich.edu 565390SN/ATick 575390SN/AX86ISA::I8259::read(PacketPtr pkt) 585390SN/A{ 595631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 605631Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 615631Sgblack@eecs.umich.edu { 625631Sgblack@eecs.umich.edu case 0x0: 635631Sgblack@eecs.umich.edu if (readIRR) { 645631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 655631Sgblack@eecs.umich.edu pkt->set(IRR); 665631Sgblack@eecs.umich.edu } else { 675631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 685631Sgblack@eecs.umich.edu pkt->set(ISR); 695631Sgblack@eecs.umich.edu } 705631Sgblack@eecs.umich.edu break; 715631Sgblack@eecs.umich.edu case 0x1: 725631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 735631Sgblack@eecs.umich.edu pkt->set(IMR); 745631Sgblack@eecs.umich.edu break; 755631Sgblack@eecs.umich.edu } 765630Sgblack@eecs.umich.edu return latency; 775390SN/A} 785390SN/A 795390SN/ATick 805390SN/AX86ISA::I8259::write(PacketPtr pkt) 815390SN/A{ 825631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 835631Sgblack@eecs.umich.edu uint8_t val = pkt->get<uint8_t>(); 845631Sgblack@eecs.umich.edu switch (pkt->getAddr() - pioAddr) { 855631Sgblack@eecs.umich.edu case 0x0: 865631Sgblack@eecs.umich.edu if (bits(val, 4)) { 875631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 1.\n"); 885631Sgblack@eecs.umich.edu IMR = 0; 895631Sgblack@eecs.umich.edu edgeTriggered = bits(val, 3); 905631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s triggered mode.\n", 915631Sgblack@eecs.umich.edu edgeTriggered ? "Edge" : "Level"); 925631Sgblack@eecs.umich.edu cascadeMode = !bits(val, 1); 935631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", 945631Sgblack@eecs.umich.edu cascadeMode ? "Cascade" : "Single"); 955631Sgblack@eecs.umich.edu expectICW4 = bits(val, 0); 965688Sgblack@eecs.umich.edu if (!expectICW4) { 975688Sgblack@eecs.umich.edu autoEOI = false; 985688Sgblack@eecs.umich.edu } 995631Sgblack@eecs.umich.edu initControlWord = 1; 1005631Sgblack@eecs.umich.edu DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 1015631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 0) { 1025631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 2.\n"); 1035631Sgblack@eecs.umich.edu switch (bits(val, 7, 5)) { 1045631Sgblack@eecs.umich.edu case 0x0: 1055631Sgblack@eecs.umich.edu DPRINTF(I8259, 1065631Sgblack@eecs.umich.edu "Subcommand: Rotate in auto-EOI mode (clear).\n"); 1075631Sgblack@eecs.umich.edu break; 1085631Sgblack@eecs.umich.edu case 0x1: 1095687Sgblack@eecs.umich.edu { 1105687Sgblack@eecs.umich.edu int line = findMsbSet(ISR); 1115687Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 1125687Sgblack@eecs.umich.edu line); 1135687Sgblack@eecs.umich.edu handleEOI(line); 1145687Sgblack@eecs.umich.edu } 1155631Sgblack@eecs.umich.edu break; 1165631Sgblack@eecs.umich.edu case 0x2: 1175631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: No operation.\n"); 1185631Sgblack@eecs.umich.edu break; 1195631Sgblack@eecs.umich.edu case 0x3: 1205686Sgblack@eecs.umich.edu { 1215686Sgblack@eecs.umich.edu int line = bits(val, 2, 0); 1225686Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 1235686Sgblack@eecs.umich.edu line); 1245686Sgblack@eecs.umich.edu handleEOI(line); 1255686Sgblack@eecs.umich.edu } 1265631Sgblack@eecs.umich.edu break; 1275631Sgblack@eecs.umich.edu case 0x4: 1285631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 1295631Sgblack@eecs.umich.edu break; 1305631Sgblack@eecs.umich.edu case 0x5: 1315631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 1325631Sgblack@eecs.umich.edu break; 1335631Sgblack@eecs.umich.edu case 0x6: 1345631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Set priority command.\n"); 1355631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1365631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1375631Sgblack@eecs.umich.edu break; 1385631Sgblack@eecs.umich.edu case 0x7: 1395631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 1405631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1415631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1425631Sgblack@eecs.umich.edu break; 1435631Sgblack@eecs.umich.edu } 1445631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 1) { 1455631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 3.\n"); 1465631Sgblack@eecs.umich.edu if (bits(val, 7)) { 1475631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s special mask mode.\n", 1485631Sgblack@eecs.umich.edu bits(val, 6) ? "Set" : "Clear"); 1495631Sgblack@eecs.umich.edu } 1505631Sgblack@eecs.umich.edu if (bits(val, 1)) { 1515631Sgblack@eecs.umich.edu readIRR = bits(val, 0); 1525631Sgblack@eecs.umich.edu DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 1535631Sgblack@eecs.umich.edu } 1545631Sgblack@eecs.umich.edu } 1555631Sgblack@eecs.umich.edu break; 1565631Sgblack@eecs.umich.edu case 0x1: 1575631Sgblack@eecs.umich.edu switch (initControlWord) { 1585631Sgblack@eecs.umich.edu case 0x0: 1595631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 1.\n"); 1605631Sgblack@eecs.umich.edu DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 1615631Sgblack@eecs.umich.edu IMR = val; 1625631Sgblack@eecs.umich.edu break; 1635631Sgblack@eecs.umich.edu case 0x1: 1645631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 2.\n"); 1655656Sgblack@eecs.umich.edu vectorOffset = val & ~mask(3); 1665631Sgblack@eecs.umich.edu DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 1675656Sgblack@eecs.umich.edu vectorOffset, vectorOffset | mask(3)); 1685631Sgblack@eecs.umich.edu if (cascadeMode) { 1695631Sgblack@eecs.umich.edu initControlWord++; 1705631Sgblack@eecs.umich.edu } else { 1715632Sgblack@eecs.umich.edu cascadeBits = 0; 1725631Sgblack@eecs.umich.edu initControlWord = 0; 1735631Sgblack@eecs.umich.edu } 1745631Sgblack@eecs.umich.edu break; 1755631Sgblack@eecs.umich.edu case 0x2: 1765631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 3.\n"); 1775634Sgblack@eecs.umich.edu if (mode == Enums::I8259Master) { 1785631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 1795631Sgblack@eecs.umich.edu bits(val, 0) ? " 0" : "", 1805631Sgblack@eecs.umich.edu bits(val, 1) ? " 1" : "", 1815631Sgblack@eecs.umich.edu bits(val, 2) ? " 2" : "", 1825631Sgblack@eecs.umich.edu bits(val, 3) ? " 3" : "", 1835631Sgblack@eecs.umich.edu bits(val, 4) ? " 4" : "", 1845631Sgblack@eecs.umich.edu bits(val, 5) ? " 5" : "", 1855631Sgblack@eecs.umich.edu bits(val, 6) ? " 6" : "", 1865631Sgblack@eecs.umich.edu bits(val, 7) ? " 7" : ""); 1875632Sgblack@eecs.umich.edu cascadeBits = val; 1885631Sgblack@eecs.umich.edu } else { 1895631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 1905632Sgblack@eecs.umich.edu cascadeBits = val & mask(3); 1915631Sgblack@eecs.umich.edu } 1925631Sgblack@eecs.umich.edu if (expectICW4) 1935631Sgblack@eecs.umich.edu initControlWord++; 1945631Sgblack@eecs.umich.edu else 1955631Sgblack@eecs.umich.edu initControlWord = 0; 1965631Sgblack@eecs.umich.edu break; 1975631Sgblack@eecs.umich.edu case 0x3: 1985631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 4.\n"); 1995631Sgblack@eecs.umich.edu if (bits(val, 4)) { 2005631Sgblack@eecs.umich.edu DPRINTF(I8259, "Special fully nested mode.\n"); 2015631Sgblack@eecs.umich.edu } else { 2025631Sgblack@eecs.umich.edu DPRINTF(I8259, "Not special fully nested mode.\n"); 2035631Sgblack@eecs.umich.edu } 2045631Sgblack@eecs.umich.edu if (bits(val, 3) == 0) { 2055631Sgblack@eecs.umich.edu DPRINTF(I8259, "Nonbuffered.\n"); 2065631Sgblack@eecs.umich.edu } else if (bits(val, 2) == 0) { 2075631Sgblack@eecs.umich.edu DPRINTF(I8259, "Buffered.\n"); 2085631Sgblack@eecs.umich.edu } else { 2095631Sgblack@eecs.umich.edu DPRINTF(I8259, "Unrecognized buffer mode.\n"); 2105631Sgblack@eecs.umich.edu } 2115688Sgblack@eecs.umich.edu autoEOI = bits(val, 1); 2125631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s End Of Interrupt.\n", 2135688Sgblack@eecs.umich.edu autoEOI ? "Automatic" : "Normal"); 2145688Sgblack@eecs.umich.edu 2155631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 2165631Sgblack@eecs.umich.edu initControlWord = 0; 2175631Sgblack@eecs.umich.edu break; 2185631Sgblack@eecs.umich.edu } 2195631Sgblack@eecs.umich.edu break; 2205631Sgblack@eecs.umich.edu } 2215630Sgblack@eecs.umich.edu return latency; 2225390SN/A} 2235630Sgblack@eecs.umich.edu 2245632Sgblack@eecs.umich.eduvoid 2255686Sgblack@eecs.umich.eduX86ISA::I8259::handleEOI(int line) 2265686Sgblack@eecs.umich.edu{ 2275686Sgblack@eecs.umich.edu ISR &= ~(1 << line); 2285686Sgblack@eecs.umich.edu // There may be an interrupt that was waiting which can 2295686Sgblack@eecs.umich.edu // now be sent. 2305686Sgblack@eecs.umich.edu if (IRR) 2315686Sgblack@eecs.umich.edu requestInterrupt(findMsbSet(IRR)); 2325686Sgblack@eecs.umich.edu} 2335686Sgblack@eecs.umich.edu 2345686Sgblack@eecs.umich.eduvoid 2355686Sgblack@eecs.umich.eduX86ISA::I8259::requestInterrupt(int line) 2365686Sgblack@eecs.umich.edu{ 2375686Sgblack@eecs.umich.edu if (bits(ISR, 7, line) == 0) { 2385686Sgblack@eecs.umich.edu if (output) { 2395686Sgblack@eecs.umich.edu DPRINTF(I8259, "Propogating interrupt.\n"); 2405686Sgblack@eecs.umich.edu output->signalInterrupt(); 2415686Sgblack@eecs.umich.edu } else { 2425686Sgblack@eecs.umich.edu warn("Received interrupt but didn't have " 2435686Sgblack@eecs.umich.edu "anyone to tell about it.\n"); 2445686Sgblack@eecs.umich.edu } 2455686Sgblack@eecs.umich.edu } 2465686Sgblack@eecs.umich.edu} 2475686Sgblack@eecs.umich.edu 2485686Sgblack@eecs.umich.eduvoid 2495632Sgblack@eecs.umich.eduX86ISA::I8259::signalInterrupt(int line) 2505632Sgblack@eecs.umich.edu{ 2515632Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt raised on line %d.\n", line); 2525657Sgblack@eecs.umich.edu if (line >= NumLines) 2535657Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2545657Sgblack@eecs.umich.edu line, NumLines - 1); 2555632Sgblack@eecs.umich.edu if (bits(IMR, line)) { 2565632Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was masked.\n", line); 2575634Sgblack@eecs.umich.edu } else { 2585657Sgblack@eecs.umich.edu IRR |= 1 << line; 2595686Sgblack@eecs.umich.edu requestInterrupt(line); 2605632Sgblack@eecs.umich.edu } 2615632Sgblack@eecs.umich.edu} 2625632Sgblack@eecs.umich.edu 2635657Sgblack@eecs.umich.eduint 2645657Sgblack@eecs.umich.eduX86ISA::I8259::getVector() 2655657Sgblack@eecs.umich.edu{ 2665657Sgblack@eecs.umich.edu /* 2675657Sgblack@eecs.umich.edu * This code only handles one slave. Since that's how the PC platform 2685657Sgblack@eecs.umich.edu * always uses the 8259 PIC, there shouldn't be any need for more. If 2695657Sgblack@eecs.umich.edu * there -is- a need for more for some reason, "slave" can become a 2705657Sgblack@eecs.umich.edu * vector of slaves. 2715657Sgblack@eecs.umich.edu */ 2725657Sgblack@eecs.umich.edu int line = findMsbSet(IRR); 2735657Sgblack@eecs.umich.edu IRR &= ~(1 << line); 2745657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 2755688Sgblack@eecs.umich.edu if (autoEOI) { 2765688Sgblack@eecs.umich.edu handleEOI(line); 2775688Sgblack@eecs.umich.edu } else { 2785688Sgblack@eecs.umich.edu ISR |= 1 << line; 2795688Sgblack@eecs.umich.edu } 2805657Sgblack@eecs.umich.edu if (slave && bits(cascadeBits, line)) { 2815657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt was from slave who will " 2825657Sgblack@eecs.umich.edu "provide the vector.\n"); 2835657Sgblack@eecs.umich.edu return slave->getVector(); 2845657Sgblack@eecs.umich.edu } 2855657Sgblack@eecs.umich.edu return line | vectorOffset; 2865657Sgblack@eecs.umich.edu} 2875657Sgblack@eecs.umich.edu 2885630Sgblack@eecs.umich.eduX86ISA::I8259 * 2895630Sgblack@eecs.umich.eduI8259Params::create() 2905630Sgblack@eecs.umich.edu{ 2915630Sgblack@eecs.umich.edu return new X86ISA::I8259(this); 2925630Sgblack@eecs.umich.edu} 293