i8259.cc revision 10905
15390SN/A/* 25390SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Gabe Black 295390SN/A */ 305390SN/A 315631Sgblack@eecs.umich.edu#include "base/bitfield.hh" 328232Snate@binkert.org#include "debug/I8259.hh" 335657Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 345630Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 355698Snate@binkert.org#include "mem/packet.hh" 365698Snate@binkert.org#include "mem/packet_access.hh" 375390SN/A 389808Sstever@gmail.comX86ISA::I8259::I8259(Params * p) 399808Sstever@gmail.com : BasicPioDevice(p, 2), IntDevice(this), 409808Sstever@gmail.com latency(p->pio_latency), output(p->output), 419808Sstever@gmail.com mode(p->mode), slave(p->slave), 429808Sstever@gmail.com IRR(0), ISR(0), IMR(0), 439808Sstever@gmail.com readIRR(true), initControlWord(0), autoEOI(false) 445657Sgblack@eecs.umich.edu{ 455827Sgblack@eecs.umich.edu for (int i = 0; i < NumLines; i++) 465827Sgblack@eecs.umich.edu pinStates[i] = false; 475657Sgblack@eecs.umich.edu} 485657Sgblack@eecs.umich.edu 495390SN/ATick 505390SN/AX86ISA::I8259::read(PacketPtr pkt) 515390SN/A{ 525631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 535631Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 545631Sgblack@eecs.umich.edu { 555631Sgblack@eecs.umich.edu case 0x0: 565631Sgblack@eecs.umich.edu if (readIRR) { 575631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 585631Sgblack@eecs.umich.edu pkt->set(IRR); 595631Sgblack@eecs.umich.edu } else { 605631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 615631Sgblack@eecs.umich.edu pkt->set(ISR); 625631Sgblack@eecs.umich.edu } 635631Sgblack@eecs.umich.edu break; 645631Sgblack@eecs.umich.edu case 0x1: 655631Sgblack@eecs.umich.edu DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 665631Sgblack@eecs.umich.edu pkt->set(IMR); 675631Sgblack@eecs.umich.edu break; 685631Sgblack@eecs.umich.edu } 695898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 705630Sgblack@eecs.umich.edu return latency; 715390SN/A} 725390SN/A 735390SN/ATick 745390SN/AX86ISA::I8259::write(PacketPtr pkt) 755390SN/A{ 765631Sgblack@eecs.umich.edu assert(pkt->getSize() == 1); 775631Sgblack@eecs.umich.edu uint8_t val = pkt->get<uint8_t>(); 785631Sgblack@eecs.umich.edu switch (pkt->getAddr() - pioAddr) { 795631Sgblack@eecs.umich.edu case 0x0: 805631Sgblack@eecs.umich.edu if (bits(val, 4)) { 815631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 1.\n"); 825631Sgblack@eecs.umich.edu IMR = 0; 835631Sgblack@eecs.umich.edu edgeTriggered = bits(val, 3); 845631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s triggered mode.\n", 855631Sgblack@eecs.umich.edu edgeTriggered ? "Edge" : "Level"); 865631Sgblack@eecs.umich.edu cascadeMode = !bits(val, 1); 875631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", 885631Sgblack@eecs.umich.edu cascadeMode ? "Cascade" : "Single"); 895631Sgblack@eecs.umich.edu expectICW4 = bits(val, 0); 905688Sgblack@eecs.umich.edu if (!expectICW4) { 915688Sgblack@eecs.umich.edu autoEOI = false; 925688Sgblack@eecs.umich.edu } 935631Sgblack@eecs.umich.edu initControlWord = 1; 945631Sgblack@eecs.umich.edu DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 955631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 0) { 965631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 2.\n"); 975631Sgblack@eecs.umich.edu switch (bits(val, 7, 5)) { 985631Sgblack@eecs.umich.edu case 0x0: 995631Sgblack@eecs.umich.edu DPRINTF(I8259, 1005631Sgblack@eecs.umich.edu "Subcommand: Rotate in auto-EOI mode (clear).\n"); 1015631Sgblack@eecs.umich.edu break; 1025631Sgblack@eecs.umich.edu case 0x1: 1035687Sgblack@eecs.umich.edu { 1045687Sgblack@eecs.umich.edu int line = findMsbSet(ISR); 1055687Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 1065687Sgblack@eecs.umich.edu line); 1075687Sgblack@eecs.umich.edu handleEOI(line); 1085687Sgblack@eecs.umich.edu } 1095631Sgblack@eecs.umich.edu break; 1105631Sgblack@eecs.umich.edu case 0x2: 1115631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: No operation.\n"); 1125631Sgblack@eecs.umich.edu break; 1135631Sgblack@eecs.umich.edu case 0x3: 1145686Sgblack@eecs.umich.edu { 1155686Sgblack@eecs.umich.edu int line = bits(val, 2, 0); 1165686Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 1175686Sgblack@eecs.umich.edu line); 1185686Sgblack@eecs.umich.edu handleEOI(line); 1195686Sgblack@eecs.umich.edu } 1205631Sgblack@eecs.umich.edu break; 1215631Sgblack@eecs.umich.edu case 0x4: 1225631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 1235631Sgblack@eecs.umich.edu break; 1245631Sgblack@eecs.umich.edu case 0x5: 1255631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 1265631Sgblack@eecs.umich.edu break; 1275631Sgblack@eecs.umich.edu case 0x6: 1285631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Set priority command.\n"); 1295631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1305631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1315631Sgblack@eecs.umich.edu break; 1325631Sgblack@eecs.umich.edu case 0x7: 1335631Sgblack@eecs.umich.edu DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 1345631Sgblack@eecs.umich.edu DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 1355631Sgblack@eecs.umich.edu bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 1365631Sgblack@eecs.umich.edu break; 1375631Sgblack@eecs.umich.edu } 1385631Sgblack@eecs.umich.edu } else if (bits(val, 4, 3) == 1) { 1395631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 3.\n"); 1405631Sgblack@eecs.umich.edu if (bits(val, 7)) { 1415631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s special mask mode.\n", 1425631Sgblack@eecs.umich.edu bits(val, 6) ? "Set" : "Clear"); 1435631Sgblack@eecs.umich.edu } 1445631Sgblack@eecs.umich.edu if (bits(val, 1)) { 1455631Sgblack@eecs.umich.edu readIRR = bits(val, 0); 1465631Sgblack@eecs.umich.edu DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 1475631Sgblack@eecs.umich.edu } 1485631Sgblack@eecs.umich.edu } 1495631Sgblack@eecs.umich.edu break; 1505631Sgblack@eecs.umich.edu case 0x1: 1515631Sgblack@eecs.umich.edu switch (initControlWord) { 1525631Sgblack@eecs.umich.edu case 0x0: 1535631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received operation command word 1.\n"); 1545631Sgblack@eecs.umich.edu DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 1555631Sgblack@eecs.umich.edu IMR = val; 1565631Sgblack@eecs.umich.edu break; 1575631Sgblack@eecs.umich.edu case 0x1: 1585631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 2.\n"); 1595656Sgblack@eecs.umich.edu vectorOffset = val & ~mask(3); 1605631Sgblack@eecs.umich.edu DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 1615656Sgblack@eecs.umich.edu vectorOffset, vectorOffset | mask(3)); 1625631Sgblack@eecs.umich.edu if (cascadeMode) { 1635631Sgblack@eecs.umich.edu initControlWord++; 1645631Sgblack@eecs.umich.edu } else { 1655632Sgblack@eecs.umich.edu cascadeBits = 0; 1665631Sgblack@eecs.umich.edu initControlWord = 0; 1675631Sgblack@eecs.umich.edu } 1685631Sgblack@eecs.umich.edu break; 1695631Sgblack@eecs.umich.edu case 0x2: 1705631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 3.\n"); 1715634Sgblack@eecs.umich.edu if (mode == Enums::I8259Master) { 1725631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 1735631Sgblack@eecs.umich.edu bits(val, 0) ? " 0" : "", 1745631Sgblack@eecs.umich.edu bits(val, 1) ? " 1" : "", 1755631Sgblack@eecs.umich.edu bits(val, 2) ? " 2" : "", 1765631Sgblack@eecs.umich.edu bits(val, 3) ? " 3" : "", 1775631Sgblack@eecs.umich.edu bits(val, 4) ? " 4" : "", 1785631Sgblack@eecs.umich.edu bits(val, 5) ? " 5" : "", 1795631Sgblack@eecs.umich.edu bits(val, 6) ? " 6" : "", 1805631Sgblack@eecs.umich.edu bits(val, 7) ? " 7" : ""); 1815632Sgblack@eecs.umich.edu cascadeBits = val; 1825631Sgblack@eecs.umich.edu } else { 1835631Sgblack@eecs.umich.edu DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 1845632Sgblack@eecs.umich.edu cascadeBits = val & mask(3); 1855631Sgblack@eecs.umich.edu } 1865631Sgblack@eecs.umich.edu if (expectICW4) 1875631Sgblack@eecs.umich.edu initControlWord++; 1885631Sgblack@eecs.umich.edu else 1895631Sgblack@eecs.umich.edu initControlWord = 0; 1905631Sgblack@eecs.umich.edu break; 1915631Sgblack@eecs.umich.edu case 0x3: 1925631Sgblack@eecs.umich.edu DPRINTF(I8259, "Received initialization command word 4.\n"); 1935631Sgblack@eecs.umich.edu if (bits(val, 4)) { 1945631Sgblack@eecs.umich.edu DPRINTF(I8259, "Special fully nested mode.\n"); 1955631Sgblack@eecs.umich.edu } else { 1965631Sgblack@eecs.umich.edu DPRINTF(I8259, "Not special fully nested mode.\n"); 1975631Sgblack@eecs.umich.edu } 1985631Sgblack@eecs.umich.edu if (bits(val, 3) == 0) { 1995631Sgblack@eecs.umich.edu DPRINTF(I8259, "Nonbuffered.\n"); 2005631Sgblack@eecs.umich.edu } else if (bits(val, 2) == 0) { 2015631Sgblack@eecs.umich.edu DPRINTF(I8259, "Buffered.\n"); 2025631Sgblack@eecs.umich.edu } else { 2035631Sgblack@eecs.umich.edu DPRINTF(I8259, "Unrecognized buffer mode.\n"); 2045631Sgblack@eecs.umich.edu } 2055688Sgblack@eecs.umich.edu autoEOI = bits(val, 1); 2065631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s End Of Interrupt.\n", 2075688Sgblack@eecs.umich.edu autoEOI ? "Automatic" : "Normal"); 2085688Sgblack@eecs.umich.edu 2095631Sgblack@eecs.umich.edu DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 2105631Sgblack@eecs.umich.edu initControlWord = 0; 2115631Sgblack@eecs.umich.edu break; 2125631Sgblack@eecs.umich.edu } 2135631Sgblack@eecs.umich.edu break; 2145631Sgblack@eecs.umich.edu } 2155898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 2165630Sgblack@eecs.umich.edu return latency; 2175390SN/A} 2185630Sgblack@eecs.umich.edu 2195632Sgblack@eecs.umich.eduvoid 2205686Sgblack@eecs.umich.eduX86ISA::I8259::handleEOI(int line) 2215686Sgblack@eecs.umich.edu{ 2225686Sgblack@eecs.umich.edu ISR &= ~(1 << line); 2235686Sgblack@eecs.umich.edu // There may be an interrupt that was waiting which can 2245686Sgblack@eecs.umich.edu // now be sent. 2255686Sgblack@eecs.umich.edu if (IRR) 2265686Sgblack@eecs.umich.edu requestInterrupt(findMsbSet(IRR)); 2275686Sgblack@eecs.umich.edu} 2285686Sgblack@eecs.umich.edu 2295686Sgblack@eecs.umich.eduvoid 2305686Sgblack@eecs.umich.eduX86ISA::I8259::requestInterrupt(int line) 2315686Sgblack@eecs.umich.edu{ 2325686Sgblack@eecs.umich.edu if (bits(ISR, 7, line) == 0) { 2335686Sgblack@eecs.umich.edu if (output) { 2345686Sgblack@eecs.umich.edu DPRINTF(I8259, "Propogating interrupt.\n"); 2355827Sgblack@eecs.umich.edu output->raise(); 2365827Sgblack@eecs.umich.edu //XXX This is a hack. 2375827Sgblack@eecs.umich.edu output->lower(); 2385686Sgblack@eecs.umich.edu } else { 2395686Sgblack@eecs.umich.edu warn("Received interrupt but didn't have " 2405686Sgblack@eecs.umich.edu "anyone to tell about it.\n"); 2415686Sgblack@eecs.umich.edu } 2425686Sgblack@eecs.umich.edu } 2435686Sgblack@eecs.umich.edu} 2445686Sgblack@eecs.umich.edu 2455686Sgblack@eecs.umich.eduvoid 2465632Sgblack@eecs.umich.eduX86ISA::I8259::signalInterrupt(int line) 2475632Sgblack@eecs.umich.edu{ 2485830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt requested for line %d.\n", line); 2495657Sgblack@eecs.umich.edu if (line >= NumLines) 2505657Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2515657Sgblack@eecs.umich.edu line, NumLines - 1); 2525632Sgblack@eecs.umich.edu if (bits(IMR, line)) { 2535632Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was masked.\n", line); 2545634Sgblack@eecs.umich.edu } else { 2555657Sgblack@eecs.umich.edu IRR |= 1 << line; 2565686Sgblack@eecs.umich.edu requestInterrupt(line); 2575632Sgblack@eecs.umich.edu } 2585632Sgblack@eecs.umich.edu} 2595632Sgblack@eecs.umich.edu 2605827Sgblack@eecs.umich.eduvoid 2615827Sgblack@eecs.umich.eduX86ISA::I8259::raiseInterruptPin(int number) 2625827Sgblack@eecs.umich.edu{ 2635830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number); 2645827Sgblack@eecs.umich.edu if (number >= NumLines) 2655827Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2665827Sgblack@eecs.umich.edu number, NumLines - 1); 2675827Sgblack@eecs.umich.edu if (!pinStates[number]) 2685827Sgblack@eecs.umich.edu signalInterrupt(number); 2695827Sgblack@eecs.umich.edu pinStates[number] = true; 2705827Sgblack@eecs.umich.edu} 2715827Sgblack@eecs.umich.edu 2725827Sgblack@eecs.umich.eduvoid 2735827Sgblack@eecs.umich.eduX86ISA::I8259::lowerInterruptPin(int number) 2745827Sgblack@eecs.umich.edu{ 2755830Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number); 2765827Sgblack@eecs.umich.edu if (number >= NumLines) 2775827Sgblack@eecs.umich.edu fatal("Line number %d doesn't exist. The max is %d.\n", 2785827Sgblack@eecs.umich.edu number, NumLines - 1); 2795827Sgblack@eecs.umich.edu pinStates[number] = false; 2805827Sgblack@eecs.umich.edu} 2815827Sgblack@eecs.umich.edu 2825657Sgblack@eecs.umich.eduint 2835657Sgblack@eecs.umich.eduX86ISA::I8259::getVector() 2845657Sgblack@eecs.umich.edu{ 2855657Sgblack@eecs.umich.edu /* 2865657Sgblack@eecs.umich.edu * This code only handles one slave. Since that's how the PC platform 2875657Sgblack@eecs.umich.edu * always uses the 8259 PIC, there shouldn't be any need for more. If 2885657Sgblack@eecs.umich.edu * there -is- a need for more for some reason, "slave" can become a 2895657Sgblack@eecs.umich.edu * vector of slaves. 2905657Sgblack@eecs.umich.edu */ 2915657Sgblack@eecs.umich.edu int line = findMsbSet(IRR); 2925657Sgblack@eecs.umich.edu IRR &= ~(1 << line); 2935657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 2945688Sgblack@eecs.umich.edu if (autoEOI) { 2955688Sgblack@eecs.umich.edu handleEOI(line); 2965688Sgblack@eecs.umich.edu } else { 2975688Sgblack@eecs.umich.edu ISR |= 1 << line; 2985688Sgblack@eecs.umich.edu } 2995657Sgblack@eecs.umich.edu if (slave && bits(cascadeBits, line)) { 3005657Sgblack@eecs.umich.edu DPRINTF(I8259, "Interrupt was from slave who will " 3015657Sgblack@eecs.umich.edu "provide the vector.\n"); 3025657Sgblack@eecs.umich.edu return slave->getVector(); 3035657Sgblack@eecs.umich.edu } 3045657Sgblack@eecs.umich.edu return line | vectorOffset; 3055657Sgblack@eecs.umich.edu} 3065657Sgblack@eecs.umich.edu 3077903Shestness@cs.utexas.eduvoid 30810905Sandreas.sandberg@arm.comX86ISA::I8259::serialize(CheckpointOut &cp) const 3097903Shestness@cs.utexas.edu{ 3107903Shestness@cs.utexas.edu SERIALIZE_ARRAY(pinStates, NumLines); 3117903Shestness@cs.utexas.edu SERIALIZE_ENUM(mode); 3127903Shestness@cs.utexas.edu SERIALIZE_SCALAR(IRR); 3137903Shestness@cs.utexas.edu SERIALIZE_SCALAR(ISR); 3147903Shestness@cs.utexas.edu SERIALIZE_SCALAR(IMR); 3157903Shestness@cs.utexas.edu SERIALIZE_SCALAR(vectorOffset); 3167903Shestness@cs.utexas.edu SERIALIZE_SCALAR(cascadeMode); 3177903Shestness@cs.utexas.edu SERIALIZE_SCALAR(cascadeBits); 3187903Shestness@cs.utexas.edu SERIALIZE_SCALAR(edgeTriggered); 3197903Shestness@cs.utexas.edu SERIALIZE_SCALAR(readIRR); 3207903Shestness@cs.utexas.edu SERIALIZE_SCALAR(expectICW4); 3217903Shestness@cs.utexas.edu SERIALIZE_SCALAR(initControlWord); 3227903Shestness@cs.utexas.edu SERIALIZE_SCALAR(autoEOI); 3237903Shestness@cs.utexas.edu} 3247903Shestness@cs.utexas.edu 3257903Shestness@cs.utexas.eduvoid 32610905Sandreas.sandberg@arm.comX86ISA::I8259::unserialize(CheckpointIn &cp) 3277903Shestness@cs.utexas.edu{ 3287903Shestness@cs.utexas.edu UNSERIALIZE_ARRAY(pinStates, NumLines); 3297903Shestness@cs.utexas.edu UNSERIALIZE_ENUM(mode); 3307903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IRR); 3317903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(ISR); 3327903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(IMR); 3337903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(vectorOffset); 3347903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(cascadeMode); 3357903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(cascadeBits); 3367903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(edgeTriggered); 3377903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(readIRR); 3387903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(expectICW4); 3397903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(initControlWord); 3407903Shestness@cs.utexas.edu UNSERIALIZE_SCALAR(autoEOI); 3417903Shestness@cs.utexas.edu} 3427903Shestness@cs.utexas.edu 3435630Sgblack@eecs.umich.eduX86ISA::I8259 * 3445630Sgblack@eecs.umich.eduI8259Params::create() 3455630Sgblack@eecs.umich.edu{ 3465630Sgblack@eecs.umich.edu return new X86ISA::I8259(this); 3475630Sgblack@eecs.umich.edu} 348