i82094aa.cc revision 9808:13ffc0066b76 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/interrupts.hh"
32#include "arch/x86/intmessage.hh"
33#include "cpu/base.hh"
34#include "debug/I82094AA.hh"
35#include "dev/x86/i82094aa.hh"
36#include "dev/x86/i8259.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/system.hh"
40
41X86ISA::I82094AA::I82094AA(Params *p)
42    : BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
43      extIntPic(p->external_int_pic), lowestPriorityOffset(0)
44{
45    // This assumes there's only one I/O APIC in the system and since the apic
46    // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
47    // be less than 0xff
48
49    assert(p->apic_id < 0xff);
50    initialApicId = id = p->apic_id;
51    arbId = id;
52    regSel = 0;
53    RedirTableEntry entry = 0;
54    entry.mask = 1;
55    for (int i = 0; i < TableSize; i++) {
56        redirTable[i] = entry;
57        pinStates[i] = false;
58    }
59}
60
61void
62X86ISA::I82094AA::init()
63{
64    // The io apic must register its address ranges on both its pio port
65    // via the piodevice init() function and its int port that it inherited
66    // from IntDevice.  Note IntDevice is not a SimObject itself.
67
68    BasicPioDevice::init();
69    IntDevice::init();
70}
71
72BaseMasterPort &
73X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
74{
75    if (if_name == "int_master")
76        return intMasterPort;
77    return BasicPioDevice::getMasterPort(if_name, idx);
78}
79
80AddrRangeList
81X86ISA::I82094AA::getIntAddrRange() const
82{
83    AddrRangeList ranges;
84    ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
85                             x86InterruptAddress(initialApicId, 0) +
86                             PhysAddrAPICRangeSize));
87    return ranges;
88}
89
90Tick
91X86ISA::I82094AA::read(PacketPtr pkt)
92{
93    assert(pkt->getSize() == 4);
94    Addr offset = pkt->getAddr() - pioAddr;
95    switch(offset) {
96      case 0:
97        pkt->set<uint32_t>(regSel);
98        break;
99      case 16:
100        pkt->set<uint32_t>(readReg(regSel));
101        break;
102      default:
103        panic("Illegal read from I/O APIC.\n");
104    }
105    pkt->makeAtomicResponse();
106    return pioDelay;
107}
108
109Tick
110X86ISA::I82094AA::write(PacketPtr pkt)
111{
112    assert(pkt->getSize() == 4);
113    Addr offset = pkt->getAddr() - pioAddr;
114    switch(offset) {
115      case 0:
116        regSel = pkt->get<uint32_t>();
117        break;
118      case 16:
119        writeReg(regSel, pkt->get<uint32_t>());
120        break;
121      default:
122        panic("Illegal write to I/O APIC.\n");
123    }
124    pkt->makeAtomicResponse();
125    return pioDelay;
126}
127
128void
129X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
130{
131    if (offset == 0x0) {
132        id = bits(value, 31, 24);
133    } else if (offset == 0x1) {
134        // The IOAPICVER register is read only.
135    } else if (offset == 0x2) {
136        arbId = bits(value, 31, 24);
137    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
138        int index = (offset - 0x10) / 2;
139        if (offset % 2) {
140            redirTable[index].topDW = value;
141            redirTable[index].topReserved = 0;
142        } else {
143            redirTable[index].bottomDW = value;
144            redirTable[index].bottomReserved = 0;
145        }
146    } else {
147        warn("Access to undefined I/O APIC register %#x.\n", offset);
148    }
149    DPRINTF(I82094AA,
150            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
151}
152
153uint32_t
154X86ISA::I82094AA::readReg(uint8_t offset)
155{
156    uint32_t result = 0;
157    if (offset == 0x0) {
158        result = id << 24;
159    } else if (offset == 0x1) {
160        result = ((TableSize - 1) << 16) | APICVersion;
161    } else if (offset == 0x2) {
162        result = arbId << 24;
163    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
164        int index = (offset - 0x10) / 2;
165        if (offset % 2) {
166            result = redirTable[index].topDW;
167        } else {
168            result = redirTable[index].bottomDW;
169        }
170    } else {
171        warn("Access to undefined I/O APIC register %#x.\n", offset);
172    }
173    DPRINTF(I82094AA,
174            "Read %#x from I/O APIC register %#x.\n", result, offset);
175    return result;
176}
177
178void
179X86ISA::I82094AA::signalInterrupt(int line)
180{
181    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
182    assert(line < TableSize);
183    RedirTableEntry entry = redirTable[line];
184    if (entry.mask) {
185        DPRINTF(I82094AA, "Entry was masked.\n");
186        return;
187    } else {
188        TriggerIntMessage message = 0;
189        message.destination = entry.dest;
190        if (entry.deliveryMode == DeliveryMode::ExtInt) {
191            assert(extIntPic);
192            message.vector = extIntPic->getVector();
193        } else {
194            message.vector = entry.vector;
195        }
196        message.deliveryMode = entry.deliveryMode;
197        message.destMode = entry.destMode;
198        message.level = entry.polarity;
199        message.trigger = entry.trigger;
200        ApicList apics;
201        int numContexts = sys->numContexts();
202        if (message.destMode == 0) {
203            if (message.deliveryMode == DeliveryMode::LowestPriority) {
204                panic("Lowest priority delivery mode from the "
205                        "IO APIC aren't supported in physical "
206                        "destination mode.\n");
207            }
208            if (message.destination == 0xFF) {
209                for (int i = 0; i < numContexts; i++) {
210                    apics.push_back(i);
211                }
212            } else {
213                apics.push_back(message.destination);
214            }
215        } else {
216            for (int i = 0; i < numContexts; i++) {
217                Interrupts *localApic = sys->getThreadContext(i)->
218                    getCpuPtr()->getInterruptController();
219                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
220                        message.destination) {
221                    apics.push_back(localApic->getInitialApicId());
222                }
223            }
224            if (message.deliveryMode == DeliveryMode::LowestPriority &&
225                    apics.size()) {
226                // The manual seems to suggest that the chipset just does
227                // something reasonable for these instead of actually using
228                // state from the local APIC. We'll just rotate an offset
229                // through the set of APICs selected above.
230                uint64_t modOffset = lowestPriorityOffset % apics.size();
231                lowestPriorityOffset++;
232                ApicList::iterator apicIt = apics.begin();
233                while (modOffset--) {
234                    apicIt++;
235                    assert(apicIt != apics.end());
236                }
237                int selected = *apicIt;
238                apics.clear();
239                apics.push_back(selected);
240            }
241        }
242        intMasterPort.sendMessage(apics, message, sys->isTimingMode());
243    }
244}
245
246void
247X86ISA::I82094AA::raiseInterruptPin(int number)
248{
249    assert(number < TableSize);
250    if (!pinStates[number])
251        signalInterrupt(number);
252    pinStates[number] = true;
253}
254
255void
256X86ISA::I82094AA::lowerInterruptPin(int number)
257{
258    assert(number < TableSize);
259    pinStates[number] = false;
260}
261
262void
263X86ISA::I82094AA::serialize(std::ostream &os)
264{
265    uint64_t* redirTableArray = (uint64_t*)redirTable;
266    SERIALIZE_SCALAR(regSel);
267    SERIALIZE_SCALAR(initialApicId);
268    SERIALIZE_SCALAR(id);
269    SERIALIZE_SCALAR(arbId);
270    SERIALIZE_SCALAR(lowestPriorityOffset);
271    SERIALIZE_ARRAY(redirTableArray, TableSize);
272    SERIALIZE_ARRAY(pinStates, TableSize);
273}
274
275void
276X86ISA::I82094AA::unserialize(Checkpoint *cp, const std::string &section)
277{
278    uint64_t redirTableArray[TableSize];
279    UNSERIALIZE_SCALAR(regSel);
280    UNSERIALIZE_SCALAR(initialApicId);
281    UNSERIALIZE_SCALAR(id);
282    UNSERIALIZE_SCALAR(arbId);
283    UNSERIALIZE_SCALAR(lowestPriorityOffset);
284    UNSERIALIZE_ARRAY(redirTableArray, TableSize);
285    UNSERIALIZE_ARRAY(pinStates, TableSize);
286    for (int i = 0; i < TableSize; i++) {
287        redirTable[i] = (RedirTableEntry)redirTableArray[i];
288    }
289}
290
291X86ISA::I82094AA *
292I82094AAParams::create()
293{
294    return new X86ISA::I82094AA(this);
295}
296