i82094aa.cc revision 9807:63d7362bbdf2 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/interrupts.hh"
32#include "arch/x86/intmessage.hh"
33#include "cpu/base.hh"
34#include "debug/I82094AA.hh"
35#include "dev/x86/i82094aa.hh"
36#include "dev/x86/i8259.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/system.hh"
40
41X86ISA::I82094AA::I82094AA(Params *p)
42    : BasicPioDevice(p), IntDevice(this, p->int_latency),
43      extIntPic(p->external_int_pic), lowestPriorityOffset(0)
44{
45    // This assumes there's only one I/O APIC in the system and since the apic
46    // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
47    // be less than 0xff
48
49    assert(p->apic_id < 0xff);
50    initialApicId = id = p->apic_id;
51    arbId = id;
52    regSel = 0;
53    RedirTableEntry entry = 0;
54    entry.mask = 1;
55    for (int i = 0; i < TableSize; i++) {
56        redirTable[i] = entry;
57        pinStates[i] = false;
58    }
59
60    pioSize = 20;
61}
62
63void
64X86ISA::I82094AA::init()
65{
66    // The io apic must register its address ranges on both its pio port
67    // via the piodevice init() function and its int port that it inherited
68    // from IntDevice.  Note IntDevice is not a SimObject itself.
69
70    BasicPioDevice::init();
71    IntDevice::init();
72}
73
74BaseMasterPort &
75X86ISA::I82094AA::getMasterPort(const std::string &if_name, PortID idx)
76{
77    if (if_name == "int_master")
78        return intMasterPort;
79    return BasicPioDevice::getMasterPort(if_name, idx);
80}
81
82AddrRangeList
83X86ISA::I82094AA::getIntAddrRange() const
84{
85    AddrRangeList ranges;
86    ranges.push_back(RangeEx(x86InterruptAddress(initialApicId, 0),
87                             x86InterruptAddress(initialApicId, 0) +
88                             PhysAddrAPICRangeSize));
89    return ranges;
90}
91
92Tick
93X86ISA::I82094AA::read(PacketPtr pkt)
94{
95    assert(pkt->getSize() == 4);
96    Addr offset = pkt->getAddr() - pioAddr;
97    switch(offset) {
98      case 0:
99        pkt->set<uint32_t>(regSel);
100        break;
101      case 16:
102        pkt->set<uint32_t>(readReg(regSel));
103        break;
104      default:
105        panic("Illegal read from I/O APIC.\n");
106    }
107    pkt->makeAtomicResponse();
108    return pioDelay;
109}
110
111Tick
112X86ISA::I82094AA::write(PacketPtr pkt)
113{
114    assert(pkt->getSize() == 4);
115    Addr offset = pkt->getAddr() - pioAddr;
116    switch(offset) {
117      case 0:
118        regSel = pkt->get<uint32_t>();
119        break;
120      case 16:
121        writeReg(regSel, pkt->get<uint32_t>());
122        break;
123      default:
124        panic("Illegal write to I/O APIC.\n");
125    }
126    pkt->makeAtomicResponse();
127    return pioDelay;
128}
129
130void
131X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
132{
133    if (offset == 0x0) {
134        id = bits(value, 31, 24);
135    } else if (offset == 0x1) {
136        // The IOAPICVER register is read only.
137    } else if (offset == 0x2) {
138        arbId = bits(value, 31, 24);
139    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
140        int index = (offset - 0x10) / 2;
141        if (offset % 2) {
142            redirTable[index].topDW = value;
143            redirTable[index].topReserved = 0;
144        } else {
145            redirTable[index].bottomDW = value;
146            redirTable[index].bottomReserved = 0;
147        }
148    } else {
149        warn("Access to undefined I/O APIC register %#x.\n", offset);
150    }
151    DPRINTF(I82094AA,
152            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
153}
154
155uint32_t
156X86ISA::I82094AA::readReg(uint8_t offset)
157{
158    uint32_t result = 0;
159    if (offset == 0x0) {
160        result = id << 24;
161    } else if (offset == 0x1) {
162        result = ((TableSize - 1) << 16) | APICVersion;
163    } else if (offset == 0x2) {
164        result = arbId << 24;
165    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
166        int index = (offset - 0x10) / 2;
167        if (offset % 2) {
168            result = redirTable[index].topDW;
169        } else {
170            result = redirTable[index].bottomDW;
171        }
172    } else {
173        warn("Access to undefined I/O APIC register %#x.\n", offset);
174    }
175    DPRINTF(I82094AA,
176            "Read %#x from I/O APIC register %#x.\n", result, offset);
177    return result;
178}
179
180void
181X86ISA::I82094AA::signalInterrupt(int line)
182{
183    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
184    assert(line < TableSize);
185    RedirTableEntry entry = redirTable[line];
186    if (entry.mask) {
187        DPRINTF(I82094AA, "Entry was masked.\n");
188        return;
189    } else {
190        TriggerIntMessage message = 0;
191        message.destination = entry.dest;
192        if (entry.deliveryMode == DeliveryMode::ExtInt) {
193            assert(extIntPic);
194            message.vector = extIntPic->getVector();
195        } else {
196            message.vector = entry.vector;
197        }
198        message.deliveryMode = entry.deliveryMode;
199        message.destMode = entry.destMode;
200        message.level = entry.polarity;
201        message.trigger = entry.trigger;
202        ApicList apics;
203        int numContexts = sys->numContexts();
204        if (message.destMode == 0) {
205            if (message.deliveryMode == DeliveryMode::LowestPriority) {
206                panic("Lowest priority delivery mode from the "
207                        "IO APIC aren't supported in physical "
208                        "destination mode.\n");
209            }
210            if (message.destination == 0xFF) {
211                for (int i = 0; i < numContexts; i++) {
212                    apics.push_back(i);
213                }
214            } else {
215                apics.push_back(message.destination);
216            }
217        } else {
218            for (int i = 0; i < numContexts; i++) {
219                Interrupts *localApic = sys->getThreadContext(i)->
220                    getCpuPtr()->getInterruptController();
221                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
222                        message.destination) {
223                    apics.push_back(localApic->getInitialApicId());
224                }
225            }
226            if (message.deliveryMode == DeliveryMode::LowestPriority &&
227                    apics.size()) {
228                // The manual seems to suggest that the chipset just does
229                // something reasonable for these instead of actually using
230                // state from the local APIC. We'll just rotate an offset
231                // through the set of APICs selected above.
232                uint64_t modOffset = lowestPriorityOffset % apics.size();
233                lowestPriorityOffset++;
234                ApicList::iterator apicIt = apics.begin();
235                while (modOffset--) {
236                    apicIt++;
237                    assert(apicIt != apics.end());
238                }
239                int selected = *apicIt;
240                apics.clear();
241                apics.push_back(selected);
242            }
243        }
244        intMasterPort.sendMessage(apics, message, sys->isTimingMode());
245    }
246}
247
248void
249X86ISA::I82094AA::raiseInterruptPin(int number)
250{
251    assert(number < TableSize);
252    if (!pinStates[number])
253        signalInterrupt(number);
254    pinStates[number] = true;
255}
256
257void
258X86ISA::I82094AA::lowerInterruptPin(int number)
259{
260    assert(number < TableSize);
261    pinStates[number] = false;
262}
263
264void
265X86ISA::I82094AA::serialize(std::ostream &os)
266{
267    uint64_t* redirTableArray = (uint64_t*)redirTable;
268    SERIALIZE_SCALAR(regSel);
269    SERIALIZE_SCALAR(initialApicId);
270    SERIALIZE_SCALAR(id);
271    SERIALIZE_SCALAR(arbId);
272    SERIALIZE_SCALAR(lowestPriorityOffset);
273    SERIALIZE_ARRAY(redirTableArray, TableSize);
274    SERIALIZE_ARRAY(pinStates, TableSize);
275}
276
277void
278X86ISA::I82094AA::unserialize(Checkpoint *cp, const std::string &section)
279{
280    uint64_t redirTableArray[TableSize];
281    UNSERIALIZE_SCALAR(regSel);
282    UNSERIALIZE_SCALAR(initialApicId);
283    UNSERIALIZE_SCALAR(id);
284    UNSERIALIZE_SCALAR(arbId);
285    UNSERIALIZE_SCALAR(lowestPriorityOffset);
286    UNSERIALIZE_ARRAY(redirTableArray, TableSize);
287    UNSERIALIZE_ARRAY(pinStates, TableSize);
288    for (int i = 0; i < TableSize; i++) {
289        redirTable[i] = (RedirTableEntry)redirTableArray[i];
290    }
291}
292
293X86ISA::I82094AA *
294I82094AAParams::create()
295{
296    return new X86ISA::I82094AA(this);
297}
298