i82094aa.cc revision 9524 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/interrupts.hh"
32#include "arch/x86/intmessage.hh"
33#include "cpu/base.hh"
34#include "debug/I82094AA.hh"
35#include "dev/x86/i82094aa.hh"
36#include "dev/x86/i8259.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "sim/system.hh"
40
41X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
42    IntDev(this, p->int_latency),
43    latency(p->pio_latency), pioAddr(p->pio_addr),
44    extIntPic(p->external_int_pic), lowestPriorityOffset(0)
45{
46    // This assumes there's only one I/O APIC in the system and since the apic
47    // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
48    // be less than 0xff
49
50    assert(p->apic_id < 0xff);
51    initialApicId = id = p->apic_id;
52    arbId = id;
53    regSel = 0;
54    RedirTableEntry entry = 0;
55    entry.mask = 1;
56    for (int i = 0; i < TableSize; i++) {
57        redirTable[i] = entry;
58        pinStates[i] = false;
59    }
60}
61
62void
63X86ISA::I82094AA::init()
64{
65    // The io apic must register its address ranges on both its pio port
66    // via the piodevice init() function and its int port that it inherited
67    // from IntDev.  Note IntDev is not a SimObject itself.
68
69    PioDevice::init();
70    IntDev::init();
71}
72
73Tick
74X86ISA::I82094AA::read(PacketPtr pkt)
75{
76    assert(pkt->getSize() == 4);
77    Addr offset = pkt->getAddr() - pioAddr;
78    switch(offset) {
79      case 0:
80        pkt->set<uint32_t>(regSel);
81        break;
82      case 16:
83        pkt->set<uint32_t>(readReg(regSel));
84        break;
85      default:
86        panic("Illegal read from I/O APIC.\n");
87    }
88    pkt->makeAtomicResponse();
89    return latency;
90}
91
92Tick
93X86ISA::I82094AA::write(PacketPtr pkt)
94{
95    assert(pkt->getSize() == 4);
96    Addr offset = pkt->getAddr() - pioAddr;
97    switch(offset) {
98      case 0:
99        regSel = pkt->get<uint32_t>();
100        break;
101      case 16:
102        writeReg(regSel, pkt->get<uint32_t>());
103        break;
104      default:
105        panic("Illegal write to I/O APIC.\n");
106    }
107    pkt->makeAtomicResponse();
108    return latency;
109}
110
111void
112X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
113{
114    if (offset == 0x0) {
115        id = bits(value, 31, 24);
116    } else if (offset == 0x1) {
117        // The IOAPICVER register is read only.
118    } else if (offset == 0x2) {
119        arbId = bits(value, 31, 24);
120    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
121        int index = (offset - 0x10) / 2;
122        if (offset % 2) {
123            redirTable[index].topDW = value;
124            redirTable[index].topReserved = 0;
125        } else {
126            redirTable[index].bottomDW = value;
127            redirTable[index].bottomReserved = 0;
128        }
129    } else {
130        warn("Access to undefined I/O APIC register %#x.\n", offset);
131    }
132    DPRINTF(I82094AA,
133            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
134}
135
136uint32_t
137X86ISA::I82094AA::readReg(uint8_t offset)
138{
139    uint32_t result = 0;
140    if (offset == 0x0) {
141        result = id << 24;
142    } else if (offset == 0x1) {
143        result = ((TableSize - 1) << 16) | APICVersion;
144    } else if (offset == 0x2) {
145        result = arbId << 24;
146    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
147        int index = (offset - 0x10) / 2;
148        if (offset % 2) {
149            result = redirTable[index].topDW;
150        } else {
151            result = redirTable[index].bottomDW;
152        }
153    } else {
154        warn("Access to undefined I/O APIC register %#x.\n", offset);
155    }
156    DPRINTF(I82094AA,
157            "Read %#x from I/O APIC register %#x.\n", result, offset);
158    return result;
159}
160
161void
162X86ISA::I82094AA::signalInterrupt(int line)
163{
164    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
165    assert(line < TableSize);
166    RedirTableEntry entry = redirTable[line];
167    if (entry.mask) {
168        DPRINTF(I82094AA, "Entry was masked.\n");
169        return;
170    } else {
171        TriggerIntMessage message = 0;
172        message.destination = entry.dest;
173        if (entry.deliveryMode == DeliveryMode::ExtInt) {
174            assert(extIntPic);
175            message.vector = extIntPic->getVector();
176        } else {
177            message.vector = entry.vector;
178        }
179        message.deliveryMode = entry.deliveryMode;
180        message.destMode = entry.destMode;
181        message.level = entry.polarity;
182        message.trigger = entry.trigger;
183        ApicList apics;
184        int numContexts = sys->numContexts();
185        if (message.destMode == 0) {
186            if (message.deliveryMode == DeliveryMode::LowestPriority) {
187                panic("Lowest priority delivery mode from the "
188                        "IO APIC aren't supported in physical "
189                        "destination mode.\n");
190            }
191            if (message.destination == 0xFF) {
192                for (int i = 0; i < numContexts; i++) {
193                    apics.push_back(i);
194                }
195            } else {
196                apics.push_back(message.destination);
197            }
198        } else {
199            for (int i = 0; i < numContexts; i++) {
200                Interrupts *localApic = sys->getThreadContext(i)->
201                    getCpuPtr()->getInterruptController();
202                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
203                        message.destination) {
204                    apics.push_back(localApic->getInitialApicId());
205                }
206            }
207            if (message.deliveryMode == DeliveryMode::LowestPriority &&
208                    apics.size()) {
209                // The manual seems to suggest that the chipset just does
210                // something reasonable for these instead of actually using
211                // state from the local APIC. We'll just rotate an offset
212                // through the set of APICs selected above.
213                uint64_t modOffset = lowestPriorityOffset % apics.size();
214                lowestPriorityOffset++;
215                ApicList::iterator apicIt = apics.begin();
216                while (modOffset--) {
217                    apicIt++;
218                    assert(apicIt != apics.end());
219                }
220                int selected = *apicIt;
221                apics.clear();
222                apics.push_back(selected);
223            }
224        }
225        intMasterPort.sendMessage(apics, message, sys->isTimingMode());
226    }
227}
228
229void
230X86ISA::I82094AA::raiseInterruptPin(int number)
231{
232    assert(number < TableSize);
233    if (!pinStates[number])
234        signalInterrupt(number);
235    pinStates[number] = true;
236}
237
238void
239X86ISA::I82094AA::lowerInterruptPin(int number)
240{
241    assert(number < TableSize);
242    pinStates[number] = false;
243}
244
245void
246X86ISA::I82094AA::serialize(std::ostream &os)
247{
248    uint64_t* redirTableArray = (uint64_t*)redirTable;
249    SERIALIZE_SCALAR(regSel);
250    SERIALIZE_SCALAR(initialApicId);
251    SERIALIZE_SCALAR(id);
252    SERIALIZE_SCALAR(arbId);
253    SERIALIZE_SCALAR(lowestPriorityOffset);
254    SERIALIZE_ARRAY(redirTableArray, TableSize);
255    SERIALIZE_ARRAY(pinStates, TableSize);
256}
257
258void
259X86ISA::I82094AA::unserialize(Checkpoint *cp, const std::string &section)
260{
261    uint64_t redirTableArray[TableSize];
262    UNSERIALIZE_SCALAR(regSel);
263    UNSERIALIZE_SCALAR(initialApicId);
264    UNSERIALIZE_SCALAR(id);
265    UNSERIALIZE_SCALAR(arbId);
266    UNSERIALIZE_SCALAR(lowestPriorityOffset);
267    UNSERIALIZE_ARRAY(redirTableArray, TableSize);
268    UNSERIALIZE_ARRAY(pinStates, TableSize);
269    for (int i = 0; i < TableSize; i++) {
270        redirTable[i] = (RedirTableEntry)redirTableArray[i];
271    }
272}
273
274X86ISA::I82094AA *
275I82094AAParams::create()
276{
277    return new X86ISA::I82094AA(this);
278}
279