i82094aa.cc revision 8232:b28d06a175be 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "arch/x86/interrupts.hh"
32#include "arch/x86/intmessage.hh"
33#include "debug/I82094AA.hh"
34#include "dev/x86/i82094aa.hh"
35#include "dev/x86/i8259.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38#include "sim/system.hh"
39
40X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p),
41    IntDev(this, p->int_latency),
42    latency(p->pio_latency), pioAddr(p->pio_addr),
43    extIntPic(p->external_int_pic), lowestPriorityOffset(0)
44{
45    // This assumes there's only one I/O APIC in the system and since the apic
46    // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
47    // be less than 0xff
48
49    assert(p->apic_id < 0xff);
50    initialApicId = id = p->apic_id;
51    arbId = id;
52    regSel = 0;
53    RedirTableEntry entry = 0;
54    entry.mask = 1;
55    for (int i = 0; i < TableSize; i++) {
56        redirTable[i] = entry;
57        pinStates[i] = false;
58    }
59}
60
61void
62X86ISA::I82094AA::init()
63{
64    // The io apic must register its address ranges on both its pio port
65    // via the piodevice init() function and its int port that it inherited
66    // from IntDev.  Note IntDev is not a SimObject itself.
67
68    PioDevice::init();
69    IntDev::init();
70}
71
72Tick
73X86ISA::I82094AA::read(PacketPtr pkt)
74{
75    assert(pkt->getSize() == 4);
76    Addr offset = pkt->getAddr() - pioAddr;
77    switch(offset) {
78      case 0:
79        pkt->set<uint32_t>(regSel);
80        break;
81      case 16:
82        pkt->set<uint32_t>(readReg(regSel));
83        break;
84      default:
85        panic("Illegal read from I/O APIC.\n");
86    }
87    pkt->makeAtomicResponse();
88    return latency;
89}
90
91Tick
92X86ISA::I82094AA::write(PacketPtr pkt)
93{
94    assert(pkt->getSize() == 4);
95    Addr offset = pkt->getAddr() - pioAddr;
96    switch(offset) {
97      case 0:
98        regSel = pkt->get<uint32_t>();
99        break;
100      case 16:
101        writeReg(regSel, pkt->get<uint32_t>());
102        break;
103      default:
104        panic("Illegal write to I/O APIC.\n");
105    }
106    pkt->makeAtomicResponse();
107    return latency;
108}
109
110void
111X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
112{
113    if (offset == 0x0) {
114        id = bits(value, 31, 24);
115    } else if (offset == 0x1) {
116        // The IOAPICVER register is read only.
117    } else if (offset == 0x2) {
118        arbId = bits(value, 31, 24);
119    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
120        int index = (offset - 0x10) / 2;
121        if (offset % 2) {
122            redirTable[index].topDW = value;
123            redirTable[index].topReserved = 0;
124        } else {
125            redirTable[index].bottomDW = value;
126            redirTable[index].bottomReserved = 0;
127        }
128    } else {
129        warn("Access to undefined I/O APIC register %#x.\n", offset);
130    }
131    DPRINTF(I82094AA,
132            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
133}
134
135uint32_t
136X86ISA::I82094AA::readReg(uint8_t offset)
137{
138    uint32_t result = 0;
139    if (offset == 0x0) {
140        result = id << 24;
141    } else if (offset == 0x1) {
142        result = ((TableSize - 1) << 16) | APICVersion;
143    } else if (offset == 0x2) {
144        result = arbId << 24;
145    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
146        int index = (offset - 0x10) / 2;
147        if (offset % 2) {
148            result = redirTable[index].topDW;
149        } else {
150            result = redirTable[index].bottomDW;
151        }
152    } else {
153        warn("Access to undefined I/O APIC register %#x.\n", offset);
154    }
155    DPRINTF(I82094AA,
156            "Read %#x from I/O APIC register %#x.\n", result, offset);
157    return result;
158}
159
160void
161X86ISA::I82094AA::signalInterrupt(int line)
162{
163    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
164    assert(line < TableSize);
165    RedirTableEntry entry = redirTable[line];
166    if (entry.mask) {
167        DPRINTF(I82094AA, "Entry was masked.\n");
168        return;
169    } else {
170        TriggerIntMessage message = 0;
171        message.destination = entry.dest;
172        if (entry.deliveryMode == DeliveryMode::ExtInt) {
173            assert(extIntPic);
174            message.vector = extIntPic->getVector();
175        } else {
176            message.vector = entry.vector;
177        }
178        message.deliveryMode = entry.deliveryMode;
179        message.destMode = entry.destMode;
180        message.level = entry.polarity;
181        message.trigger = entry.trigger;
182        ApicList apics;
183        int numContexts = sys->numContexts();
184        if (message.destMode == 0) {
185            if (message.deliveryMode == DeliveryMode::LowestPriority) {
186                panic("Lowest priority delivery mode from the "
187                        "IO APIC aren't supported in physical "
188                        "destination mode.\n");
189            }
190            if (message.destination == 0xFF) {
191                for (int i = 0; i < numContexts; i++) {
192                    apics.push_back(i);
193                }
194            } else {
195                apics.push_back(message.destination);
196            }
197        } else {
198            for (int i = 0; i < numContexts; i++) {
199                std::map<int, Interrupts *>::iterator localApicIt =
200                    localApics.find(i);
201                assert(localApicIt != localApics.end());
202                Interrupts *localApic = localApicIt->second;
203                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
204                        message.destination) {
205                    apics.push_back(localApicIt->first);
206                }
207            }
208            if (message.deliveryMode == DeliveryMode::LowestPriority &&
209                    apics.size()) {
210                // The manual seems to suggest that the chipset just does
211                // something reasonable for these instead of actually using
212                // state from the local APIC. We'll just rotate an offset
213                // through the set of APICs selected above.
214                uint64_t modOffset = lowestPriorityOffset % apics.size();
215                lowestPriorityOffset++;
216                ApicList::iterator apicIt = apics.begin();
217                while (modOffset--) {
218                    apicIt++;
219                    assert(apicIt != apics.end());
220                }
221                int selected = *apicIt;
222                apics.clear();
223                apics.push_back(selected);
224            }
225        }
226        intPort->sendMessage(apics, message,
227                sys->getMemoryMode() == Enums::timing);
228    }
229}
230
231void
232X86ISA::I82094AA::raiseInterruptPin(int number)
233{
234    assert(number < TableSize);
235    if (!pinStates[number])
236        signalInterrupt(number);
237    pinStates[number] = true;
238}
239
240void
241X86ISA::I82094AA::lowerInterruptPin(int number)
242{
243    assert(number < TableSize);
244    pinStates[number] = false;
245}
246
247void
248X86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic)
249{
250    assert(localApic);
251    localApics[initialId] = localApic;
252}
253
254void
255X86ISA::I82094AA::serialize(std::ostream &os)
256{
257    uint64_t* redirTableArray = (uint64_t*)redirTable;
258    SERIALIZE_SCALAR(regSel);
259    SERIALIZE_SCALAR(initialApicId);
260    SERIALIZE_SCALAR(id);
261    SERIALIZE_SCALAR(arbId);
262    SERIALIZE_SCALAR(lowestPriorityOffset);
263    SERIALIZE_ARRAY(redirTableArray, TableSize);
264    SERIALIZE_ARRAY(pinStates, TableSize);
265}
266
267void
268X86ISA::I82094AA::unserialize(Checkpoint *cp, const std::string &section)
269{
270    uint64_t redirTableArray[TableSize];
271    UNSERIALIZE_SCALAR(regSel);
272    UNSERIALIZE_SCALAR(initialApicId);
273    UNSERIALIZE_SCALAR(id);
274    UNSERIALIZE_SCALAR(arbId);
275    UNSERIALIZE_SCALAR(lowestPriorityOffset);
276    UNSERIALIZE_ARRAY(redirTableArray, TableSize);
277    UNSERIALIZE_ARRAY(pinStates, TableSize);
278    for (int i = 0; i < TableSize; i++) {
279        redirTable[i] = (RedirTableEntry)redirTableArray[i];
280    }
281}
282
283X86ISA::I82094AA *
284I82094AAParams::create()
285{
286    return new X86ISA::I82094AA(this);
287}
288